CY62127BV_02 [CYPRESS]
1M (64K x 16) Static RAM; 1M （ 64K ×16 ）静态RAM
| 型号： | CY62127BV_02 |
| 厂家： | 
CYPRESS |
| 描述： | 1M (64K x 16) Static RAM |
| 文件： | 总11页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
CY62127BV MoBL
1M (64K x 16) Static RAM
significantly reduces power consumption when addresses are
not toggling, or when deselected (CE HIGH or both BLE and
BHE are HIGH). The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW, and WE LOW).
Features
• High Speed: 55 ns and 70 ns
• Wide voltage range: 2.7V–3.6V
• Low active power
— 54 mW (max.) (15 mA)
• Low standby power (70 ns)
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
— 54 µW (max.) (15 µA)
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package available in a 44-pin TSOP Type II (forward
pinout) and a 48-ball fBGA package
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description[1]
The CY62127BV MoBL® MoBL® is a high-performance
CMOS static RAM organized as 64K words by 16 bits. This
device features advanced circuit design to provide ultra-low
active current. This is ideal for providing More Battery Life
(MoBL) in portable applications such as cellular telephones.
The device also has an automatic power-down feature that
Logic Block Diagram
DATA IN DRIVERS
A
10
9
A
A
8
A
7
A
A
64K x 16
6
RAM Array
2048 X 512
I/O –I/O
5
0
7
A
4
I/O –I/O
A
8
15
3
A
A
2
1
A
0
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
Power -Down
Circuit
BHE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05155 Rev. *B
Revised August 27, 2002
®
CY62127BV MoBL
Pin Configurations[2]
FBGA (Top View)
TSOP II (Forward)
Top View
1
2
4
3
5
6
44
1
A
A
5
4
A
A
A
2
NC
OE
BLE
0
1
A
B
C
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
2
7
OE
A
A
A
4
I/O BHE
8
CE
I/O
I/O
0
1
3
BHE
BLE
I/O
A
0
CE
A
A
6
I/O I/O
I/O
2
5
I/O
9
10
1
7
0
15
37
36
35
34
33
I/O
I/O
8
I/O
I/O
1
2
14
13
12
9
V
NC
A
7
V
I/O
I/O
3
CC
D
E
F
SS
11
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
V
DNU NC
V
CC
SS
I/O
I/O
V
V
12
4
CC
32
I/O
I/O
I/O
4
5
6
7
11
10
31
30
29
28
I/O
I/O
I/O
14
15
16
A
A
15
I/O
I/O
I/O
I/O
6
14
13
5
14
I/O
I/O
9
8
WE 17
NC
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
18
27
26
25
A
A
8
15
19
A
A
14
13
9
10
11
A
A
A
A
A
20
21
22
A
A
NC
NC
10
9
11
8
A
12
24
23
NC
NC
DC Input Voltage[3].................................... −0.5V to VCC + 0.5V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential................. –0.5V to 4.6V
Ambient
DC Voltage Applied to Outputs
Range
Temperature
VCC
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
2.7V to 3.6V
Product Portfolio
Power Dissipation (Industrial)
Operating, ICC
VCC Range (V)
(mA) f = fmax
Standby, ISB2 (µA)
[4]
Product
VCC(min.) VCC(typ.)
2.7 3.0
VCC(max.)
Speed (ns)
Max.
20
Typ.[4]
Max.
CY62127BV
MoBL®
3.6
55
70
0.5
15
15
Notes:
2. NC pins are not connected to the die.
3. VIL(min.) = –2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05155 Rev. *B
Page 2 of 11
®
CY62127BV MoBL
Electrical Characteristics Over the Operating Range
CY62127BV
MoBL®-55
CY62127BV
MoBL®-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = 2.7V
VCC = 2.7V
2.2
2.2
V
V
V
VOL
0.4
0.4
VIH
2.0
VCC
+
2.0
VCC +
0.3V
0.4
+1
0.3V
0.4
+1
VIL
IIX
Input LOW Voltage
–0.3
–1
–0.3
–1
V
Input Leakage Current GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VI< VCC, Output Disabled
–1
+1
–1
+1
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC VCC = 3.6V
IOUT = 0 mA
20
2
15
2
mA
mA
CMOS Levels
ISB1
Automatic CE
Max. VCC, CE ≥ VIH
Power-Down
VIN ≥ VIH or VIN ≤ VIL, f = fMAX
Current— TTL Inputs
ISB2
Automatic CE
Power-Down
Current— CMOS
Inputs
Max. VCC, CE ≥ VCC – 0.3V,
IN ≥ VCC – 0.3V, or VIN ≤ 0.3V,
f = 0
0.5
15
0.5
15
V
µA
Capacitance[5]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Max.
Unit
pF
9
9
VCC = 3.3V
COUT
pF
Thermal Resistance
Description
Test Conditions
Symbol
BGA
Unit
Thermal Resistance
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board
ΘJA
55
°C/W
(Junction to Ambient)[5]
Thermal Resistance
(Junction to Case)[5]
ΘJC
16
°C/W
AC Test Loads and Waveforms
R1
V
ALL INPUT PULSES
90%
10%
CC
V
Typ
CC
OUTPUT
90%
10%
GND
Rise TIme: 1 V/ns
R2
30 pF
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05155 Rev. *B
Page 3 of 11
®
CY62127BV MoBL
Parameters
3.0V
1.076
1.262
0.581
1.620
Unit
R1
R2
K Ohms
K Ohms
K Ohms
Volts
RTH
VTH
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VCC for Data Retention
Conditions
Min. Typ.[4] Max. Unit
VDR
2.0
3.6
V
VCC= VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC
0.3V or VIN < 0.3V
–
ICCDR
Data Retention Current
0.5
15
µA
[5]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
[6]
tR
tRC
Data Retention Waveform[7]
DATA RETENTION MODE
3.0 V
3.0 V
V
> 2.0 V
V
CC
DR
t
t
R
CDR
CE or
BHE.BLE
[8]
Switching Characteristics Over the Operating Range
55 ns
70 ns
Parameter
Read Cycle
Description
Min.
55
Max.
Min.
70
Max.
Unit
tRC
Read Cycle Time
Address to Data Valid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
10
10
55
25
70
35
OE LOW to Data Valid
OE LOW to Low Z[9]
OE HIGH to High Z[9, 11]
CE LOW to Low Z[9]
CE HIGH to High Z[9, 11]
5
10
0
5
10
0
20
20
25
25
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z[9]
BHE / BLE HIGH to High Z[9, 11]
55
55
70
70
tDBE
[10]
tLZBE
5
5
tHZBE
20
25
Write Cycle[12]
tWC
Write Cycle Time
55
45
70
60
ns
ns
tSCE
CE LOW to Write End
Notes:
6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
10. If both byte enables are toggled together this value is 10 ns.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05155 Rev. *B
Page 4 of 11
®
CY62127BV MoBL
Switching Characteristics Over the Operating Range (continued)[8]
55 ns
70 ns
Parameter
Description
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Min.
45
0
Max.
Min.
60
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAW
tHA
tSA
0
0
tPWE
tBW
tSD
40
45
25
0
50
60
30
0
BHE / BLE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[9, 11]
WE HIGH to Low Z[9]
tHD
tHZWE
tLZWE
25
25
5
5
Switching Waveforms
[13, 14]
Read Cycle No. 1 (Address Transition Controlled)
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
tDOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
I
CC
CC
SUPPLY
CURRENT
50%
50%
I
SB
Notes:
13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL
14. WE is HIGH for read cycle.
.
15. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05155 Rev. *B
Page 5 of 11
®
CY62127BV MoBL
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[12, 16, 17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATA
DATA I/O
VALID
IN
NOTE
18
t
HZOE
[12, 16, 17]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
t
PWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATA
DATA I/O
IN
NOTE
18
t
HZOE
Notes:
16. Data I/O is high-impedance if OE = VIH
.
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05155 Rev. *B
Page 6 of 11
®
CY62127BV MoBL
Switching Waveforms (continued)
[17]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 18
DATAI/O
DATA VALID
IN
t
LZWE
t
HZWE
[17]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
BW
BHE/BLE
WE
t
SA
t
PWE
t
SD
t
HD
DATA I/O
VALID
DATA
NOTE 18
IN
Truth Table
CE
H
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
Mode
Power
High Z
Deselect/Power-Down
Deselect/Power-Down
Read
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
)
X
X
H
H
High Z
)
L
H
L
L
L
Data Out (I/OO–I/O15
)
)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
L
H
H
H
H
L
L
L
High Z
High Z
Output Disabled
Output Disabled
Active (ICC
)
H
Active (ICC
)
Document #: 38-05155 Rev. *B
Page 7 of 11
®
CY62127BV MoBL
Truth Table (continued)
CE
L
WE
H
L
OE
H
BHE
L
BLE
H
Inputs/Outputs
Mode
Power
High Z
Data In (I/OO–I/O15
Data In (I/OO–I/O7)
Output Disabled
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
L
X
L
L
)
Write
)
L
L
X
H
L
Write Lower Byte Only
Write Upper Byte Only
)
L
L
X
L
H
Data In (I/O8–I/O15
)
)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY62127BVLL-55ZI
CY62127BVLL-70ZI
CY62127BVLL-70BAI
CY62127BVLL-70BVI
Package Type
55
Z44
44-lead TSOP II
Industrial
70
BA48A
BV48A
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Package Diagrams
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-* E
Document #: 38-05155 Rev. *B
Page 8 of 11
®
CY62127BV MoBL
Package Diagrams (continued)
44-pin TSOP II Z44
51-85087-A
Document #: 38-05155 Rev. *B
Page 9 of 11
®
CY62127BV MoBL
Package Diagrams (continued)
.
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-**
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company
names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05155 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
®
CY62127BV MoBL
Document Title: CY62127BV MoBL® 1M (64K x 16) Static RAM
Document Number: 38-05155
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
*A
*B
109899
113307
116362
10/02/01
03/01/02
09/04/02
SZV
MGN
GBI
Change from Spec number: 38-01018 to 38-05155
Format standardization & update ordering information
Add footnote 1 and BV Package.
Document #: 38-05155 Rev. *B
Page 11 of 11
相关型号：
©2020 ICPDF网 联系我们和版权申明