概述
数据手册CY62136CV30_06 概述
2-Mbit (128K x 16) Static RAM 2兆位（ 128K ×16 ）静态RAM
CY62136CV30_06 数据手册
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PDF下载CY62136CV30 MoBL®
2-Mbit (128K x 16) Static RAM
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O0 through
Features
• Very high speed
— 55 ns
• Voltage range
— 2.7V – 3.3V
I/O15) are placed in a high-impedance state when: deselected
• Pin-compatible with the CY62136V
• Ultra-low active power
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW, and WE LOW).
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 7 mA @ f = fMax (55 ns speed)
• Low standby power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball VFBGA
package
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description[1]
The CY62136CV30 is high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
128K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
A3
A2
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05199 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 19, 2006
CY62136CV30 MoBL®
Product Portfolio
Power Dissipation
Operating, ICC (mA)
f = 1 MHz f = fMax
Typ.[2] Max. Typ.[2] Max. Typ.[2]
VCC Range (V)
Standby, ISB2 (µA)
Speed
(ns)
[2]
Product
VCC(min.) VCC(typ.)
VCC(max.)
Max.
CY62136CV30LL
2.7
3.0
3.3
55
70
1.5
1.5
3
3
7
15
12
2
10
5.5
Pin Configuration[3, 4]
48-ball VFBGA
Top View
1
4
3
2
5
6
A
A
A
2
NC
I/O
OE
BLE
0
1
A
B
C
A
A
I/O BHE
CE
I/O
4
3
0
8
A
A
6
I/O
I/O
2
I/O
5
10
1
9
VCC
VSS
NC
A
7
V
I/O
I/O
3
D
E
F
SS
11
DNU
A
16
V
CC
I/O
I/O
12
4
A
A
15
I/O
I/O
5
I/O
I/O
14
13
14
6
A
A
G
H
I/O
NC
WE
I/O
13
12
15
7
A
A
A
A
NC
NC
10
9
11
8
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ.)
3. NC pins are not connected to the die.
4. E3 (DNU) pin have to be left floating or tied to V to ensure proper operation.
SS
Document #: 38-05199 Rev. *E
Page 2 of 12
CY62136CV30 MoBL®
DC Input Voltage[5] ................................ –0.5V to VCC + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential–0.5V to VCC(max) + 0.5V
Ambient
DC Voltage Applied to Outputs
Device
Range
Temperature
VCC
in High-Z State[5] ....................................–0.5V to VCC + 0.3V
CY62136CV30 Industrial –40°C to +85°C 2.7V to 3.3V
Electrical Characteristics Over the Operating Range
CY62136CV30-55
CY62136CV30-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = –1.0 mA
IOL = 2.1 mA
VCC = 2.7V
VCC = 2.7V
2.4
2.2
2.4
2.2
V
V
V
VOL
0.4
0.4
VIH
VCC
+
VCC +
0.3V
0.3V
0.8
+1
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8
+1
+1
–0.3
–1
V
Input Leakage Current GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled –1
–1
+1
ICC
VCC Operating Supply f = fMax = 1/tRC
VCC = 3.3V
OUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
Current
I
f = 1 MHz
1.5
ISB1
Automatic CE
CE > VCC – 0.2V
2
10
2
10
µA
Power-downCurrent— VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs
Automatic CE
f = fMax (Address and Data Only),
f = 0 (OE, WE, BHE, and BLE)
ISB2
CE > VCC – 0.2V
2
10
2
10
µA
Power-downCurrent— VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs f = 0, VCC = 3.3V
Capacitance[7]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = VCC(typ.)
6
8
pF
pF
COUT
Output Capacitance
Thermal Resistance[7]
Parameter
Description
Test Conditions
VFBGA
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch,
2-layer printed circuit board
55
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
16
°C/W
Notes:
5. V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full Device AC operation requires linear V ramp from V to V > 100 µs or stable at V > 100 µs.
CC(min.)
CC
DR
CC(min.)
Document #: 38-05199 Rev. *E
Page 3 of 12
CY62136CV30 MoBL®
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC Typ
GND
90%
10%
OUTPUT
90%
10%
R2
30 pF
Rise TIme: 1 V/ns
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
3.0V
1105
1550
645
Unit
Ω
R1
R2
Ω
RTH
VTH
Ω
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Typ.[2]
Max.
Unit
1.5
Vcc(max)
V
VCC= 1.5V, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
1
6
µA
[7]
tCDR
Chip Deselect to Data
Retention Time
0
ns
[7]
tR
Operation Recovery Time
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VCC(min)
V
> 1.5 V
V
CC
DR
t
t
R
CDR
CE
Document #: 38-05199 Rev. *E
Page 4 of 12
CY62136CV30 MoBL®
Switching Characteristics Over the Operating Range[8]
55 ns
70 ns
Parameter
Read Cycle
Description
Min.
55
Max.
Min.
70
Max.
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
10
10
55
25
70
35
OE LOW to Data Valid
OE LOW to Low-Z[9]
5
10
0
5
10
0
OE HIGH to High-Z[9, 10]
CE LOW to Low-Z[9]
20
20
25
25
CE HIGH to High-Z[9, 10]
CE LOW to Power-up
tPD
CE HIGH to Power-down
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z[9]
BHE/BLE HIGH to High-Z[9, 10]
55
25
70
35
tDBE
tLZBE
tHZBE
Write Cycle[11]
tWC
5
5
20
25
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tBW
40
50
25
0
45
60
30
0
BHE/BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9, 10]
WE HIGH to Low-Z[9]
tSD
tHD
tHZWE
tLZWE
20
25
10
10
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the
CC(typ.)
CC(typ.)
specified I /I and 30 pF load capacitance.
OL OH
9. At any given temperature and voltage condition, t
given device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
10. It
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
11. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any
IL
IL
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05199 Rev. *E
Page 5 of 12
CY62136CV30 MoBL®
Switching Waveforms
Read Cycle No. 1(Address Transition Controlled)[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
tDOE
t
LZOE
BHE/BLE
t
HZBE
tDBE
LZBE
t
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
I
CC
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
12. Device is continuously selected. OE, CE = V , BHE, BLE = V
.
IL
IL
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05199 Rev. *E
Page 6 of 12
CY62136CV30 MoBL®
Switching Waveforms
Write Cycle No. 1 (WE Controlled)[11, 15, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATA VALID
DATA I/O
NOTE17
IN
t
HZOE
Write Cycle No. 2 (CE Controlled)[11, 15, 16]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATA I/O
DATAIN
NOTE
17
t
HZOE
Notes:
15. Data I/O is high-impedance if OE = V
IH
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05199 Rev. *E
Page 7 of 12
CY62136CV30 MoBL®
Switching Waveforms
Write Cycle No. 3 (WE Controlled, OE LOW)[16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
BW
BHE/BLE
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 17
DATA I/O
DATA VALID
IN
t
t
LZWE
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
BW
BHE/BLE
WE
t
SA
t
PWE
t
t
HD
SD
NOTE 17
DATA VALID
IN
DATA I/O
t
t
LZWE
HZWE
Document #: 38-05199 Rev. *E
Page 8 of 12
CY62136CV30 MoBL®
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
CC
, T = 25°C)
A
CC(typ.)
Operating Current vs. Supply Voltage
14.0
12.0
14.0
12.0
10.0
10.0
MoBL
MoBL
(f = fMax
55 ns)
,
,
(f = fMax
55 ns)
,
8.0
6.0
4.0
8.0
6.0
4.0
(f = fMax
70 ns)
,
(f = fMax
70 ns)
2.0
0.0
2.0
0.0
(f = 1 MHz)
(f = 1 MHz)
3.6
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
3.3
3.0
2.7
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
12.0
MoBL
10.0
8.0
10.0
8.0
MoBL
6.0
4.0
2.0
0
6.0
4.0
2.0
0
3.3
3.0
2.7
3.3
3.0
3.6
2.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
50
40
30
60
MoBL
MoBL
50
40
30
20
20
10
0
10
0
3.6
2.7
3.3
3.0
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Document #: 38-05199 Rev. *E
Page 9 of 12
CY62136CV30 MoBL®
Truth Table
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
Mode
Power
High-Z
High-Z
Deselect/Power-down Standby (ISB
)
X
X
H
H
Output Disabled
Read
Active (ICC
Active (ICC
Active (ICC
)
L
H
L
L
L
Data Out (I/O0–I/O15
)
)
L
H
L
H
L
High Z (I/O8–I/O15);
Data Out (I/O0–I/O7)
Read
)
L
H
L
L
H
Data Out (I/O8–I/O15);
High Z (I/O0–I/O7)
Read
Active (ICC)
L
L
L
L
X
X
L
L
L
Data In (I/O0–I/O15
)
Write
Write
Active (ICC
)
H
High Z (I/O8–I/O15);
Data In (I/O0–I/O7)
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
High Z (I/O0–I/O7)
Write
Active (ICC)
L
L
L
H
H
H
H
H
H
L
H
L
L
L
High-Z
High-Z
High-Z
Output Disabled
Output Disabled
Output Disabled
Active (ICC
Active (ICC
Active (ICC
)
)
H
)
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
55
CY62136CV30LL-55BVI
51-85150 48-ball Fine Pitch BGA (6 x 8 x 1 mm)
48-ball Fine Pitch BGA (6 x 8 x 1 mm) Pb-free
Industrial
70
CY62136CV30LL-70BVXI
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05199 Rev. *E
Page 10 of 12
CY62136CV30 MoBL®
Package Diagram
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05ꢀ(48X
A1 CORNER
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
51-85150-*D
SEATING PLANE
C
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05199 Rev. *E
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62136CV30 MoBL®
Document History Page
Document Title: CY62136CV30 2-Mbit (128K x 16) Static RAM
Document Number: 38-05199
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
112379
114023
Description of Change
New Data Sheet (advance information)
Added BV package diagram
02/19/02
04/25/02
GAV
JUI
*A
Changed Advance Information to Preliminary
*B
*C
117063
118121
07/12/02
08/26/02
MGN
MGN
Changed Preliminary to Final
Added new part numbers: CY62136CV with wider voltage (2.7V – 3.6V);
CY62136CV33 narrower voltage range (3.0V – 3.6V)
For TAA = 55 ns, improved tPWE Min from 45 ns to 40 ns
For TAA = 70 ns, improved tPWE Min from 50 ns to 45 ns
For TAA = 70 ns, improved tLZWE Min from 5 ns to 10 ns
*D
*E
118622
486789
10/3/02
MGN
VKN
Improved Typ. ICC spec. to 7 mA (for 55 ns) and 5.5 mA (for 70 ns)
Improved Max ICC spec. to 15 mA (for 55 ns) and 12 mA (for 70 ns)
For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns
Changed upper spec. for Supply Voltage to Ground Potential to VCC(max) + 0.5V
Changed upper spec. for DC Voltage Applied to Outputs in High-Z State and DC
Input Voltage to VCC + 0.3V
SEE ECN
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed Part numbers: CY62136CV and CY62136CV33
Updated Ordering Information table
Document #: 38-05199 Rev. *E
Page 12 of 12
CY62136CV30_06 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CY62136CV33 | CYPRESS | 2M (128K x 16) Static RAM | 获取价格 |
|
| CY62136CV33LL-55BAI | CYPRESS | 2M (128K x 16) Static RAM | 获取价格 |
|
| CY62136CV33LL-55BAIT | CYPRESS | Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48 | 获取价格 |
|
| CY62136CV33LL-55BVI | CYPRESS | 2M (128K x 16) Static RAM | 获取价格 |
|
| CY62136CV33LL-70BAI | CYPRESS | 2M (128K x 16) Static RAM | 获取价格 |
|
| CY62136CV33LL-70BVI | CYPRESS | 2M (128K x 16) Static RAM | 获取价格 |
|
| CY62136CV33LL-70BVIT | CYPRESS | Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 | 获取价格 |
|
| CY62136CVLL-70BAI | CYPRESS | 2M (128K x 16) Static RAM | 获取价格 |
|
| CY62136CVLL-70BAIT | CYPRESS | Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48 | 获取价格 |
|
| CY62136CVLL-70BVI | CYPRESS | 2M (128K x 16) Static RAM | 获取价格 |
|
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