CY62136CVLL-70BAIT [CYPRESS]
Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48;
| 型号： | CY62136CVLL-70BAIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62136CV30/33 MoBL
CY62136CV MoBL
2M (128K x 16) Static RAM
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O0 through
Features
• Very high speed: 55 ns and 70 ns
• Voltage range:
— CY62136CV30: 2.7V–3.3V
— CY62136CV33: 3.0V–3.6V
— CY62136CV: 2.7V–3.6V
I/O15) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW, and WE LOW).
• Pin-compatible with the CY62136V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
— Typical active current: 5.5 mA @ f = fmax (70-ns
speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball FBGA
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description[1]
The and CY62136CV are high-performance CMOS static
RAM organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
7
6
A
A
A
A
A
128K x 16
5
4
RAM Array
I/O –I/O
0
7
2048 x 1024
3
2
I/O –I/O
A
8
15
A
A
1
0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05199 Rev. *D
Revised September 20, 2002
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CY62136CV30/33 MoBL
CY62136CV MoBL
Pin Configuration[2, 3]
FBGA (Top View)
1
2
4
3
5
6
A
A
A
2
NC
OE
BLE
0
1
A
B
C
A
A
4
I/O BHE
8
CE
I/O
I/O
0
3
A
A
6
I/O I/O
I/O
2
5
9
10
1
V
NC
A
7
V
I/O
I/O
3
CC
D
E
F
SS
11
V
DNU
A
16
V
CC
SS
I/O
I/O
12
4
A
A
15
I/O
I/O
I/O
I/O
6
14
13
5
14
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
A
A
9
A
A
NC
NC
10
11
8
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Temperature
Device
Range
VCC
Supply Voltage to Ground Potential –0.5V to VCCMAX + 0.5V
CY62136CV30 Industrial –40°C to +85°C 2.7V to 3.3V
DC Voltage Applied to Outputs
CY62136CV33
CY62136CV
3.0V to 3.6V
2.7V to 3.6V
in High-Z State[4] ....................................–0.5V to VCC + 0.3V
DC Input Voltage[4].................................–0.5V to VCC + 0.3V
Output Current into Outputs (LOW) .............................20 mA
Product Portfolio
Power Dissipation
Operating, ICC (mA)
f = 1 MHz f = fmax
Typ.[5] Max. Typ.[5] Max. Typ.[5]
V
CC Range (V)
Standby, ISB2 (µA)
Speed
(ns)
[5]
Product
VCC(min.) VCC(typ.)
VCC(max.)
Max.
CY62136CV30LL
2.7
3.0
2.7
3.0
3.3
3.3
3.3
55
70
55
70
70
1.5
1.5
1.5
1.5
1.5
3
3
3
3
3
7
15
12
15
12
12
2
5
5
10
5.5
7
CY62136CV33LL
3.6
3.6
15
15
5.5
5.5
CY62136CVLL
Notes:
2. NC pins are not connected to the die.
3. E3 (DNU) can be left as NC or VSS to ensure proper application.
4. VIL(min.) = –2.0V for pulse durations less than 20 ns.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05199 Rev. *D
Page 2 of 13
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CY62136CV30/33 MoBL
CY62136CV MoBL
Electrical Characteristics Over the Operating Range
CY62136CV30-55
CY62136CV30-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[5] Max. Min. Typ.[5] Max. Unit
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = 2.7V
VCC = 2.7V
2.4
2.4
V
V
V
VOL
0.4
0.4
VIH
2.2
VCC
+
2.2
VCC +
0.3V
0.3V
0.8
+1
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8
+1
+1
–0.3
–1
V
Input Leakage Current GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled –1
–1
+1
ICC
VCC Operating Supply f = fMAX = 1/tRC
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
Current
f = 1 MHz
1.5
ISB1
Automatic CE
CE > VCC – 0.2V
2
10
2
10
µA
Power-down Current VIN > VCC – 0.2V or VIN < 0.2V, f
— CMOS Inputs
= fmax (Address and Data Only), f
= 0 (OE, WE, BHE, and BLE)
ISB2
Automatic CE
Power-down Current VIN > VCC – 0.2V or VIN < 0.2V,
CE > VCC – 0.2V
— CMOS Inputs
f = 0, VCC = 3.3V
CY62136CV33-70
CY62136CV-70
CY62136CV33-55
Parameter
Description
Test Conditions
Min. Typ.[5] Max. Min. Typ.[5] Max. Unit
VOH
Output HIGH Voltage IOH = –1.0 mA
VCC = 3.0V
CC = 2.7V
2.4
2.4
2.4
V
V
V
V
V
V
VOL
VIH
Output LOW Voltage IOL = 2.1 mA
VCC = 3.0V
VCC = 2.7V
0.4
0.4
0.4
Input HIGH Voltage
Input LOW Voltage
2.2
VCC
+
2.2
VCC +
0.3V
0.3V
0.8
+1
VIL
IIX
–0.3
–1
0.8
+1
–0.3
–1
V
Input Leakage
Current
GND < VI < VCC
GND < VO < VCC, Output Disabled
µA
IOZ
ICC
Output Leakage
Current
–1
+1
–1
+1
µA
VCC Operating
Supply Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
1.5
ISB1
Automatic CE
Power-down Current VIN > VCC – 0.2V or VIN < 0.2V,
CE > VCC – 0.2V
5
15
5
15
µA
—CMOS Inputs
f = fmax (Address and Data Only),
f = 0 (OE, WE, BHE, and BLE)
ISB2
Automatic CE
Power-down Current VIN > VCC – 0.2V or VIN < 0.2V,
CE > VCC – 0.2V
—CMOS Inputs
f = 0, VCC = 3.6V
Capacitance[6]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
Max.
Unit
CIN
Input Capacitance
Output Capacitance
6
8
pF
pF
COUT
Document #: 38-05199 Rev. *D
Page 3 of 13
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CY62136CV30/33 MoBL
CY62136CV MoBL
Thermal Resistance
Parameter
Description
Test Conditions
BGA
Unit
ΘJA
Thermal Resistance
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
55
°C/W
(Junction to Ambient)[6]
ΘJC
Thermal Resistance
(Junction to Case)[6]
16
°C/W
AC Test Loads and Waveforms
R1
V
ALL INPUT PULSES
CC
V
Typ
CC
OUTPUT
90%
10%
90%
10%
GND
Rise TIme: 1 V/ns
R2
30 pF
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
3.0V
1105
1550
645
3.3V
1216
1374
645
Unit
Ω
R1
R2
Ω
RTH
VTH
Ω
1.75
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Typ.[5]
Max.
Unit
1.5
Vccmax
V
VCC= 1.5V CE > VCC – 0.2V,
IN > VCC – 0.2V or VIN < 0.2V
1
6
µA
ns
V
[6]
tCDR
Chip Deselect to Data
Retention Time
0
[7]
tR
Operation Recovery Time
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
> 1.5 V
VCC(min)
VCC(min)
V
V
CC
DR
t
t
R
CDR
CE
Notes:
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
Document #: 38-05199 Rev. *D
Page 4 of 13
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CY62136CV30/33 MoBL
CY62136CV MoBL
Switching Characteristics Over the Operating Range[8]
55 ns
70 ns
Parameter
Read Cycle
Description
Read Cycle Time
Min.
55
Max.
Min.
70
Max.
Unit
tRC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
10
10
55
25
70
35
OE LOW to Data Valid
OE LOW to Low-Z[9]
OE HIGH to High-Z[9, 10]
CE LOW to Low-Z[9]
CE HIGH to High-Z[9, 10]
5
10
0
5
10
0
20
20
25
25
CE LOW to Power-up
tPD
CE HIGH to Power-down
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z[9]
BHE/BLE HIGH to High-Z[9, 10]
55
25
70
35
tDBE
tLZBE
tHZBE
Write Cycle[11]
tWC
5
5
20
25
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tBW
40
50
25
0
45
60
30
0
BHE/BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9, 10]
WE HIGH to Low-Z[9]
tSD
tHD
tHZWE
tLZWE
20
25
10
10
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
Notes:
PREVIOUS DATA VALID
DATA VALID
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
10. ItHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
12. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL
13. WE is HIGH for read cycle.
.
Document #: 38-05199 Rev. *D
Page 5 of 13
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CY62136CV30/33 MoBL
CY62136CV MoBL
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
tDOE
BHE/BLE
t
LZOE
t
HZBE
tDBE
LZBE
t
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
I
CC
CC
SUPPLY
CURRENT
50%
50%
I
SB
[11, 15, 16]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATA VALID
DATA I/O
NOTE17
IN
t
HZOE
Notes:
14. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
15. Data I/O is high-impedance if OE = VIH
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05199 Rev. *D
Page 6 of 13
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CY62136CV30/33 MoBL
CY62136CV MoBL
Switching Waveforms (continued)
[11, 15, 16]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
t
PWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATA I/O
DATA
IN
NOTE
17
t
HZOE
[16]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 17
DATAI/O
DATA VALID
IN
t
LZWE
t
HZWE
Document #: 38-05199 Rev. *D
Page 7 of 13
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CY62136CV30/33 MoBL
CY62136CV MoBL
Switching Waveforms (continued)
[16]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
BW
BHE/BLE
WE
t
SA
t
PWE
t
t
HD
SD
DATA I/O
VALID
DATA
NOTE 17
IN
Document #: 38-05199 Rev. *D
Page 8 of 13
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CY62136CV30/33 MoBL
CY62136CV MoBL
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C)
Operating Current vs. Supply Voltage
14.0
12.0
14.0
12.0
10.0
10.0
MoBL
MoBL
(f = f
55 ns)
,
,
(f = f
55 ns)
,
max
max
8.0
6.0
4.0
8.0
6.0
4.0
(f = f
70 ns)
,
max
(f = f
70 ns)
max
2.0
0.0
2.0
0.0
(f = 1 MHz)
(f = 1 MHz)
3.6
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
3.3
3.0
2.7
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
12.0
MoBL
10.0
8.0
10.0
8.0
MoBL
6.0
4.0
2.0
0
6.0
4.0
2.0
0
3.3
3.0
2.7
3.3
3.0
3.6
2.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
50
40
30
60
MoBL
MoBL
50
40
30
20
20
10
0
10
0
3.6
2.7
3.3
3.0
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Truth Table
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High-Z
High-Z
Mode
Deselect/Power-down
Output Disabled
Read
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
X
X
H
H
)
L
H
L
L
L
Data Out (I/OO–I/O15
)
)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High-Z
Read
)
L
L
H
H
L
L
L
H
L
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC
)
H
High-Z
Output Disabled
Active (ICC)
Document #: 38-05199 Rev. *D
Page 9 of 13
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CY62136CV30/33 MoBL
CY62136CV MoBL
Truth Table (continued)
CE
L
WE
H
OE
H
BHE
H
BLE
L
Inputs/Outputs
High-Z
Mode
Output Disabled
Power
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
L
H
H
L
H
High-Z
Output Disabled
Write
)
L
L
X
L
L
Data In (I/OO–I/O15
)
)
L
L
X
H
L
Data In (I/OO–I/O7);
I/O8–I/O15 in High-Z
Write
)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
Ordering Information
Speed
Voltage
Package
Name
Operating
Range
(ns)
Ordering Code
Range (V)
2.7–3.3
2.7–3.3
3.0–3.6
3.0–3.6
2.7–3.6
2.7–3.6
2.7–3.3
2.7–3.3
3.0–3.6
3.0–3.6
Package Type
70
CY62136CV30LL-70BAI
CY62136CV30LL-70BVI
CY62136CV33LL-70BAI
CY62136CV33LL-70BVI
CY62136CVLL-70BAI
CY62136CVLL-70BVI
CY62136CV30LL-55BAI
CY62136CV30LL-55BVI
CY62136CV33LL-55BAI
CY62136CV33LL-55BVI
BA48A
BV48A
BA48A
BV48A
BA48A
BV48A
BA48A
BV48A
BA48A
BV48A
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Industrial
55
Document #: 38-05199 Rev. *D
Page 10 of 13
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CY62136CV30/33 MoBL
CY62136CV MoBL
Package Diagrams
48-ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
Document #: 38-05199 Rev. *D
Page 11 of 13
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CY62136CV30/33 MoBL
CY62136CV MoBL
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05199 Rev. *D
Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
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CY62136CV30/33 MoBL
CY62136CV MoBL
Document History Page
Document Title: CY62136CV30/33/CY62136CV/CY62136CV30/33 2M (128K x 16) Static RAM
Document Number: 38-05199
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
112379
114023
Description of Change
New Data Sheet (advance information)
02/19/02
04/25/02
GAV
JUI
*A
Added BV package diagram
Changed Advance Information to Preliminary
*B
*C
117063
118121
07/12/02
08/26/02
MGN
MGN
Changed Preliminary to Final
Added new part numbers: CY62136CV with wider voltage (2.7V – 3.6V);
CY62136CV33 narrower voltage range (3.0V – 3.6V)
For TAA = 55 ns, improved tPWE Min from 45 ns to 40 ns
For TAA = 70 ns, improved tPWE Min from 50 ns to 45 ns
For TAA = 70 ns, improved tLZWE Min from 5 ns to 10 ns
*D
118622
10/3/02
MGN
Improved Typ. ICC spec. to 7 mA (for 55 ns) and 5.5 mA (for 70 ns)
Improved Max ICC spec. to 15 mA (for 55 ns) and 12 mA (for 70 ns)
For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns
Changed upper spec. for Supply Voltage to Ground Potential to VCCMAX + 0.5V
Changed upper spec. for DC Voltage Applied to Outputs in High-Z State and DC
Input Voltage to VCC + 0.3V
Document #: 38-05199 Rev. *D
Page 13 of 13
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