CY62136EV30LL-45BVXI [CYPRESS]
2-Mbit (128K x 16) Static RAM; 2兆位（ 128K ×16 ）静态RAM
| 型号： | CY62136EV30LL-45BVXI |
| 厂家： | 
CYPRESS |
| 描述： | 2-Mbit (128K x 16) Static RAM |
| 文件： | 总12页 (文件大小：572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62136EV30
MoBL®
2-Mbit (128K x 16) Static RAM
Features
Functional Description[1]
• Very high speed: 45 ns
The CY62136EV30 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O0 through
I/O15) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW and WE LOW).
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62136CV30
• Ultra low standby power
— Typical standby current: 1µA
— Maximum standby current: 7µA
• Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
• Offered in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
128K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05569 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 6, 2006
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CY62136EV30
MoBL®
Pin Configuration[2, 3]
VFBGA (Top View)
44 TSOP II (Top View)
1
4
2
5
3
6
44
1
A
4
A
5
A
A
A
2
NC
43
42
41
40
39
38
A
A
OE
2
3
4
5
6
BLE
0
1
A
B
C
3
6
A
A
2
7
OE
A
1
A
A
I/O BHE
CE
I/O
I/O
0
3
4
8
BHE
BLE
I/O
I/O
I/O
A
0
CE
I/O
A
A
7
I/O
I/O
2
I/O
0
15
5
6
10
1
9
37
36
35
34
33
I/O
I/O
8
1
2
14
13
12
9
Vcc
Vss
A
V
SS
I/O
I/O
3
NC
NC
D
E
F
7
11
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
V
V
A
V
CC
CC
I/O
I/O
16
12
4
32
I/O
I/O
I/O
4
5
6
7
11
10
31
30
29
28
I/O
I/O
I/O
14
15
16
A
A
15
I/O
I/O
5
I/O
I/O
I/O
14
13
14
6
9
8
I/O
NC
WE 17
18
A
A
G
H
I/O
NC
WE
I/O
7
13
12
27
26
25
15
A
16
A
8
19
20
21
22
A
14
A
9
15
A
A
11
10
A
A
A
A
NC
NC
10
9
11
8
A
A
12
24
23
13
A
NC
Product Portfolio[4]
Power Dissipation
Operating ICC (mA)
f = 1MHz f = fmax Standby ISB2 (µA)
Speed
(ns)
Product
VCC Range (V)
Typ.[4]
Min.
2.2
Max.
Typ.[4]
Max.
Typ.[4]
Max.
Typ.[4]
Max.
CY62136EV30LL
3.0
3.6
45
2
2.5
15
20
1
7
Notes:
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, and H6 in the BGA package are address expansion pins for 4 Mbit, 8 Mbit, 16 Mbit and 32 Mbit, respectively.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ.)
Document #: 38-05569 Rev. *B
Page 2 of 12
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CY62136EV30
MoBL®
DC Input Voltage[5,6]............ –0.3V to 3.9V (VCC MAX + 0.3V)
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................–65°C to + 150°C
Latch-up Current ....................................................> 200 mA
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Operating Range[7]
Ambient
Temperature
Supply Voltage to Ground
Potential ..............................–0.3V to 3.9V (VCC MAX + 0.3V)
[7]
Device
Range
VCC
CY62136EV30LL Industrial –40°Cto+85°C 2.2V - 3.6V
DC Voltage Applied to Outputs
in High-Z State[5,6]................–0.3V to 3.9V (VCC MAX + 0.3V)
Electrical Characteristics Over the Operating Range [5, 6, 7]
45 ns
Parameter
Description
Output HIGH
Voltage
Test Conditions
IOH = –0.1 mA VCC = 2.20V
IOH = –1.0 mA VCC = 2.70V
Min.
2.0
Typ.[4]
Max.
Unit
V
VOH
2.4
V
VOL
VIH
VIL
Output LOW
Voltage
IOL = 0.1 mA
IOL = 2.1mA
VCC = 2.20V
VCC = 2.70V
0.4
0.4
V
V
Input HIGH Voltage VCC = 2.2V to 2.7V
VCC= 2.7V to 3.6V
1.8
2.2
VCC + 0.3
VCC + 0.3
0.6
V
V
Input LOW Voltage VCC = 2.2V to 2.7V
VCC= 2.7V to 3.6V
–0.3
–0.3
–1
V
0.8
V
IIX
Input Leakage
Current
GND < VI < VCC
+1
µA
IOZ
ICC
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
+1
µA
VCC Operating
Supply Current
f = fMAX = 1/tRC VCC = VCCmax, OUT
I
= 0 mA
15
2
20
2.5
7
mA
CMOS levels
f = 1 MHz
ISB1
Automatic CE
Power-down
CE > VCC−0.2V,
VIN>VCC–0.2V, VIN<0.2V)
1
µA
Current — CMOS f = fMAX (Address and Data Only),
Inputs
f = 0 (OE, and WE),
VCC = 3.60V
ISB2
Automatic CE
Power-down
Current — CMOS
Inputs
CE > VCC – 0.2V,
1
7
µA
VIN > VCC – 0.2V or VIN < 0.2V, f = 0,
CC = 3.60V
V
Capacitance (for all packages)[8]
Parameter
Description
Test Conditions
Max.
10
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
CC = VCC(typ)
pF
pF
V
COUT
10
Notes:
5. V
6. V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
=V +0.75V for pulse durations less than 20ns.
IH(max)
CC
7. Full Device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after V stabilization.
CC
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05569 Rev. *B
Page 3 of 12
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CY62136EV30
MoBL®
Thermal Resistance[8]
VFBGA
Package
TSOP II
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
75
77
°C/W
(Junction to Ambient)[8]
ΘJC
Thermal Resistance
(Junction to Case)[8]
10
13
°C/W
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
VCC
OUTPUT
VCC
90%
10%
GND
Rise Time = 1 V/ns
R2
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.50V
16667
15385
8000
3.0V
1103
1554
645
Unit
Ω
R1
R2
Ω
RTH
VTH
Ω
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)[8, 9]
Parameter
VDR
ICCDR
Description
Conditions
Min.
Typ.[4]
Max.
Unit
V
VCC for Data Retention
1.0
Data Retention Current VCC= 1.0V
0.8
3
µA
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
[8]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[9]
tR
Operation Recovery
Time
tRC
Data Retention Waveform
DATA RETENTION MODE
> 1.0 V
VCC(min)
VCC(min)
V
V
CC
DR
t
t
R
CDR
CE
Notes:
9. Full device operation requires linear V ramp from V to V
> 100 µs or stable at V
> 100 µs.
CC(min.)
CC
DR
CC(min.)
Document #: 38-05569 Rev. *B
Page 4 of 12
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CY62136EV30
MoBL®
Switching Characteristics Over the Operating Range [10, 11, 12, 13]
45 ns
Parameter
Read Cycle
Description
Min.
45
Max.
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
45
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
10
45
22
OE LOW to Data Valid
OE LOW to LOW Z[11]
OE HIGH to High Z[11, 12]
CE LOW to Low Z[11]
CE HIGH to High Z[11, 12]
5
10
0
18
18
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z[11]
BLE/BHE HIGH to HIGH Z[11, 12]
45
22
tDBE
tLZBE
tHZBE
Write Cycle[13]
tWC
5
18
Write Cycle Time
45
35
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
tPWE
tBW
35
35
25
0
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z[11, 12]
WE HIGH to Low-Z[11]
tSD
tHD
tHZWE
18
tLZWE
10
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
CC(typ.)
OL OH
11. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
given device.
12. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedence state.
HZOE HZCE HZBE
HZWE
13. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any
IL
IL
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05569 Rev. *B
Page 5 of 12
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CY62136EV30
MoBL®
Switching Waveforms [14, 15]
Read Cycle 1 (Address Transition Controlled)[14, 15]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
I
CC
CC
SUPPLY
CURRENT
50%
50%
I
SB
Notes:
14. The device is continuously selected. OE, CE= V , BHE and/or BLE = V
.
IL
IL
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document #: 38-05569 Rev. *B
Page 6 of 12
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CY62136EV30
MoBL®
Switching Waveforms (continued)[14, 15]
Write Cycle No. 1 (WE Controlled)[13, 17, 18]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATAIN
DATA I/O
NOTE19
t
HZOE
Write Cycle No. 2 (CE Controlled)[13, 17, 18]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
NOTE 19
t
HZOE
Notes:
17. Data I/O is high impedance if OE = V
.
IH
18. If CE goes HIGH simultaneously with WE = V , the output remains in a high-impedance state.
IH
19. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05569 Rev. *B
Page 7 of 12
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CY62136EV30
MoBL®
Switching Waveforms (continued)[14, 15]
Write Cycle No. 3 (WE Controlled, OE LOW)[18]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
NOTE 19
DATAI/O
DATAIN
t
HZWE
t
LZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
tHD
t
SD
DATA I/O
DATAIN
NOTE 19
tLZWE
Document #: 38-05569 Rev. *B
Page 8 of 12
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CY62136EV30
MoBL®
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
High Z
Mode
Power
H
X
X
X
X
Deselect/Power-down
Standby (ISB)
L
L
L
X
H
H
X
L
L
H
L
H
L
L
High Z
Output Disabled
Read
Active (ICC
Active (ICC
Active (ICC
)
)
)
Data Out (I/OO–I/O15
)
H
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC
)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data In (I/OO–I/O15)
L
H
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC
)
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62136EV30LL-45BVXI
CY62136EV30LL-45ZSXI
51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
51-85087 44-pin Thin Small Outline Package II (Pb-free)
Industrial
Please contact your local Cypress sales representative for availability of other parts
Document #: 38-05569 Rev. *B
Page 9 of 12
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CY62136EV30
MoBL®
Package Diagrams
48-pin VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05ꢀ(48X
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
51-85150-*D
SEATING PLANE
C
Document #: 38-05569 Rev. *B
Page 10 of 12
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CY62136EV30
MoBL®
Package Diagrams (continued)
44-pin TSOP II (51-85087)
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05569 Rev. *B
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62136EV30
MoBL®
Document History Page
Document Title: CY62136EV30 MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 38-05569
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
237432
419988
See ECN
See ECN
AJU
New Data Sheet
*A
RXU
Converted from Advanced Information to Final.
Changed the address of Cypress Semiconductor Corporation on Page #1
from “3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62136EV30
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ. values from 0.7 µA to 1 µA and Max. values from
2.5 µA to 7 µA.
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed VDR from 1.5V to 1V on Page# 4.
Changed ICCDR from 2.5 µA to 3 µA.
Added ICCDR typical value.
Changed tOHA , tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tLZOE from 3 ns to 5 ns
Changed tHZOE, tHZCE, HZBE
t
and tHZWE from 15 ns to 18 ns
Changed tSCE, AW and BW from 40 ns to 35 ns
t
t
Changed tPWE from 30 ns to 35 ns
Changed tSD from 20 ns to 25 ns
Corrected typo in the Truth Table on Page# 9
Updated the package diagram 48-pin VFBGA from *B to *D
Updated the ordering Information table and replaced the Package Name
column with Package Diagram.
*B
427817
See ECN
NXR
Minor change: Moved datasheet to external web
Document #: 38-05569 Rev. *B
Page 12 of 12
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