CY62137CVSL-70BVIT [CYPRESS]
Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48;
| 型号： | CY62137CVSL-70BVIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
2M (128K x 16) Static RAM
Life™ (MoBL®) in portable applications such as cellular
telephones. The devices also has an automatic power-down
feature that significantly reduces power consumption by 80%
when addresses are not toggling. The device can also be put
into standby mode reducing power consumption by more than
99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE HIGH),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH), or during a
write operation (CE LOW, and WE LOW).
Features
• Very high speed: 55 ns and 70 ns
• Temperature Ranges
— Industrial: –40°C to +85°C
— Automotive: –40°C to +125°C
• Pin-compatible with the CY62137V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
— Typical active current: 5.5 mA @ f = fmax (70-ns
speed)
• Low and ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
• Offered in a lead-free and non-lead-free 48-ball FBGA
packages
Functional Description[1]
The CY62137CV25/30/33 and CY62137CV are high-perfor-
mance CMOS static RAMs organized as 128K words by 16
bits. These devices feature advanced circuit design to provide
ultra-low active current. This is ideal for providing More Battery
Logic Block Diagram
DATA IN DRIVERS
10
A10
A9
A8
A7
A6
A5
128K x 16
A4
A3
A2
RAM Array
2048 x 1024
I/O0–I/O7
I/O8–I/O15
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
Power-down
Circuit
BHE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05201 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 6, 2006
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Pin Configuration[2, 3]
48-ball FBGA Pinout
Top View
1
2
4
3
5
6
A
A
A
2
NC
I/O
OE
BLE
0
1
A
B
C
A
A
I/O BHE
CE
I/O
4
3
0
8
A
A
6
I/O
I/O
2
I/O
5
10
1
9
VCC
VSS
NC
A
7
V
I/O
I/O
3
D
E
F
SS
11
DNU
A
16
V
CC
I/O
I/O
12
4
A
A
15
I/O
I/O
I/O
I/O
14
13
5
14
6
A
A
G
H
I/O
I/O
NC
WE
13
12
15
7
A
A
A
A
NC
NC
10
9
11
8
Product Portfolio
Power Dissipation
Operating, ICC (mA)
f = 1 MHz f = fmax
Standby, ISB2
VCC Range (V)
Min. Typ.[4] Max.
(µA)
Speed
(ns)
Product
Range
Typ.[4] Max. Typ.[4] Max. Typ.[4] Max.
CY62137CV25LL Industrial
2.2
2.5
2.7
55
70
55
70
70
55
70
70
70
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3
3
3
3
3
3
3
3
3
7
15
12
15
12
15
15
12
12
12
2
10
5.5
7
CY62137CV30LL Industrial
2.7
3.0
3.3
2
10
5.5
5.5
7
CY62137CV30LL Automotive
CY62137CV33LL Industrial
2.7
3.0
3.0
3.3
3.3
3.6
2
5
15
15
5.5
5.5
5.5
CY62137CVLL
CY62137CVSL
Industrial
Industrial
2.7V
2.7V
3.3
3.3
3.6
3.6
5
1
15
5
Notes:
2. NC pins are not connected to the die.
3. E3 (DNU) can be left as NC or tied to V to ensure proper application.
SS
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ.)
Document #: 38-05201 Rev. *F
Page 2 of 13
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient
Temperature TA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Device
Range
VCC
CY62137CV25 Industrial –40°C to +85°C 2.2V to 2.7V
Supply Voltage to Ground Potential –0.5V to VCCMAX + 0.5V
CY62137CV30
CY62137CV33
CY62137CV
2.7V to 3.3V
3.0V to 3.6V
2.7V to 3.6V
DC Voltage Applied to Outputs
in High-Z State[5] ....................................–0.5V to VCC + 0.3V
DC Input Voltage[5].................................... −0.5V to VCC + 0.3V
Output Current into Outputs (LOW) .............................20 mA
CY62137CV30 Automotive –40°C to +125°C 2.7V to 3.3V
Electrical Characteristics Over the Operating Range
CY62137CV25-55
CY62137CV25-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[4]
Max.
Min. Typ.[4] Max.
Unit
V
Output HIGH Voltage IOH = –0.1 mA
Output LOW Voltage IOL = 0.1 mA
Input HIGH Voltage
VCC = 2.2V
VCC = 2.2V
2.0
2.0
VOL
0.4
0.4
V
VIH
1.8
–0.3
–1
VCC + 0.3 1.8
VCC + 0.3
0.6
V
VIL
Input LOW Voltage
0.6
+1
–0.3
–1
V
IIX
Input Leakage
Current
GND < VI < VCC
+1
µA
IOZ
ICC
Output Leakage
Current
GND < VO < VCC, Output Disabled –1
+1
–1
+1
µA
VCC Operating
Supply Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 2.7V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
1.5
ISB1
Automatic CE
Power-down
Current— CMOS
Inputs
2
10
2
10
µA
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f=0 (OE, WE, BHE, and BLE)
ISB2
Automatic CE
Power-down
Current— CMOS
Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 2.7V
Note:
5. V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
Document #: 38-05201 Rev. *F
Page 3 of 13
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Electrical Characteristics Over the Operating Range
CY62137CV30-55
Min. Typ.[4] Max.
CY62137CV30-70
Min. Typ.[4] Max.
2.4
Parameter
Description
Output HIGH
Voltage
Test Conditions
Unit
VOH
IOH = –1.0 mA VCC = 2.7V
2.4
V
VOL
VIH
VIL
IIX
Output LOW Voltage IOL = 2.1 mA VCC = 2.7V
Input HIGH Voltage
0.4
VCC + 0.3 2.2
0.4
V
V
2.2
VCC + 0.3
Input LOW Voltage
–0.3
–1
0.8
+1
–0.3
–1
0.8
+1
+2
+1
+2
12
15
3
V
Input Leakage
Current
GND < VI < VCC
Ind’l
Auto
Ind’l
Auto
µA
–2
IOZ
Output Leakage
Current
GND < VO < VCC
Output Disabled
,
–1
+1
15
3
–1
µA
–2
ICC
VCC Operating
Supply Current
f = fMAX = 1/tRC VCC = 3.3V Ind’l
7
1.5
2
5.5
5.5
1.5
mA
IOUT = 0mA
Auto
CMOS
Levels
f = 1 MHz
Ind’l
Auto
Ind’l
ISB1
Automatic CE
Power-down
Current— CMOS
Inputs
10
2
2
10
15
µA
CE > VCC – 0.2V
VIN > VCC – 0.2V or
VIN < 0.2V,
Auto
f = fmax (Address and Data
Only), f=0 (OE, WE, BHE
and BLE)
ISB2
Automatic CE
Power-down
Current— CMOS
Inputs
Ind’l
2
10
2
2
10
15
CE > VCC – 0.2V
VIN > VCC – 0.2V or
VIN < 0.2V
Auto
f = 0, VCC = 3.3V
CY62137CV33-70
CY62137CV-70
CY62137CV33-55
Parameter
Description
Test Conditions
Min. Typ.[4]
Max.
Min. Typ.[4] Max. Unit
VOH
Output HIGH Voltage
IOH = –1.0 mA VCC = 3.0V
VCC = 2.7V
2.4
2.4
2.4
V
V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 3.0V
VCC = 2.7V
0.4
0.4
0.4
V
V
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage
2.2
–0.3
–1
VCC + 0.3 2.2
VCC + 0.3
0.8
V
0.8
+1
+1
–0.3
–1
V
Input Leakage Current GND < VI < VCC
+1
µA
µA
IOZ
Output Leakage Current GND < VO < VCC, Output
Disabled
–1
–1
+1
ICC
VCC Operating
Supply Current
f = fMAX = 1/tRC VCC = 3.6V
7
15
3
5.5
1.5
12
3
mA
IOUT = 0 mA
f = 1 MHz
1.5
CMOS Levels
ISB1
Automatic CE
Power-down Current
—CMOS Inputs
5
15
5
15
µA
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f=0 (OE, WE, BHE, and BLE)
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
LL
5
15
5
1
15
5
CE > VCC – 0.2V
VIN > VCC – 0.2V or
VIN < 0.2V, f = 0, VCC = 3.6V
SL
Document #: 38-05201 Rev. *F
Page 4 of 13
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Capacitance[6]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
6
8
COUT
pF
Thermal Resistance
FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
55
16
°C/W
(Junction to Ambient)[6]
ΘJC
Thermal Resistance
(Junction to Case)[6]
°C/W
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC Typ
OUTPUT
90%
10%
90%
10%
GND
Rise TIme: 1 V/ns
R2
30 pF
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5V
16600
15400
8000
1.20
3.0V
1105
1550
645
3.3V
Unit
R1
R2
1216
1374
645
Ω
Ω
Ω
V
RTH
VTH
1.75
1.75
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min. Typ.[4] Max. Unit
1.5
Vccmax
V
ICCDR
VCC= 1.5V
Ind’l
Auto
Ind’l
1
6
8
4
LL
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
µA
SL
[6]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
[7]
tR
tRC
Data Retention Waveform[8]
DATA RETENTION MODE
VCC(min.)
VCC(min.)
V
> 1.5 V
V
CC
DR
t
t
R
CDR
CE or
BHE.BLE
Notes:
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full-device AC operation requires linear V ramp from V to V > 100 µs or stable at V > 100 µs.
CC(min.)
CC
DR
CC(min.)
8. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05201 Rev. *F
Page 5 of 13
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Switching Characteristics Over the Operating Range[9]
55 ns
70 ns
Parameter
Read Cycle
Description
Min
55
Max
Min
70
Max
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
10
10
55
25
70
35
OE LOW to Data Valid
OE LOW to Low-Z[10]
OE HIGH to High-Z[10, 12]
CE LOW to Low-Z[10]
CE HIGH to High-Z[10, 12]
5
10
0
5
10
0
20
20
25
25
CE LOW to Power-up
tPD
CE HIGH to Power-down
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z[10]
BHE/BLE HIGH to High-Z[10, 12]
55
55
70
70
tDBE
[11]
tLZBE
tHZBE
Write Cycle[13]
tWC
5
5
20
25
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
0
tPWE
tBW
40
50
25
0
45
60
30
0
BHE/BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[10, 12]
WE HIGH to Low-Z[10]
tSD
tHD
tHZWE
20
25
tLZWE
10
10
Notes:
9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the
CC(typ.)
CC(typ.)
specified I /I and 30-pF load capacitance.
OL OH
10. At any given temperature and voltage condition, t
given device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
11. If both byte enables are toggled together this value is 10 ns.
12. t , t , t , and t transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
13. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any
IL
IL
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05201 Rev. *F
Page 6 of 13
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
tDOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
I
CC
CC
SUPPLY
CURRENT
50%
50%
I
SB
Notes:
14. Device is continuously selected. OE, CE = V , BHE, BLE = V
.
IL
IL
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05201 Rev. *F
Page 7 of 13
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[13, 17, 18]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
VALID
NOTE
19
t
HZOE
Write Cycle No. 2 (CE Controlled)[13, 17, 18]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATAIN
DATA I/O
19
NOTE
t
HZOE
Notes:
17. Data I/O is high-impedance if OE = V
.
IH
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
19. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05201 Rev. *F
Page 8 of 13
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[18]
.
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 19
DATAI/O
DATAIN VALID
t
LZWE
t
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
t
t
HD
SD
DATA I/O
VALID
DATAIN
NOTE 19
Document #: 38-05201 Rev. *F
Page 9 of 13
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Truth Table
CE
H
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High-Z
Mode
Deselect/Power-down
Deselect/Power-down
Read
Power
Standby (ISB
)
)
X
X
H
H
High-Z
Standby (ISB
L
H
L
L
L
Data Out (I/OO–I/O15
)
Active (ICC
)
)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC
)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z
High-Z
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data In (I/OO–I/O15)
L
H
Data In (I/OO–I/O7);
I/O8–I/O15 in High-Z
Write
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC
)
Ordering Information
Speed
(ns)
Voltage
Package
Operating
Range
Ordering Code
Range (V) Diagram
Package Type
70
CY62137CV30LL-70BAI
CY62137CV30LL-70BVI
CY62137CV30LL-70BVXI
CY62137CV33LL-70BAI
CY62137CV33LL-70BVI
CY62137CVSL-70BVI
2.7–3.3
51-85096 48-ball FBGA (7 x 7 x 1.2 mm)
51-85150 48-ball FBGA (6 x 8 x 1 mm)
48-ball FBGA (6 x 8 x 1 mm) (Pb-free)
51-85096 48-ball FBGA (7 x 7 x 1.2 mm)
51-85150 48-ball FBGA (6 x 8 x 1 mm)
51-85150 48-ball FBGA (6 x 8 x 1 mm)
51-85096 48-ball FBGA (7 x 7 x 1.2 mm)
Industrial
3.0–3.6
2.7–3.6
CY62137CVSL-70BAI
CY62137CVSL-70BAXI
CY62137CV30LL-70BAE
CY62137CV30LL-70BVE
CY62137CV30LL-70BVXE
CY62137CV30LL-55BAI
CY62137CV30LL-55BVI
CY62137CV30LL-55BVXI
CY62137CV33LL-55BAI
CY62137CV33LL-55BVI
48-ball FBGA (7 x 7 x 1.2 mm) (Pb-free)
51-85096 48-ball FBGA (7 x 7 x 1.2 mm)
51-85150 48-ball FBGA (6 x 8 x 1 mm)
48-ball FBGA (6 x 8 x 1 mm) (Pb-free)
51-85096 48-ball FBGA (7 x 7 x 1.2 mm)
51-85150 48-ball FBGA (6 x 8 x 1 mm)
48-ball FBGA (6 x 8 x 1 mm) (Pb-free)
51-85096 48-ball FBGA (7 x 7 x 1.2 mm)
51-85150 48-ball FBGA (6 x 8 x 1 mm)
2.7–3.3
2.7–3.3
3.0–3.6
Automotive
Industrial
55
Please contact your local Cypress sales representative for availability of other parts.
Document #: 38-05201 Rev. *F
Page 10 of 13
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Package Diagrams
48-ball FBGA (7 x 7 x 1.2 mm) (51-85096)
BOTTOM VIEW
Ø0.05 M C
TOP VIEW
PIN 1 CORNER
PIN 1 CORNER
ꢀLASER MARKX
Ø0.25 M C A B
Ø0.30 0.05ꢀ4ꢁ8X
1
2
3
4
5
6
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
F
E
F
G
H
G
H
A
A
1.ꢁ75
0.75
3.75
B
7.00 0.10
7.00 0.10
B
0.15ꢀ48X
51-85096-*F
SEATING PLANE
C
1.20 MA8.
Document #: 38-05201 Rev. *F
Page 11 of 13
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Package Diagrams (continued)
48-ball FBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05ꢀ4ꢁ8X
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.ꢁ75
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ48X
51-85150-*D
SEATING PLANE
C
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05201 Rev. *F
Page 12 of 13
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document History Page
Document Title: CY62137CV25/30/33 MoBL® and CY62137CV MoBL® 2M (128K x 16) Static RAM
Document Number: 38-05201
Orig. of
REV. ECN NO. Issue Date Change
Description of Change
New Data Sheet (advance information)
**
112393
114015
02/19/02
04/25/02
GAV
JUI
*A
Added BV package diagram
Changed from Advance Information to Preliminary
*B
*C
117064
118122
07/12/02
09/10/02
MGN
MGN
Changed from Preliminary to Final
Added new part number: CY62137CV with wider voltage (2.7V – 3.6V).
Added new SL power bin for new part number.
For TAA = 55 ns, improved tPWE min. from 45 ns to 40 ns.
For TAA = 70 ns, improved tPWE min. from 50 ns to 45 ns.
For TAA = 70 ns, improved tLZWE min. from 5 ns to 10 ns.
*D
118761
09/23/02
MGN
Improved Typ. ICC spec to 7 mA (for 55 ns) and 5.5 mA (for 70 ns).
Improved Max ICC spec to 15 mA (for 55 ns) and 12 mA (for 70 ns).
For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns.
Changed upper spec. for Supply Voltage to Ground Potential to VCCMAX + 0.5V.
Changed upper spec. for DC Voltage Applied to Outputs in High-Z State and DC
Input Voltage to VCC + 0.3V.
*E
*F
343877
419237
See ECN
See ECN
PCI
Added Automotive Information in Operating Range, DC and Ordering Information
Table
ZSD
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Updated the ordering information table and replaced the Package name column
with Package diagram.
Document #: 38-05201 Rev. *F
Page 13 of 13
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