CY62138FLL-45SXI [CYPRESS]
2-Mbit (256K x 8) Static RAM; 2兆位（ 256K ×8 ）静态RAM
| 型号： | CY62138FLL-45SXI |
| 厂家： | 
CYPRESS |
| 描述： | 2-Mbit (256K x 8) Static RAM |
| 文件： | 总10页 (文件大小：841K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62138F MoBL®
2-Mbit (256K x 8) Static RAM
Features
Functional Description [1]
• High speed: 45 ns
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE1 HIGH
or CE2 LOW).
• Wide voltage range: 4.5 V – 5.5 V
• Pin compatible with CY62138V
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 5 µA
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE1, CE2, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO0 through IO7) is then written into the location
specified on the address pins (A0 through A17).
• Available in Pb-free 32-pin SOIC and 32-pin TSOP II
packages
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and output enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO0 through IO7) are placed
in a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
Logic Block Diagram
IO
0
DATA IN DRIVERS
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO
1
IO
2
256K x 8
ARRAY
IO
3
IO
IO
IO
IO
4
5
6
7
A
A
A
9
10
11
CE
CE
1
2
POWER
DOWN
COLUMN DECODER
WE
OE
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-13194 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 26, 2007
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CY62138F MoBL®
Pin Configuration [2]
32-Pin SOIC/TSOP II Pinout
Top View
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
IO7
IO6
IO5
IO4
IO3
A17
A16
A14
A12
A7
1
2
32
31
30
29
28
27
26
25
24
23
22
3
4
5
A6
6
A5
A4
A3
A2
A1
A0
IO0
IO1
IO2
VSS
7
8
9
10
11
12
13
14
15
16
21
20
19
18
17
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1MHz f = fmax
VCC Range (V)
Speed
(ns)
Product
Standby ISB2 (µA)
Min
Typ [3]
Max
5.5V
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
CY62138FLL
4.5V
5.0V
45
1.6
2.5
13
18
1
5
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ)
Document #: 001-13194 Rev. *A
Page 2 of 10
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CY62138F MoBL®
DC Input Voltage [4, 5]............ –0.5V to 6.0V (VCCmax + 0.5V)
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Storage Temperature ................................–65°C to + 150°C
Latch-up Current ................................................... > 200 mA
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground
Ambient
Potential ................................–0.5V to 6.0V (VCCmax + 0.5V)
[6]
Device
Range
VCC
Temperature
DC Voltage Applied to Outputs
in High-Z state [4, 5] ................–0.5V to 6.0V (VCCmax + 0.5V)
CY62138FLL
Industrial –40°C to +85°C 4.5V to 5.5V
Electrical Characteristics (Over the Operating Range)
45 ns
Parameter
Description
Test Conditions
Unit
Min
Typ [3]
Max
VOH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOH = –1.0 mA
2.4
V
V
VOL
VIH
VIL
IIX
IOL = 2.1 mA
0.4
VCC + 0.5
0.8
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
GND < VI < VCC
2.2
–0.5
–1
V
V
Input Leakage Current
Output Leakage Current
+1
µA
µA
mA
IOZ
ICC
GND < VO < VCC, Output Disabled
–1
+1
VCC Operating Supply
Current
f = fmax = 1/tRC
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
13
18
1.6
2.5
[7]
ISB2
Automatic CE Power Down CE1 > VCC – 0.2V or CE2 < 0.2V
Current CMOS inputs
1
5
µA
V
IN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max)
Capacitance (For all packages) [8]
Parameter
CIN
COUT
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
pF
pF
10
Thermal Resistance [8]
Parameter
Description
Test Conditions
SOIC
TSOP II
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch
two-layer printed circuit board
44.53
44.16
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
24.05
11.97
°C/W
Notes
4.
V
= –2.0V for pulse durations less than 20 ns.
IL(min)
5.
V
= V +0.75V for pulse durations less than 20ns.
IH(max)
CC
6. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
CC
CC
7. Only chip enables (CE and CE ) must be at CMOS level to meet the I / I spec. Other inputs can be left floating.
SB2 CCDR
1
2
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-13194 Rev. *A
Page 3 of 10
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CY62138F MoBL®
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
VCC
3.0V
GND
OUTPUT
90%
10%
10%
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
Equivalent to:
THEVENIN EQUIVALENT
SCOPE
RTH
OUTPUT
V
Parameters
5.0V
1800
990
Unit
Ω
R1
R2
Ω
RTH
VTH
639
Ω
1.77
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
Conditions
Min
Typ [3]
Max
Unit
V
VCC for Data Retention
Data Retention Current
2.0
[7]
ICCDR
VCC= VDR, CE1 > VCC − 0.2V or CE2 < 0.2V,
IN > VCC - 0.2V or VIN < 0.2V
1
5
µA
V
[8]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[9]
tR
Operation Recovery Time
tRC
Data Retention Waveform [10]
DATA RETENTION MODE
> 2.0V
VCC(min)
VCC(min)
V
VCC
CE
DR
t
t
R
CDR
Notes:
9. Full device AC operation requires linear V ramp from V to V
> 100 µs or stable at V
> 100 µs.
CC
DR
CC(min)
CC(min)
10. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
Document #: 001-13194 Rev. *A
Page 4 of 10
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CY62138F MoBL®
Switching Characteristics (Over the Operating Range) [11]
45 ns
Parameter
Description
Unit
Min
45
Max
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
45
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
10
45
22
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z [12]
5
10
0
OE HIGH to High-Z [12, 13]
18
18
45
CE1 LOW and CE2 HIGH to Low Z [12]
CE1 HIGH or CE2 LOW to High-Z [12, 13]
to power up
CE1 LOW and CE2 HIGH
tPD
to power down
CE1 HIGH or CE2 LOW
Write Cycle [14]
tWC
Write Cycle Time
45
35
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
to Write End
CE1 LOW and CE2 HIGH
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tHA
tSA
0
tPWE
tSD
35
25
0
Data Setup to Write end
Data Hold from Write End
WE LOW to High-Z [12, 13]
WE HIGH to Low-Z [12]
tHD
tHZWE
tLZWE
18
10
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the AC Test Loads and Waveforms on page 4.
CC(typ)
OL OH
12. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
13. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
14. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-13194 Rev. *A
Page 5 of 10
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CY62138F MoBL®
Switching Waveforms
Read Cycle 1 (Address transition controlled) [15, 16]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE controlled) [10, 16, 17]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
t
V
CC
PU
50%
SUPPLY
CURRENT
50%
ISB
Write Cycle No. 1 (WE controlled) [10, 14, 18, 19]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
20
DATA IO
NOTE
DATA VALID
t
HZOE
Notes:
15. The device is continuously selected. OE, CE = V , CE = V
.
1
IL
2
IH
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE transition LOW and CE transition HIGH.
1
2
18. Data IO is high impedance if OE = V
.
IH
19. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
2
20. During this period, the IOs are in output state. Do not apply input signals.
Document #: 001-13194 Rev. *A
Page 6 of 10
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CY62138F MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
AW
HA
t
PWE
WE
t
t
HD
SD
DATA IO
DATA VALID
Write Cycle No. 3 (WE controlled, OE LOW) [10, 19]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
20
NOTE
DATA VALID
DATA IO
t
t
LZWE
HZWE
Truth Table
CE
H
L
WE
OE
X
Inputs/Outputs
Mode
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
X
H
L
High Z
Deselect/Power Down
)
L
Data Out
Data In
High Z
Read
Write
)
L
X
)
L
H
H
Selected, Outputs Disabled
)
Ordering Information
Speed
Package
Diagram
Operating
Package Type
(ns)
Ordering Code
CY62138FLL-45SXI
CY62138FLL-45ZSXI
Range
45
51-85081 32-pin Small Outline Integrated Circuit (Pb-free)
51-85095 32-pin Thin Small Outline Package II (Pb-free)
Industrial
Contact your local Cypress sales representative for availability of these parts.
Document #: 001-13194 Rev. *A
Page 7 of 10
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CY62138F MoBL®
Package Diagrams
Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081
16
1
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
17
32
0.793[20.142]
0.817[20.751]
0.006[0.152]
0.012[0.304]
0.101[2.565]
0.111[2.819]
0.118[2.997]
MAX.
0.004[0.102]
0.047[1.193]
0.063[1.600]
0.004[0.102]
0.050[1.270]
0.023[0.584]
0.039[0.990]
MIN.
BSC.
0.014[0.355]
0.020[0.508]
51-85081-*B
SEATING PLANE
Document #: 001-13194 Rev. *A
Page 8 of 10
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CY62138F MoBL®
Package Diagrams (continued)
Figure 2. 32-Pin TSOP II, 51-85095
51-85095-**
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 001-13194 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62138F MoBL®
Document History Page
Document Title: CY62138F MoBL® 2-Mbit (256K x 8) Static RAM
Document Number: 001-13194
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
797956
940341
See ECN
See ECN
VKN
New Data Sheet
*A
VKN
Added footnote #7 related to ISB2 and ICCDR
Document #: 001-13194 Rev. *A
Page 10 of 10
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相关型号：
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Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
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CY62138FV30LL-45ZAXIT
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