CY62138FV30LL-45ZAXIT [CYPRESS]
Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, 1.20 MM HEIGHT, LEAD FREE, STSOP-32;
| 型号： | CY62138FV30LL-45ZAXIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 13.40 MM, 1.20 MM HEIGHT, LEAD FREE, STSOP-32 存储 内存集成电路 静态存储器 光电二极管 |
| 文件： | 总16页 (文件大小：642K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62138FV30 MoBL®
2-Mbit (256K x 8) Static RAM
Features
Functional Description
■ Very High-speed: 45 ns
The CY62138FV30[1] is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Place the device into standby mode reducing
power consumption when deselected (CE1 HIGH or CE2 LOW).
■ Temperature ranges
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
■ Wide voltage range: 2.20 V to 3.60 V
■ Pin compatible with CY62138CV25/30/33
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A17).
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 5 A
■ Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
■ Easy memory expansion with CE1, CE2, and OE Features
■ Automatic power down when deselected
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
■ complementary metal oxide semiconductor (CMOS) for
Optimum speed and power
■ Offered in Pb-free 36-Ball VFBGA, 32-Pin TSOP II, 32-Pin
SOIC, 32-Pin TSOP I and 32-Pin STSOP Packages
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-08029 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 4, 2010
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CY62138FV30 MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Electrical Characteristics ................................................ 4
Capacitance ...................................................................... 4
Thermal Resistance.......................................................... 5
Data Retention Characteristics .......................................5
Switching Characteristics ................................................6
Switching Waveforms ......................................................7
Truth Table ........................................................................8
Ordering Information........................................................ 9
Ordering Code Definition............................................. 9
Package Diagrams ..........................................................10
Acronyms........................................................................ 14
Document Conventions .................................................14
Units of Measure ....................................................... 14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................16
Worldwide Sales and Design Support .......................16
Products ....................................................................16
PSoC Solutions .........................................................16
Document #: 001-08029 Rev. *I
Page 2 of 16
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CY62138FV30 MoBL®
Pin Configuration
36-Ball VFBGA (Top View) [2]
32-Pin SOIC/TSOP II (Top View)
1
2
4
3
5
6
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
A17
A16
A14
A12
A7
1
2
32
31
30
29
28
27
26
25
24
23
22
A
A
A8
I/O
A1
A2
CE2
A0
6
A
B
C
3
3
4
5
A
I/O
WE
NC
A7
4
0
4
A6
6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
7
A
I/O
I/O
1
8
9
10
5
5
V
CC
V
SS
D
E
F
11
12
13
14
15
16
CE1
21
20
19
18
17
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
V
CC
NC
A
17
I/O
I/O
6
2
CE1
A
G
H
I/O
OE
A15
I/O
16
7
3
A
A
A
A
A9
A14
12
11
13
10
32-Pin TSOP I (Top View)
32-Pin STSOP (Top View)
A
A
A
24
23
OE
11
A11
A9
A8
25
26
1
2
32
31
OE
A10
A
9
8
10
22
21
20
19
18
17
16
15
14
13
12
11
10
9
CE
26
7
3
4
5
6
7
8
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
28
29
30
31
32
1
2
3
4
5
6
7
8
A
I/O
I/O
I/O
I/O
I/O
13
7
6
5
A13
WE
CE
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
2
A
STSOP
Top View
(not to scale)
15
TSOP I
Top View
(not to scale)
4
3
V
CC
A
A
GND
17
16
9
I/O
2
10
11
12
13
14
15
16
I/O
1
A
A
14
12
I/O
0
A
A
A
A
A
0
7
A
1
6
A
2
5
4
A
3
Product Portfolio
Power Dissipation
Speed
(ns)
Product
Range
VCC Range (V)
Operating ICC (mA)
f = 1 MHz f = fmax
Standby ISB2 (A)
Min
Typ[3]
Max
Typ[3]
Max
Typ[3]
Max
Typ[3]
Max
CY62138FV30LL Ind’l/Auto-A
2.2
3.0
3.6
45
1.6
2.5
13
18
1
5
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ.)
Document #: 001-08029 Rev. *I
Page 3 of 16
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CY62138FV30 MoBL®
DC input voltage [4, 5]......................................–0.3 V to 3.9 V
Output current into outputs (LOW) .............................. 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage......................................... > 2001 V
(MIL-STD-883, Method 3015)
Storage temperature................................. –65 °C to +150 °C
Latch-up current .....................................................> 200 mA
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Ambient
[6]
Product
Range
VCC
Supply voltage to ground
potential..........................................................–0.3 V to 3.9 V
Temperature
CY62138FV30LL Ind’l/Auto-A –40 °C to +85 °C 2.2 V to 3.6 V
DC voltage applied to outputs
in High-Z State [4, 5] ........................................–0.3 V to 3.9 V
Electrical Characteristics (Over the Operating Range)
45 ns (Ind’l/Auto-A)
Parameter
Description
Output HIGH voltage
Test Conditions
Unit
Min Typ [7]
Max
VOH
IOH = –0.1 mA
2.0
2.4
–
–
–
–
–
–
–
–
–
–
–
–
–
V
V
IOH = –1.0 mA, VCC > 2.70 V
IOL = 0.1 mA
–
VOL
VIH
VIL
Output LOW voltage
Input HIGH voltage
Input LOW voltage
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
VCC = 2.2 V to 2.7 V
0.4
VCC + 0.3V
VCC + 0.3V
0.6
V
1.8
2.2
V
VCC= 2.7 V to 3.6 V
V
VCC = 2.2 V to 2.7 V For BGA package
VCC= 2.7 V to 3.6 V
–0.3
–0.3
–0.3
–1
V
0.8
V
VCC = 2.2 V to 3.6 V For other packages
GND < VI < VCC
0.6
V
IIX
Input leakage current
Output leakage current
+1
A
A
IOZ
GND < VO < VCC
output disabled
,
–1
+1
ICC
VCC Operating supply current
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA
CMOS levels
–
–
13
18
mA
1.6
2.5
[8]
ISB1
Automatic CE Power-down
Current CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V),
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = 3.60 V
–
1
5
A
[8]
ISB2
Automatic CE Power-down
Current CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–
1
5
A
Capacitance
Parameter[9]
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
CC = VCC(typ.)
V
COUT
10
pF
Notes
4.
5.
V
= –2.0V for pulse durations less than 20 ns.
IL(min)
V
= V +0.75V for pulse durations less than 20 ns.
IH(max)
CC
6. Full device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
CC
CC
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C
A
CC
CC(typ.)
8. Chip enables (CE and CE ) must be at CMOS level to meet the I
/ I
/ I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-08029 Rev. *I
Page 4 of 16
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CY62138FV30 MoBL®
Thermal Resistance
Parameter[10]
Description
Test Conditions
SOIC
VFBGA TSOP II STSOP TSOP I Unit
JA
Thermal resistance
(Junction to Ambient) 4.5 inch, two layer
Still air, soldered on a 3 x
44.53
38.49
44.16
59.72
50.19 C/W
printed circuit board
JC
Thermal resistance
(Junction to Case)
24.05
17.66
11.97
15.38
14.59 C/W
Figure 1. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
90%
10%
90%
10%
R2
GND
Rise Time = 1 V/ns
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameter
2.5 V (2.2 V to 2.7 V)
3.0 V (2.7 V to 3.6 V)
Unit
R1
R2
16667
15385
8000
1.20
1103
1554
645
RTH
VTH
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VCC for data retention
Data retention current
Conditions
Min Typ[11] Max Unit
VDR
1.5
–
–
1
–
4
V
[12]
ICCDR
VCC = 1.5 V,
Ind’l/Auto-A
A
CE1 > VCC 0.2 V or CE2 < 0.2
V, VIN > VCC 0.2 V or VIN < 0.2 V
[10]
tCDR
Chip deselect to data retention time
Operation recovery time
0
–
–
–
–
ns
ns
[13]
tR
45
Figure 2. Data Retention Waveform [14]
DATA RETENTION MODE
VCC(min)
VCC(min)
V
DR
> 1.5V
VCC
t
t
R
CDR
CE
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 2 5°C
CC
CC(typ.)
A
12. Chip enables (CE and CE ) must be at CMOS level to meet the I
/ I
/ I
spec. Other inputs can be left floating
1
2
SB1 SB2 CCDR
13. Full device AC operation requires linear V ramp from V to V
> 100 s or stable at V
> 100 s.
CC
DR
CC(min)
CC(min)
14. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
Document #: 001-08029 Rev. *I
Page 5 of 16
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CY62138FV30 MoBL®
Switching Characteristics (Over the Operating Range)
45 ns (Ind’l/Auto-A)
Parameter[15]
Description
Unit
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data hold from address change
10
–
45
22
–
CE1 LOW and CE2 HIGH to data valid
OE LOW to
–
data valid
OE LOW to Low-Z [16]
5
OE HIGH to High-Z [16,17]
–
18
–
CE1 LOW and CE2 HIGH to Low Z [16]
CE1 HIGH or CE2 LOW to High-Z [16,17]
CE1 LOW and CE2 HIGH to Power-up
CE1 HIGH or CE2 LOW to Power-down
10
–
18
–
0
tPD
–
45
Write Cycle [18]
tWC
Write cycle time
45
35
35
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE1 LOW and CE2 HIGH to write end
Address setup to
–
write end
tHA
Address hold from
–
write end
tSA
Address setup to Write Start
WE pulse Width
0
–
tPWE
tSD
35
25
0
–
Data setup to
–
write end
tHD
Data hold from
–
write end
tHZWE
tLZWE
WE LOW to High-Z [16,17]
WE HIGH to Low-Z [16]
–
18
–
10
Notes
15. Test conditions for all parameters other than tristate parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the AC Test Loads and Waveforms on page 5.
CC(typ)
OL OH
16. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
LZWE
HZCE
LZCE HZOE
LZOE
HZWE
17. t
, t
, and t
transitions are measured when the output enters a high impedance state.
HZWE
HZOE HZCE
18. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write.
Document #: 001-08029 Rev. *I
Page 6 of 16
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CY62138FV30 MoBL®
Switching Waveforms
Figure 3. Read Cycle 1 (Address transition controlled) [20, 21]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2 (OE controlled) [21, 22, 25]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
ISB
t
V
PU
CC
50%
SUPPLY
CURRENT
50%
Figure 5. Write Cycle No. 1 (WE controlled) [19, 23, 24, 25]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
26
DATA I/O
NOTE
DATA VALID
t
HZOE
Notes
19. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write
20. The device is continuously selected. OE, CE = V , CE = V
.
IH
1
IL
2
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE transition LOW and CE transition HIGH.
1
2
23. Data I/O is high impedance if OE = V
.
IH
24. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
2
25. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
26. During this period, the I/Os are in output state. Do not apply input signals
Document #: 001-08029 Rev. *I
Page 7 of 16
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CY62138FV30 MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (CE1 or CE2 controlled) [27, 28, 29, 30]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
AW
HA
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Figure 7. Write Cycle No. 3 (WE controlled, OE LOW) [27, 30]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
31
NOTE
DATA VALID
DATA I/O
t
t
LZWE
HZWE
Truth Table
CE1
CE2
X[32]
WE
X
OE
X
Inputs/Outputs
Mode
Power
H
High-Z
High-Z
Deselect / Power-down
Deselect/Power-down
Read
Standby (ISB
)
)
X[32]
L
L
X
X
Standby (ISB
H
H
L
Data out
High-Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
H
H
H
X
Output disabled
Write
L
H
L
Data in
Notes
27. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
28. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write
29. Data I/O is high impedance if OE = V
.
IH
30. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains iin high impedance state.
1
2
31. During this period, the I/Os are in output state. Do not apply input signals.
32. The ‘X’ (Don’t care) state for the Chip enables (CE and CE ) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
1
2
pins is not permitted.
Document #: 001-08029 Rev. *I
Page 8 of 16
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CY62138FV30 MoBL®
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
36-ball VFBGA (Pb-free)
45
CY62138FV30LL-45BVXI
CY62138FV30LL-45ZSXI
CY62138FV30LL-45ZAXI
CY62138FV30LL-45ZXI
CY62138FV30LL-45SXI
CY62138FV30LL-45ZAXA
51-85149
51-85095
51-85094
51-85056
51-85081
51-85094
Industrial
32-pin TSOP II (Pb-free)
32-pin STSOP (Pb-free)
32-pin TSOP I (Pb-free)
32-pin SOIC (Pb-free)
32-pin STSOP (Pb-free)
Automotive-A
Ordering Code Definition
CY
621
3
8F V30 LL
45 XXX
X
Temperature Grades
I = Industrial, A = Auto A
Package Type BVX: VFBGA (Pb-free)
ZSX: TSOP II (Pb-free)
ZAX: STSOP (Pb-free)
ZX : TSOP I (Pb-free)
SX : SOIC (Pb-free)
Speed Grade
Low Power
Voltage Range = 3 V typical
Bus Width = x8
F = 90nm Technology
Density = 2 Mbit
MoBL SRAM Family
Coimpany ID: CY = Cypress
Document #: 001-08029 Rev. *I
Page 9 of 16
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CY62138FV30 MoBL®
Package Diagrams
Figure 8. 36-Ball VFBGA (6 x 8 x 1 mm), 51-85149
51-85149 *D
Document #: 001-08029 Rev. *I
Page 10 of 16
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CY62138FV30 MoBL®
Figure 9. 32-Pin TSOP II, 51-85095
51-85095 *A
Document #: 001-08029 Rev. *I
Page 11 of 16
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CY62138FV30 MoBL®
Figure 10. 32-Pin (450 Mil) Molded SOIC, 51-85081
51-85081 *C
Document #: 001-08029 Rev. *I
Page 12 of 16
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CY62138FV30 MoBL®
Figure 11. 32-Pin TSOP I (8 x 20 mm), 51-85056
51-85056 * E
Document #: 001-08029 Rev. *I
Page 13 of 16
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CY62138FV30 MoBL®
Figure 12. 32-Pin STSOP (8 x 13.4 mm), 51-85094
51-85094 * E
Acronyms
Document Conventions
Units of Measure
Acronym
CMOS
I/O
Description
complementary metal oxide semiconductor
input/output
Symbol
°C
Unit of Measure
SRAM
static random access memory
very fine ball grid array
degrees Celsius
VFBGA
TSOP
A
microamperes
milliampere
megahertz
nanoseconds
picofarads
volts
thin small outline package
mA
MHz
ns
pF
V
ohms
W
watts
Document #: 001-08029 Rev. *I
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CY62138FV30 MoBL®
Document History Page
Document Title: CY62138FV30 MoBL®, 2-Mbit (256K x 8) Static RAM
Document Number: 001-08029
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
463660
467351
See ECN
See ECN
NXR
NXR
New data sheet
*A
Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages
Changed ball A3 from NC to CE2 in 36-ball FBGA pin out
*B
566724
See ECN
NXR
VKN
Converted from Preliminary to Final
Corrected typo in 32 pin TSOP II pin configuration diagram on page #2 (changed
pin 24 from CE1to OE and pin 22 from CE to CE1)
Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz
Changed the ISB2(typ) value from 0.5 A to 1 A
Changed the ISB2(max) value from 2.5 A to 5 A
Changed the ICCDR(typ) value from 0.5 A to 1 A and ICCDR(max) value from 2.5
A to 4 A
*C
797956
See ECN
Added 32-pin SOIC package
Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on
Electrical characteristics table
*D
*E
*F
*G
809101
940341
2769239
3055119
See ECN
See ECN
09/25/09
VKN
VKN
Corrected typo in the Ordering Information table
Added footnote #7 related to ISB2 and ICCDR
VKN/AESA Included Automotive-A information
10/12/2010
RAME
Updated and converted all tablenotes into Footnote
Added Acronyms and Units of Measure table
Added Ordering Code Definition
Updated All Package Diagrams.
Updated datasheet as per new template.
*H
*I
3061313
3078557
10/15/2010
11/04/2010
RAME
RAME
Minor changes: Corrected “IO” to “I/O”
Corrected 55 C to -55C in Ambient Temperature with Power applied in Maximum
Ratings Section
Document #: 001-08029 Rev. *I
Page 15 of 16
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© Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-08029 Rev. *I
Revised November 4, 2010
Page 16 of 16
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CY62138FV30LL-45ZXIT
Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 20 MM, 1 MM HEIGHT, LEAD FREE, TSOP1-32
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