CY62147DV18LL-70BVXIT [CYPRESS]
Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48;
| 型号： | CY62147DV18LL-70BVXIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 静态存储器 内存集成电路 |
| 文件： | 总11页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62147DV18
MoBL2™
4-Mb (256K x 16) Static RAM
mode reducing power consumption by more than 99% when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O0 through I/O15) are placed in a high-im-
pedance state when: deselected (CE HIGH), outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by asserting Chip En-
able (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7), is written into the location specified on the address pins
(A0 through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table for a complete description of read and write
modes.
Features
• Very high speed: 55 ns and 70 ns
• Wide voltage range: 1.65V – 2.25V
• Pin-compatible with CY62147CV18
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 6 mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA
Functional Description[1]
The CY62147DV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
The CY62147DV18 is available in a 48-ball FBGA package.
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
7
6
5
4
3
2
A
A
A
A
256K x 16
RAM Array
I/O – I/O
0
7
A
I/O – I/O
8
A
A
A
15
1
0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Power
Circuit
-Down
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05343 Rev. *B
Revised February 26, 2004
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CY62147DV18
MoBL2™
Pin Configuration[2, 3, 4]
FBGA (Top View)
1
4
2
5
3
6
A
A
2
A
NC
OE
BLE
0
1
A
B
C
A
A
4
I/O BHE
CE
I/O
I/O
0
3
8
A
A
6
I/O
I/O
2
I/O
5
9
10
1
Vcc
Vss
A
V
I/O
I/O
3
A17
D
E
F
SS
7
11
DNU
A
16
V
CC
I/O
I/O
12
4
A
A
15
I/O
I/O
5
I/O
I/O
14
13
14
6
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
A
A
A
A
NC
NC
10
9
11
8
Notes:
2. NC pins are not internally connected on the die.
3. DNU pins have to be left floating or tied to Vss to ensure proper application.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
Document #: 38-05343 Rev. *B
Page 2 of 11
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CY62147DV18
MoBL2™
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current.....................................................> 200 mA
Storage Temperature ................................–65°C to + 150°C
Operating Range
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Ambient
Supply Voltage to Ground
Temperature
[7]
Device
Range
(TA)
VCC
Potential......................................–0.2V to + VCC(MAX) + 0.2V
CY62147DV18L Industrial –40°Cto+85°C 1.65V to 2.25V
CY62147DV18LL
DC Voltage Applied to Outputs
in High Z State[5,6]..........................–0.2V to VCC(MAX) + 0.2V
DC Input Voltage[5,6] .....................–0.2V to VCC (MAX) + 0.2V
Product Portfolio
Power Dissipation
Operating ICC (mA)
VCC Range (V)
f = 1MHz
f = fmax
Standby ISB2 (µA)
Speed
Product
Min.
Typ.[7]
Max.
2.25
(ns)
Typ.[7]
Max.
Typ.[7]
Max.
15
Typ.[7]
Max.
18
CY62147DV18L
CY62147DV18LL
CY62147DV18L
CY62147DV18LL
1.65
1.8
55
1.0
2.0
6
0.5
10
15
10
12
18
12
1.65
1.8
2.25
70
1.0
2.0
6
0.5
Electrical Characteristics Over the Operating Range
CY62147DV18-55
CY62147DV18-70
Parameter Description
Test Conditions
Min. Typ.[7]
Max.
Min. Typ.[7]
Max.
Unit
VOH
VOL
VIH
VIL
Output HIGH
IOH = –0.1 mA
VCC = 1.65V
1.4
1.4
V
Voltage
Output LOW
Voltage
IOL = 0.1 mA
VCC = 1.65V
0.2
0.2
VCC + 0.2V
0.4
V
Input HIGH
VCC =1.65V to 2.25V
VCC =1.65V to 2.25V
1.4
–0.2
–1
VCC + 0.2V 1.4
V
Voltage
Input LOW
Voltage
0.4
+1
+1
–0.2
–1
V
IIX
Input Leakage GND < VI < VCC
+1
µA
µA
mA
Current
IOZ
ICC
OutputLeakage GND < VO < VCC, Output Disabled
Current
–1
–1
+1
VCC Operating f = fMAX = 1/tRC
VCC(max) = 1.95V L
6
12
8
6
6
12
8
Supply Current
IOUT = 0 mA
CMOS levels
LL
VCC(max) = 2.25V L
6
15
10
15
10
mA
IOUT = 0 mA
LL
CMOS levels
f = 1 MHz
VCC(max) = 1.95V L
1
1
1.5
1
1
1.5
mA
mA
LL
VCC(max) = 2.25V L
LL
2
2
Notes:
5.
6.
V
V
= –2.0V for pulse durations less than 20 ns.
CC
IL(min.)
IH(max)
=V +0.75V for pulse durations less than 20ns.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
CC
, T = 25°C.
A
CC(typ.)
Document #: 38-05343 Rev. *B
Page 3 of 11
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CY62147DV18
MoBL2™
Electrical Characteristics Over the Operating Range (continued)
CY62147DV18-55
CY62147DV18-70
Parameter Description
Test Conditions
Min. Typ.[7]
Max.
12
8
Min. Typ.[7]
Max.
12
8
Unit
ISB1
Automatic CE CE > VCC−0.2V,
VCC(max)=1.95V
L
LL
L
0.5
0.5
µA
Power-Down
Current —
VIN>VCC–0.2V,
VIN<0.2V); f = fMAX
(Address and Data
Only), f = 0 (OE,
VCC(max)=2.25V
0.5
18
12
0.5
18
12
CMOS Inputs
LL
WE, BHE and BLE)
ISB2
Automatic CE CE > VCC – 0.2V, VCC(max)=1.95V
L
LL
L
0.5
0.5
12
8
18
12
0.5
0.5
12
8
18
12
µA
Power-down
Current —
VIN >VCC –0.2Vor
IN < 0.2V, f = 0
V
VCC(max)=2.25V
CMOS Inputs
LL
Capacitance for all Packages[8]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max.
10
10
Unit
pF
pF
CIN
Input Capacitance
COUT
Output Capacitance
Thermal Resistance
Parameter
Description
Test Conditions
BGA
Unit
ΘJA
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
75
°C/W
(Junction to Ambient)[8]
board
ΘJC
Thermal Resistance
(Junction to Case)[8]
10
°C/W
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
OUTPUT
VCC
GND
90%
90%
10%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
1.80V
13500
10800
6000
Unit
Ω
R1
R2
RTH
VTH
Ω
Ω
0.80
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
1.0
Typ.[7]
Max. Unit
V
VCC= 1.0V CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
L
LL
6
4
µA
[8]
tCDR
tR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
tRC
ns
ns
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05343 Rev. *B
Page 4 of 11
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CY62147DV18
MoBL2™
wqewqewq
Data Retention Waveform[9]
DATA RETENTION MODE
> 1.0 V
VCC(min)
VCC(min)
V
V
CC
DR
t
t
R
CDR
CE or
BHE.BLE
Switching Characteristics Over the Operating Range [10.]
55 ns
70 ns
Parameter
Read Cycle
tRC
Description
Min.
55
Max.
Min.
70
Max.
Unit
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
10
10
55
25
70
35
OE LOW to Data Valid
OE LOW to LOW Z[11]
5
10
0
5
10
0
OE HIGH to High Z[11, 12]
CE LOW to Low Z[11]
16
20
16
25
CE HIGH to High Z[11, 12]
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z[11]
BLE / BHE HIGH to HIGH Z[11, 12]
55
55
70
70
tDBE
tLZBE
tHZBE
Write Cycle[13]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
10
10
20
25
Write Cycle Time
CE LOW to Write End
55
40
40
0
70
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z[11, 12]
WE HIGH to Low-Z[11]
0
0
40
40
25
0
45
50
30
0
tHZWE
tLZWE
20
25
10
10
Notes:
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signal or by disabling both BHE and BLE.
10. Test conditions for all parameters other than three-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
OL OH
CC(typ.)
11. At any given temperature and voltage condition, t
given device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
12.
t
, t
, t
, and t
transitions are measured when the outputs enter a high impedence state.
HZOE HZCE HZBE
HZWE
13. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any
IL
IL
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05343 Rev. *B
Page 5 of 11
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CY62147DV18
MoBL2™
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[14, 15]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
I
CC
CC
SUPPLY
50%
50%
CURRENT
I
SB
Notes:
14. The device is continuously selected. OE, CE = V , BHE and/or BLE = V .
IL
IL
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document #: 38-05343 Rev. *B
Page 6 of 11
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CY62147DV18
MoBL2™
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[13, 17, 18]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATAIN
DATA I/O
19
NOTE
t
HZOE
Write Cycle No. 2 (CE Controlled)[13, 17, 18]
t
WC
ADDRESS
t
SCE
CE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
NOTE
19
t
HZOE
Notes:
17. Data I/O is high impedance if OE = V
.
IH
18. If CE goes HIGH simultaneously with WE = V , the output remains in a high-impedance state.
IH
19. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05343 Rev. *B
Page 7 of 11
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CY62147DV18
MoBL2™
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[18]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 19
DATAI/O
DATAIN
t
LZWE
t
HZWE
[18]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
DATA I/O
DATAIN
NOTE 19
tLZWE
Document #: 38-05343 Rev. *B
Page 8 of 11
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CY62147DV18
MoBL2™
Truth Table
CE
H
X
L
L
WE
X
X
H
H
OE
X
X
L
L
BHE
X
H
L
H
BLE
X
H
L
L
Inputs/Outputs
High Z
High Z
Mode
Deselect/Power-Down
Deselect/Power-Down
Read
Power
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
)
)
Data Out (I/OO–I/O15
)
)
)
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read (Lower byte only)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read (Higher byte only)
Active (ICC)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
H
L
L
H
L
L
High Z
High Z
High Z
Data In (I/OO–I/O15
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Write (Lower byte only)
)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write (Higher byte only)
Active (ICC)
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
Name
Package Type
55
CY62147DV18L-55BVI
CY62147DV18LL-55BVI
CY62147DV18L-70BVI
CY62147DV18LL-70BVI
CY62147DV18L-55BVXI
CY62147DV18LL-55BVXI
CY62147DV18L-70BVXI
CY62147DV18LL-70BVXI
BV48A
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm)
Industrial
Industrial
Industrial
Industrial
70
55
70
BV48A
BV48A
BV48A
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm)
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Pb-free
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Pb-free
Document #: 38-05343 Rev. *B
Page 9 of 11
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CY62147DV18
MoBL2™
Package Diagram
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05343 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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CY62147DV18
MoBL2™
Document History Page
Document Title:CY62147DV18 MoBL2™ 4-Mb (256K x 16) Static RAM
Document Number: 38-05343
Issue
Date
06/17/03
11/26/03
See ECN
Orig. of
Change
HRT
CBD
AJU
REV.
**
*A
ECN NO.
127482
131009
229908
Description of Change
New Data Sheet
Changed From Advance to Preliminary
Changed From Preliminary to Final
*B
Added 70 ns speed bin
Changed Vcc MAX spec from 2.20V to 2.25V
Modified VIH spec on footnote #6 from VCC (MAX) + 0.5V to VCC (MAX) + 0.75V
Changed ICC TYP values from 8 mA to 6 mA
Changed ICC MAX values at Vcc (max) = 1.95V from 15 mA to 12 mA (L bin)
and 10 mA to 8mA (LL bin)
Changed ICC MAX values at Vcc (max) = 2.25V from 18 mA to 15 mA (L bin)
and 12mA to 10 mA (LL bin)
With modified Vcc MAX spec, changed ISB1 and ISB2 MAX values from 15 uA
to 18 uA (L bin) and 10 uA to 12 uA (LL bin)
Modified input and output capacitance values
Removed footnote #9 from earlier rev
Removed MAX value for VDR
Modified tHZOE from 20 ns to 16 ns
Added Pb-free ordering information
Document #: 38-05343 Rev. *B
Page 11 of 11
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