CY62157CV30LL-70BAET [CYPRESS]
暂无描述;型号: | CY62157CV30LL-70BAET |
厂家: | CYPRESS |
描述: | 暂无描述 |
文件: | 总13页 (文件大小:338K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY62157CV30/33
512K x 16 Static RAM
significantly reduces power consumption by 80% when
addresses are not toggling. The device can also be put into
standby mode reducing power consumption by more than 99%
when deselected (CE1 HIGH or CE2 LOW or both BLE and
BHE are HIGH). The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CE1
HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE1 LOW and CE2
HIGH and WE LOW).
Features
• Temperature Ranges
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• Voltage range:
— CY62157CV30: 2.7V–3.3V
— CY62157CV33: 3.0V–3.6V
• Ultra-low active power
Writing to the device is accomplished by taking Chip Enable 1
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE2) HIGH. If Byte Low Enable (BLE) is LOW, then data from
I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A18). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18).
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = fmax
• Low standby power
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW and Chip
Enable 2 (CE2) HIGH while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins will appear on
I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O8 to I/O15. See the truth table at the
back of this data sheet for a complete description of read and
write modes.
• Available in Pb-free and non Pb-free 48-ball FBGA
package
Functional Description[1]
The CY62157CV30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life™
(MoBL™) in portable applications such as cellular telephones.
The devices also have an automatic power-down feature that
The CY62157CV30/33 are available in a 48-ball FBGA
package.
Logic Block Diagram
DATA IN DRIVERS
A
A
A
A
A
A
A
A
A
10
9
8
7
6
512K × 16
RAM Array
5
4
3
2
I/O –I/O
0
7
I/O –I/O
8
15
A
A
1
0
COLUMN DECODER
BHE
WE
CE2
CE1
OE
BLE
Power-down
Circuit
CE2
CE1
BHE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05014 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 31, 2006
[+] Feedback
CY62157CV30/33
Product Portfolio
Power Dissipation
Operating (ICC) mA
f = 1 MHz f = fmax
Standby (ISB2
)
VCC Range
Typ.[2]
3.0V
µA
Product
Range
Min.
2.7V
3.0V
Max.
3.3V
3.6V
Typ.[2]
Max.
Typ.[2]
Max.
15
Typ.[2]
8
Max.
CY62157CV30
CY62157CV33
Automotive-E
Automotive-A
Automotive-E
1.5
1.5
1.5
3
3
3
7
5.5
7
70
30
80
3.3V
12
10
15
10
Pin Configurations[2, 3, 4]
FBGA (Top View)
1
2
3
4
5
6
CE2
A
A
A
OE
BLE
0
1
2
A
A
A
I/O BHE
CE1 I/O
B
C
4
3
0
8
A
A
6
I/O
I/O
I/O
2
I/O
5
10
1
9
V
A
V
I/O
I/O
3
A17
CC
D
E
F
SS
7
11
V
SS
A
V
CC
I/O
DNU
I/O
16
12
4
A
A
15
I/O
I/O
I/O
I/O
6
14
13
5
14
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
A
A
A
A
A18
NC
10
9
11
8
Pin Definitions
Name
Definition
Input
A0-A18. Address Inputs
I/O0-I/O15. Data lines. Used as input or output lines depending on operation
Input/Output
Input/Control WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted.
Input/Control CE1. Chip Enable 1, Active LOW.
Input/Control CE2. Chip Enable 2, Active HIGH.
Input/Control OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins
Ground
Vss. Ground for the device
Power Supply Vcc. Power supply for the device
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ.)
3. NC pins are not connected on the die.
4. E3 (DNU) can be left as NC or V to ensure proper application.
SS
Document #: 38-05014 Rev. *F
Page 2 of 13
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CY62157CV30/33
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current ................................................... > 200 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Temperature
Device
Range
[TA][6]
VCC
Supply Voltage to Ground Potential...–0.5V to Vccmax + 0.5V
CY62157CV30 Automotive-E –40°Cto+125°C 2.7V – 3.3V
CY62157CV33 Automotive-A –40°C to +85°C 3.0V – 3.6V
Automotive-E –40°Cto+125°C
DC Voltage Applied to Outputs
in High-Z State[5] ....................................–0.5V to VCC + 0.3V
DC Input Voltage[5].................................–0.5V to VCC + 0.3V
Output Current into Outputs (LOW) .............................20 mA
Electrical Characteristics Over the Operating Range
CY62157CV30-70
Parameter
VOH
VOL
Description
Test Conditions
Min.
Typ.[2]
Max.
Unit
V
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = 2.7V
VCC = 2.7V
2.4
0.4
VCC + 0.3V
0.8
V
VIH
2.2
–0.3
–10
V
VIL
Input LOW Voltage
V
IIX
Input Leakage
Current
GND < VI < VCC
+10
µA
IOZ
ICC
Output Leakage
Current
GND < VO < VCC, Output Disabled
–10
+10
µA
VCC Operating
Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
7
15
3
mA
1.5
ISB1
Automatic CE
Power-Down
Current— CMOS
Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
8
70
µA
µA
V
IN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE, WE, BHE and BLE)
ISB2
Automatic CE
Power-Down
Current—CMOS
Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
8
70
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.3V
Notes:
5. V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
6. T is the “Instant-On” case temperature.
A
Document #: 38-05014 Rev. *F
Page 3 of 13
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CY62157CV30/33
Electrical Characteristics Over the Operating Range
CY62157CV33-70
Parameter
Description
Test Conditions
Min.
Typ.[2]
Max.
Unit
VOH
Output HIGH
Voltage
IOH = –1.0 mA
CC = 3.0V
2.4
V
V
VOL
Output LOW
Voltage
IOL = 2.1 mA
CC = 3.0V
0.4
V
V
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage
2.2
–0.3
–1
VCC + 0.3V
V
V
0.8
+1
+10
+1
+10
12
Input Leakage
Current
GND < VI < VCC
Auto-A
Auto-E
Auto-A
Auto-E
µA
µA
µA
µA
mA
–10
–1
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
–10
ICC
VCC Operating
Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.6V Auto-A
5.5
7
IOUT = 0 mA
CMOS Levels
Auto-E
15
Auto-A/
Auto-E
1.5
3
ISB1
Automatic CE
Power-Down
Current—CMOS
Inputs
CE1 > VCC – 0.2V or
CE2 < 0.2V
Auto-A
Auto-E
10
10
30
80
µA
µA
VIN > VCC – 0.2V or
VIN < 0.2V,
f = fmax (Address and Data
Only),
f = 0 (OE,WE,BHE,and BLE)
ISB2
Automatic CE
Power-Down
Current—CMOS
Inputs
CE1 > VCC – 0.2V or
CE2 < 0.2V
Auto-A
Auto-E
10
10
30
80
µA
µA
VIN > VCC – 0.2V or
VIN < 0.2V,
f = 0, VCC = 3.6V
Thermal Resistance[7]
Parameter
Description
Test Conditions
FBGA
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
55
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
16
°C/W
Note:
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05014 Rev. *F
Page 4 of 13
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CY62157CV30/33
Capacitance[7]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
Max.
Unit
pF
CIN
6
8
COUT
pF
AC Test Loads and Waveforms
R1
V
CC
ALL INPUT PULSES
90%
V
Typ
OUTPUT
CC
90%
10%
10%
GND
R2
30 pF
Rise TIme: 1 V/ns
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
3.0V
1.105
1.550
0.645
1.75
3.3V
Unit
ΚΩ
ΚΩ
ΚΩ
V
R1
R2
1.216
1.374
0.645
1.75
RTH
VTH
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
Conditions
Min. Typ.[2] Max. Unit
VCC for Data Retention
Data Retention Current
1.5
V
VCC = 1.5V, CE1 > VCC – 0.2V or
CE2 < 0.2V,
IN > VCC – 0.2V or VIN < 0.2V
Auto-A
Auto-E
4
4
20
60
µA
µA
V
[8]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[8]
tR
Operation Recovery Time
tRC
Data Retention Waveform[9]
DATA RETENTION MODE
> 1.5 V
V
V
V
CC
V
CC(min.)
CC(min.)
DR
t
t
R
CDR
CE or
1
BHE.BLE
or
CE
2
Notes:
8. Full Device AC operation requires linear V ramp from V to V
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
> 100 µs or stable at V >100 µs.
CC(min.)
CC
DR
CC(min.)
Document #: 38-05014 Rev. *F
Page 5 of 13
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CY62157CV30/33
Switching Characteristics Over the Operating Range [10]
70 ns
Parameter
Read Cycle
Description
Min.
70
Max.
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[11]
OE HIGH to High-Z[11, 12]
CE1 LOW and CE2 HIGH to Low-Z[11]
CE1 HIGH or CE2 LOW to High-Z[11, 12]
CE1 LOW and CE2 HIGH to Power-up
CE1 HIGH or CE2 LOW to Power-down
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z[13]
10
70
35
5
10
0
25
25
tPD
70
70
tDBE
[11]
tLZBE
tHZBE
Write Cycle[14]
tWC
5
BHE/BLE HIGH to High-Z[11, 12]
25
Write Cycle Time
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
tPWE
tBW
50
60
30
0
BHE/BLE Pulse Width
tSD
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[11, 12]
WE HIGH to Low-Z[11]
tHD
tHZWE
tLZWE
25
5
Notes:
10. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the
CC(typ.)
CC(typ.)
specified I /I and 30-pF load capacitance.
OL OH
11. At any given temperature and voltage condition, t
given device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
12. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
13. When both byte enables are toggled together this value is 10 ns.
14. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , CE = V . All signals must be ACTIVE to initiate a
1
IL
IL
2
IH
Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
Document #: 38-05014 Rev. *F
Page 6 of 13
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CY62157CV30/33
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[15, 16]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[16, 17]
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZBE
BHE/BLE
t
LZBE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Notes:
15. Device is continuously selected. OE, CE = V , BHE and/or BLE = V , CE = V .
IH
1
IL
IL
2
16. WE is HIGH for Read cycle.
17. Address valid prior to or coincident with CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05014 Rev. *F
Page 7 of 13
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CY62157CV30/33
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[14, 18, 19]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
t
PWE
SA
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
VALID
NOTE 20
t
HZOE
Notes:
18. Data I/O is high-impedance if OE = V
.
IH
19. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
1
2
20. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05014 Rev. *F
Page 8 of 13
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CY62157CV30/33
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 Controlled) [14, 18, 19]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATAIN
DATA I/O
NOTE 20
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[19]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 20
DATAI/O
DATAIN VALID
t
LZWE
t
HZWE
Document #: 38-05014 Rev. *F
Page 9 of 13
[+] Feedback
CY62157CV30/33
Switching Waveforms (continued)
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19]
t
WC
ADDRESS
CE1
CE
2
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
t
t
HD
SD
DATA I/O
VALID
DATAIN
NOTE 20
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
Mode
Power
Standby (ISB
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
High Z
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Read
)
X
L
X
X
X
X
High Z
)
X
X
X
X
H
H
High Z
)
L
H
H
L
L
L
Data Out (I/OO–I/O15
)
)
L
H
H
L
H
L
Data Out (I/OO–I/O7); Read
I/O8–I/O15 in High Z
)
L
H
H
L
L
H
Data Out (I/O8–I/O15); Read
I/O0–I/O7 in High Z
Active (ICC)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
Output Disabled
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
High Z
Output Disabled
Output Disabled
Write
)
High Z
)
L
Data In (I/OO–I/O15
)
)
L
H
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
)
L
H
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Document #: 38-05014 Rev. *F
Page 10 of 13
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CY62157CV30/33
Typical DC and AC Characteristics[2]
Operating Current vs. Supply Voltage
14.0
12.0
10.0
14.0
12.0
10.0
14.0
12.0
10.0
MoBL
MoBL
MoBL
8.0
6.0
4.0
8.0
6.0
4.0
8.0
6.0
4.0
(f = fmax, 70ns)
(f = 1 MHz)
(f = fmax, 70ns)
(f = 1 MHz)
(f = fmax, 70ns)
(f = 1 MHz)
2.0
0.0
2.0
0.0
2.0
0.0
3.0
2.7
3.3
2.7
2.2
2.5
3.3
3.0
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
12.0
10.0
12.0
10.0
MoBL
10.0
8.0
MoBL
MoBL
8.0
8.0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
3.3
3.6
3.0
2.2
3.3
2.7
3.0
2.5
2.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
60
60
MoBL
MoBL
MoBL
50
40
30
50
40
30
50
40
30
20
20
20
10
0
10
0
10
0
3.6
3.0
3.3
2.2
2.5
2.7
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Document #: 38-05014 Rev. *F
Page 11 of 13
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CY62157CV30/33
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
70
CY62157CV30LL-70BAE
CY62157CV33LL-70BAXA
CY62157CV33LL-70BAE
51-85128
48-Ball (6 mm x 10 mm x 1.2 mm) FBGA
Automotive-E
Automotive-A
Automotive-E
Package Diagram
48-Ball (6 mm x 10 mm x 1.2 mm) FBGA (51-85128)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05ꢀ(48X
A1 CORNER
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
SEATING PLANE
C
51-85128-*D
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05014 Rev. *F
Page 12 of 13
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62157CV30/33
Document History Page
Document Title: CY62157CV30/33 512K x 16 Static RAM
Document Number: 38-05014
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106184
107241
05/10/01 HRT/MGN New data sheet – Advance Information
*A
07/24/01
MGN
Made corrections to Advance Information
Added 55 ns bin
*B
*C
*D
*E
109621
114218
238448
269729
03/11/02
MGN
Changed from Advance Information to Final
05/01/02 GUG/MGN Improved Typical and Max ICC values
See ECN
See ECN
AJU
SYT
Added Automotive Product Information
Added Automotive Product information for CY62157CV30 – 70 ns
Added IIX and IOZ values for Automotive range of CY62157CV33 – 70 ns
*F
498575
See ECN
NXR
Removed Industrial Operating Range
Removed 55 ns speed bin
Removed CY62157CV25 part number from the Product Offering
Added Automotive-A operating range
Updated the Ordering Information Table
Document #: 38-05014 Rev. *F
Page 13 of 13
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