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CY62158DV30LL-55ZXI [CYPRESS]

8-Mbit (1024K x 8) MoBL Static RAM; 8兆位（ 1024K ×8 ） MoBL静态RAM
CY62158DV30LL-55ZXI
型号： CY62158DV30LL-55ZXI
厂家： CYPRESS    CYPRESS
描述：

8-Mbit (1024K x 8) MoBL Static RAM
8兆位（ 1024K ×8 ） MoBL静态RAM
文件： 总11页 (文件大小：410K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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CY62158DV30  
MoBL  
8-Mbit (1024K x 8) MoBLStatic RAM  
This is ideal for providing More Battery Life™ (MoBL) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption. The device can be put into  
standby mode reducing power consumption by 85% when  
deselected (CE1 HIGH or CE2 LOW).  
Features  
• Very high speed: 45 ns, 55 ns and 70 ns  
— Wide voltage range: 2.20V – 3.60V  
• Ultra-low active power  
— Typical active current:1.5 mA @ f = 1 MHz  
— Typical active current: 12 mA @ f = fmax  
• Ultra-low standby power  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2  
(CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is  
then written into the location specified on the address pins (A0  
• Easy memory expansion with CE1, CE2, and OE  
through A19).  
features  
Reading from the device is accomplished by taking Chip  
Enable 1 (CE1) and Output Enable (OE) LOW and Chip  
Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW and CE2 HIGH and WE  
LOW). See the truth table for a complete description of read  
and write modes.  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered in a 48-ball BGA, 48-pin TSOPI, and  
44-pin TSOPII  
Functional Description[1]  
The CY62158DV30 is a high-performance CMOS static RAMs  
organized as 1024K words by 8 bits. This device features  
advanced circuit design to provide ultra-low active current.  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
Data in Drivers  
A0  
A1  
A2  
A3  
A4  
1
2
A
A5  
A6  
3
4
5
1024K x 8  
A7  
ARRAY  
A98  
A10  
A11  
A12  
6
7
POWER  
DOWN  
COLUMN  
CE  
CE  
1
2
DECODER  
I/O  
WE  
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05391 Rev. *D  
Revised June 17, 2004  
[+] Feedback  
CY62158DV30  
MoBL  
Pin Configuration[2, 3, 4]  
FBGA  
Top View  
1
2
4
3
5
6
DNU  
DNU  
A
2
A
A
OE  
CE2  
0
1
A
B
C
A
DNU  
DNU  
DNU  
A
CE1  
4
3
A
A
I/O  
I/O  
DNU  
5
6
0
4
V
A
V
CC  
I/O  
A17  
SS  
D
E
F
I/O1  
7
5
V
DNU  
A
16  
I/O  
V
CC  
SS  
I/O  
2
6
A
A
15  
I/O  
I/O  
DNU  
NC  
DNU  
WE  
14  
3
7
A
A
G
H
DNU  
A18  
DNU  
A19  
13  
12  
A
A
A
A
10  
9
11  
8
A
48TSOPI  
44 TSOPII  
Top View  
Top View  
44  
1
A
A
5
4
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
A
A
6
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
3
A15  
A14  
A13  
A12  
A11  
A10  
A9  
1
2
3
4
5
6
7
8
9
48  
A16  
BYTE  
Vss  
A
A
2
7
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
OE  
A
1
A19  
I/O7  
DNU  
I/O6  
DNU  
I/O5  
DNU  
I/O4  
Vcc  
CE2  
A8  
A
0
CE1  
DNU  
DNU  
DNU  
A8  
NC  
DNU  
DNU 10  
WE  
CE  
11  
12  
I/O  
1
CC  
I/O  
0
7
6
2
DNU 13  
DNU 14  
DNU 15  
DNU  
I/O3  
DNU  
I/O2  
DNU  
I/O1  
DNU  
I/O0  
OE  
I/O  
I/O  
V
V
SS  
A18  
A17  
A7  
16  
17  
18  
19  
20  
21  
22  
23  
24  
V
V
SS  
CC  
32  
I/O  
I/O  
2
5
4
A6  
31  
30  
29  
28  
27  
26  
25  
I/O  
I/O  
3
A5  
A4  
DNU  
DNU  
DNU  
DNU  
A3  
Vss  
A2  
CE  
A0  
1
A1  
A
WE 17  
9
18  
A
A19  
10  
19  
A
A
18  
11  
A
20  
21  
22  
A
12  
13  
17  
A
A
24  
23  
16  
A
A
14  
15  
Notes:  
2. NC pins are not internally connected to the die.  
3. DNU pins have to be left floating.  
4. The BYTE pin in the TSOPI package has to be tied LOW to use the device as 1M x 8 SRAM. The 48-TSOPI package can also be used as a 512K × 16 SRAM  
by tying the BYTE signal HIGH. For 512K x 16 functionality, please refer to the CY62157DV30 data sheet.  
Document #: 38-05391 Rev. *D  
Page 2 of 11  
[+] Feedback  
CY62158DV30  
MoBL  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
Static Discharge Voltage............................................>2001V  
(Above which the useful life may be impaired. For user guide-  
(per MIL-STD-883, Method 3015)  
lines, not tested.)  
Latch-up Current......................................................>200 mA  
Storage Temperature ..................................–65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied...............................................55°C to +125°C  
Ambient  
Supply Voltage to Ground Potential.–0.3V to Vcc(max) + 0.3V  
Temperature  
[7]  
Product  
CY62158DV30L  
CY62158DV30LL  
Range  
(TA)  
VCC  
DC Voltage Applied to Outputs  
in High-Z State[5, 6]......................... –0.3V to VCC(max) + 0.3V  
Industrial –40°C to +85°C 2.2V – 3.6V  
DC Input Voltage[5, 6] ..................... –0.3V to VCC(max) + 0.3V  
Product Portfolio  
Power Dissipation  
Operating ICC (mA)  
f = 1 MHz f = fmax  
VCC Range (V)  
Speed  
Standby ISB2(µA)  
Product  
CY62158DV30L  
Min.  
2.2  
Typ.[8]  
3.0  
Max.  
3.6  
(ns)  
Typ.[8]  
Max.  
3
Typ.[8]  
Max.  
20  
Typ.[8]  
Max.  
20  
45,55,70  
1.5  
12  
2
CY62158DV30LL  
2.2  
3.0  
3.6  
45,55,70  
1.5  
3
12  
15  
2
8
Electrical Characteristics Over the Operating Range  
CY62158DV30  
Parameter  
VOH  
Description  
Output HIGH Voltage  
Test Conditions  
VCC = 2.20V  
Min. Typ.[8]  
2.0  
2.4  
Max.  
Unit  
V
V
V
V
V
V
V
IOH = –0.1 mA  
OH = –1.0 mA  
IOL = 0.1 mA  
OL = 2.1mA  
I
VCC = 2.70V  
VCC = 2.20V  
VCC = 2.70V  
VOL  
VIH  
VIIL  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
0.4  
0.4  
VCC + 0.3V  
VCC + 0.3V  
I
VCC = 2.2V to 2.7V  
VCC= 2.7V to 3.6V  
VCC = 2.2V to 2.7V  
CC= 2.7V to 3.6V  
GND < VI < VCC  
GND < VO < VCC, Output Disabled  
1.8  
2.2  
–0.3  
–0.3  
–1  
0.6  
0.8  
+1  
+1  
20  
15  
3
3
20  
8
V
V
IIX  
IOZ  
ICC  
Input Leakage Current  
Output Leakage Current  
µA  
µA  
mA  
mA  
mA  
mA  
µA  
–1  
VCC Operating Supply  
f = fMAX = 1/tRC  
VCC = VCCmax  
L
LL  
L
LL  
L
12  
Current  
IOUT = 0 mA  
CMOS levels  
f = 1 MHz  
1.5  
ISB1  
Automatic CE  
CE1 > VCC− 0.2V, CE2 < 0.2V  
2
2
Power-down Current —  
CMOS Inputs  
VIN > VCC – 0.2V, VIN < 0.2V)  
LL  
f = f  
(Address and Data Only),  
MAX  
f = 0 (OE, and WE), VCC = 3.60V  
CE1 > VCC – 0.2V or CE2 < 0.2V,  
ISB2  
Automatic CE  
L
LL  
2
2
20  
8
µA  
Power-down Current —  
CMOS Inputs  
VIN > VCC – 0.2V or VIN < 0.2V,  
f = 0, VCC = 3.60V  
Notes:  
5. V  
6. V  
= –2.0V for pulse durations less than 20 ns.  
IL(min.)  
IH(max)  
= V +0.75V for pulse duration less than 20ns.  
CC  
7. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.  
cc  
cc  
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V  
CC  
, T = 25°C.  
A
CC(typ.)  
Document #: 38-05391 Rev. *D  
Page 3 of 11  
[+] Feedback  
CY62158DV30  
MoBL  
Capacitance[9, 10.]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
CC = VCC(typ.)  
Max.  
10  
10  
Unit  
pF  
pF  
CIN  
COUT  
V
Thermal Resistance  
Parameter  
Description  
Test Conditions  
BGA  
72  
TSOP II  
75.13  
TSOP I  
74.88  
Unit  
°C/W  
ΘJA  
Thermal Resistance[9]  
(Junction to Ambient)  
Still Air, soldered on a 3 x 4.5 inch, four-layer  
printed circuit board  
ΘJC  
Thermal Resistance[9]  
(Junction to Case)  
8.86  
8.95  
8.6  
°C/W  
AC Test Loads and Waveforms [11]  
R1  
VCC  
ALL INPUT PULSES  
90%  
OUTPUT  
VCC  
GND  
90%  
10%  
10%  
R2  
30 pF / 50 pF  
Fall time: 1 V/ns  
Rise Time: 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THÉVENIN EQUIVALENT  
RTH  
OUTPUT  
VTH  
Parameters  
2.50V  
3.0V  
1103  
1554  
645  
Unit  
R1  
R2  
RTH  
VTH  
16667  
15385  
8000  
1.20  
Ω
Ω
Ω
V
1.75  
Data Retention Characteristics (Over the Operating Range)  
Parameter  
VDR  
ICCDR  
Description  
VCC for Data Retention  
Data Retention Current VCC = 1.5V  
Conditions  
Min.  
1.5  
Typ.[8]  
Max.  
Unit  
V
L
10  
4
µA  
µA  
CE1 > VCC − 0.2V or CE2 <0.2V  
VIN > VCC − 0.2V or VIN < 0.2V  
LL  
[9]  
tCDR  
Chip Deselect to Data  
Retention Time  
Operation Recovery  
0
ns  
ns  
[12]  
tR  
tRC  
Time  
Notes:  
9. Tested initially and after any design or process changes that may affect these parameters.  
10. The input capacitance on the CE pin is 15 pF.  
2
11. Test condition for the 45 ns part is a load capacitance of 30 pF.  
12. Full Device AC operation requires linear V ramp from V to V  
> 100 µs or stable at V > 100 µs.  
CC(min.)  
CC  
DR  
CC(min.)  
Document #: 38-05391 Rev. *D  
Page 4 of 11  
[+] Feedback  
CY62158DV30  
MoBL  
Data Retention Waveform  
DATA RETENTION MODE  
> 1.5 V  
VCC(min)  
V
V
CC  
VCC(min)  
DR  
t
t
R
CDR  
CE1  
or  
CE  
2
Switching Characteristics Over the Operating Range [13]  
45 ns [11]  
55 ns  
70 ns  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
Read Cycle  
tRC  
Read Cycle Time  
45  
10  
55  
10  
70  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
45  
55  
70  
tOHA  
Data Hold from Address Change  
CE1 LOW and CE2 HIGH to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z[14]  
OE HIGH to High Z[14, 15]  
CE1 LOW and CE2 HIGH to Low Z[14]  
CE1 HIGH or CE2 LOW to High Z[14, 15]  
CE1 LOW and CE2 HIGH to Power-Up  
CE1 HIGH or CE2 LOW to Power-Down  
tACE  
45  
25  
55  
25  
70  
35  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
5
10  
0
5
10  
0
5
15  
20  
45  
20  
20  
55  
25  
25  
25  
10  
10  
tPD  
Write Cycle[16]  
tWC  
Write Cycle Time  
45  
40  
40  
0
55  
40  
40  
0
70  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCE  
CE1 LOW and CE2 HIGH to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tAW  
tHA  
tSA  
0
0
0
tPWE  
tSD  
35  
25  
0
40  
25  
0
45  
30  
0
Data Set-Up to Write End  
Data Hold from Write End  
WE LOW to High Z[14, 15]  
WE HIGH to Low Z[14]  
tHD  
tHZWE  
15  
20  
25  
tLZWE  
10  
10  
10  
Notes:  
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1V/ns), timing reference levels of V  
/2, input  
CC(typ.)  
pulse levels of 0 to V  
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.  
OL OH  
CC(typ.)  
14. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
15. t  
, t  
, and t  
transitions are measured when the outputs enter a high impedance state.  
HZOE HZCE  
HZWE  
16. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these  
1
IL  
2
IH  
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.  
Document #: 38-05391 Rev. *D  
Page 5 of 11  
[+] Feedback  
CY62158DV30  
MoBL  
Switching Waveforms  
Read Cycle No. 1 (Address Transition Controlled)[17, 18]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 (OE Controlled)[18, 19]  
ADDRESS  
t
RC  
CE  
1
CE  
2
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
ICC  
t
PU  
50%  
50%  
SUPPLY  
ISB  
CURRENT  
Write Cycle No. 1(WE Controlled) [16, 20, 22]  
t
WC  
ADDRESS  
t
SCE  
CE  
1
CE  
2
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
OE  
t
t
SD  
HD  
VALID DATA  
NOTE [20]  
DATA I/O  
t
HZOE  
Notes:  
17. Device is continuously selected. OE, CE = V , CE = V .  
IH  
1
IL  
2
18. WE is HIGH for read cycle.  
19. Address valid prior to or coincident with CE transition LOW and CE transition HIGH.  
1
2
Document #: 38-05391 Rev. *D  
Page 6 of 11  
[+] Feedback  
CY62158DV30  
MoBL  
Switching Waveforms (continued)  
Write Cycle No. 2(CE1 or CE2 Controlled)[16, 20, 22]  
t
WC  
ADDRESS  
t
SCE  
CE  
1
t
SA  
CE  
2
t
t
HA  
AW  
t
PWE  
WE  
OE  
t
t
HD  
SD  
DATA I/O  
VALID DATA  
Write Cycle No. 3 (WE Controlled, OE LOW) [22]  
t
WC  
ADDRESS  
t
SCE  
CE  
1
CE  
2
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
NOTE [21]  
DATAI/O  
VALID DATA  
t
t
LZWE  
HZWE  
Truth Table  
CE1  
H
X
L
L
CE2  
X
L
H
H
H
WE  
X
X
H
H
OE  
X
X
L
H
X
Inputs/Outputs  
High Z  
High Z  
Data Out (I/O0-I/O7)  
High Z  
Mode  
Power  
Deselect/Power-down  
Deselect/Power-down  
Read  
Output Disabled  
Write  
Standby (ISB  
Standby (ISB  
Active (ICC  
)
)
)
Active (Icc)  
Active (Icc)  
L
L
Data in (I/O0-I/O7)  
Notes:  
20. Data I/O is high impedance if OE = V  
.
IH  
21. During this period, the I/Os are in output state and input signals should not be applied.  
22. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high-impedance state.  
1
2
Document #: 38-05391 Rev. *D  
Page 7 of 11  
[+] Feedback  
CY62158DV30  
MoBL  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
Package Type  
45  
CY62158DV30L-45BVI  
CY62158DV30LL-45BVI  
CY62158DV30L-45ZXI  
CY62158DV30LL-45ZXI  
CY62158DV30L-45ZSXI  
CY62158DV30LL-45ZSXI  
CY62158DV30L-55BVI  
CY62158DV30LL-55BVI  
CY62158DV30L-55ZXI  
CY62158DV30LL-55ZXI  
CY62158DV30L-55ZSXI  
CY62158DV30LL-55ZSXI  
CY62158DV30L-70BVI  
CY62158DV30LL-70BVI  
CY62158DV30L-70ZXI  
CY62158DV30LL-70ZXI  
CY62158DV30L-70ZSXI  
CY62158DV30LL-70ZSXI  
BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm)  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
45  
45  
55  
55  
55  
70  
70  
70  
Z-48  
48 Pin TSOP I (Pb-free)  
44 Pin TSOP II (Pb-free)  
ZS-44  
BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm)  
Z-48  
48 Pin TSOP I (Pb-free)  
44 Pin TSOP II (Pb-free)  
ZS-44  
BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm)  
Z-48  
48 Pin TSOP I (Pb-free)  
44 Pin TSOP II (Pb-free)  
ZS-44  
Document #: 38-05391 Rev. *D  
Page 8 of 11  
[+] Feedback  
CY62158DV30  
MoBL  
Package Diagrams  
48-lead VFBGA (6 x 8 x 1 mm) BV48A  
51-85150-*B  
48-Lead TSOP I (12 mm x 18.4 mm x 1.0 mm) Z48A  
DIMENSIONS IN INCHES[MM] MIN.  
MAX.  
JEDEC # MO-142  
0.037[0.95]  
0.041[1.05]  
N
1
0.020[0.50]  
TYP.  
0.472[12.00]  
0.007[0.17]  
0.011[0.27]  
0.002[0.05]  
0.006[0.15]  
0.724 [18.40]  
0.047[1.20]  
MAX.  
0.787[20.00]  
0.004[0.10]  
0.008[0.21]  
0.010[0.25]  
GAUGE PLANE  
0.020[0.50]  
0.028[0.70]  
0°-5°  
51-85183-*A  
Document #: 38-05391 Rev. *D  
Page 9 of 11  
[+] Feedback  
CY62158DV30  
MoBL  
Package Diagrams (continued)  
44-pin TSOP II ZS44  
51-85087-*A  
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company  
names mentioned in this document are trademarks of their respective holders.  
Document #: 38-05391 Rev. *D  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
[+] Feedback  
CY62158DV30  
MoBL  
Document History Page  
Document Title:CY62158DV30 MoBL8-Mbit (1024K x 8) MoBLStatic RAM  
Document Number: 38-05391  
Orig. of  
REV.  
**  
*A  
*B  
*C  
ECN NO. Issue Date Change  
Description of Change  
126293  
131014  
133114  
211602  
05/22/03  
11/25/03  
01/24/04  
See ECN  
HRT  
CBD  
CBD  
AJU  
New Data Sheet  
Change from Advance to Preliminary  
Minor Change: MPN change and upload  
Change from Preliminary to Final  
Changed Marketing part # from CY62158DV to CY62158DV30 in the “Title” and  
in the “Ordering Information” table  
Added footnote 4 and 10  
Modified footnote 7 to include ramp time and wait time  
Removed MAX value for VDR on “Data Retention Characteristics” table  
Changed ordering code for Pb-free parts  
Modified voltage limits in Maximum Ratings section  
*D  
239450  
See ECN  
SYT/AJU Added footnote #11  
Added 45 ns and 70 ns Speed Bins  
Document #: 38-05391 Rev. *D  
Page 11 of 11  
[+] Feedback  

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