CY7B933-400JXCT_技术文档

CY7B923

CY7B933

HOTLink™ Transmitter/Receiver

twisted pair). Standard HOTLink data rates range from

160-330 Mbits/second. Higher speed HOTLink is also avail-

able for high speed applications (160-400 Mbits/second), as

well as for those Low Cost applications HOTLink-155 (150-160

Mbits/second operations). Figure 1 illustrates typical connec-

tions to host systems or controllers.

Features

• Fibre Channel compliant

• IBM ESCON compliant

• DVB-ASI compliant

• ATM compliant

®

Eight bits of user data or protocol information are loaded into

the HOTLink transmitter and are encoded. Serial data is shift-

ed out of the three differential positive ECL (PECL) serial ports

at the bit rate (which is 10 times the byte rate).

• 8B/10B-coded or 10-bit unencoded

• Standard HOTLink: 160–330 Mbps

• High Speed HOTLink: 160–400 Mbps for high speed ap-

plications

The HOTLink receiver accepts the serial bit stream at its dif-

ferential line receiver inputs and, using a completely integrated

PLL Clock Synchronizer, recovers the timing information nec-

essary for data reconstruction. The bit stream is deserialized,

decoded, and checked for transmission errors. Recovered

bytes are presented in parallel to the receiving host along with

a byte-rate clock.

• Low Speed HOTLink: 150–160 Mbps for Low Cost Fiber

applications

• TTL synchronous I/O

• No external PLL components

• Triple PECL 100K serial outputs

• Dual PECL 100K serial inputs

• Low power: 350 mW (Tx), 650 mW (Rx)

• Compatible withfiber-optic modules,coaxialcable,and

twisted pair media

The 8B/10B encoder/decoder can be disabled in systems that

already encode or scramble the transmitted data. I/O signals

are available to create a seamless interface with both asyn-

chronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e.,

CY7C44X). A Built-In Self-Test pattern generator and checker

allows testing of the transmitter, receiver, and the connecting

link as a part of a system diagnostic check.

• Built-In Self-Test

• Single +5V supply

• 28-pin SOIC/PLCC/LCC

0.8 BiCMOS

•

µ

HOTLink devices are ideal for a variety of applications where

a parallel interface can be replaced with a high-speed

point-to-point serial link. Applications include interconnecting

workstations, servers, mass storage, and video transmission

equipment.

Functional Description

The CY7B923 HOTLink™ Transmitter and CY7B933 HOTLink

Receiver are point-to-point communications building blocks

that transfer data over high-speed serial links (fiber, coax, and

CY7B923 Transmitter Logic Block Diagram

CY7B933 Receiver Logic Block Diagram

SC/D(D )

a

D

b −

0− 7

h

RF

FRAMER

(D

)

SVS(D)

A/B

j

RP ENN ENA

FOTO

INA+

INA−

DATA

ENABLE

SHIFTER

INB(INB+)

SI(INB− )

INPUT REGISTER

CKW

DECODER

REGISTER

PECL

TTL

ENCODER

SO

CLOCK

SYNC

CLOCK

GENERATOR

OUTA

DECODER

SHIFTER

REFCLK

OUTB

OUTC

OUTPUT

REGISTER

MODE

TEST

LOGIC

TEST

LOGIC

MODE

BISTEN

B923–1

Q

b −

0− 7

h

CKR

RDY

RVS(Q)

j

(Q

)

B923–2

SC/D(Q )

a

HOTLink is a trademark of cypress Semiconductor Corporation.

ESCON is a registered trademark of IBM.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

April 5, 1999

CY7B923

CY7B933

SERIAL LINK

HOST

B923–3

Figure 1. HOTLink System Connections

CY7B923 Transmitter Pin Configurations

CY7B933 Receiver Pin Configurations

SOIC

Top View

SOIC

Top View

1

28

INB(INB+)

SI(INB

MODE

INA

INA+

A/B

BISTEN

RF

−

1

28

27

26

OUTB

OUTC

OUTC+

OUTB+

OUTA+

−

2

27

26

)

−

2

3

OUTA

FOTO

ENN

−

4

25

24

23

22

21

REFCLK

V

CCN

4

25

24

23

22

21

5

V

CCQ

BISTEN

GND

MODE

RP

5

6

GND

RDY

GND

SO

CKR

6

ENA

7

V

CCQ

7B923

7B933

8

V

CCQ

CKW

GND

SC/D(D )

a

8

V

CCN

9

20

19

18

17

16

15

V

CCQ

GND

9

20

19

18

17

16

15

10

11

12

13

SC/D (Q )

RVS(Q)

j

SVS(D )

j

10

11

12

13

a

Q (Q )

(Q ) Q

(D ) D

D (D )

0

b

h

7

6

5

4

h

7

6

5

4

0

b

Q (Q )

(Q ) Q

(D )D

D (D )

1

c

g

1

c

Q (Q )

(Q ) Q

f

(Q ) Q

i

(D )D

f

(D)D

i

D (D )

2

d

2

d

Q (Q )

3 e

B923–7

14

D (D )

14

3

e

B923–5

PLCC/LCC

Top View

PLCC/LCC

Top View

4

3

2

1

2726

28

4

3

2

1

2726

28

25

24

23

22

21

20

19

BISTEN

GND

FOTO

ENN

ENA

5

6

25

24

23

22

21

20

19

RF

GND

RDY

GND

REFCLK

5

6

7

MODE

RP

V

CCQ

7B923

8

V

CCQ

7

SO

CKR

7B933

V

CCQ

9

8

CKW

GND

SC/D(D )

a

SVS(D )

10

11

9

V

j

7

CCN

CCQ

(D )D

h

RVS(Q)

GND

10

11

16

1213 14 15

1718

j

(Q ) Q

SC/D (Q )

16

1213 14 15

1718

h

7

a

B923–4

B923–6

2

CY7B923

CY7B933

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage ........................................... >4001V

(per MIL−STD−883, Method 3015)

Storage Temperature......................................−65°C to +150°C

Latch-Up Current..................................................... >200 mA

Ambient Temperature with

Power Applied..................................................−55°C to +125°C

Operating Range

Ambient

Supply Voltage to Ground Potential................. −0.5V to +7.0V

DC Input Voltage ................................................ −0.5V to +7.0V

Output Current into TTL Outputs (LOW)......................30 mA

Output Current into PECL outputs (HIGH)...................−50 mA

Range

Commercial

Industrial

Military

Temperature

0°C to +70°C

−40°C to +85°C

V

CC

5V ± 10%

−55°C to +125°C

Case Temperature

Pin Descriptions

CY7B923 HOTLink Transmitter

Name

I/O

Description

D

(D

TTL In

Parallel Data Input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW

(or on the next rising CKW with ENN LOW). If ENA and ENN are HIGH, a Null character (K28.5) is

0−7

)

b − h

sent. When MODE is HIGH, D

become D

respectively.

0, 1, ...7

b, c,...h

SC/D (D ) TTL In

Special Character/Data Select. A HIGH on SC/D when CKW rises causes the transmitter to encode

the pattern on D as a control code (Special Character), while a LOW causes the data to be coded

a

0−7

using the 8B/10B data alphabet. When MODE is HIGH, SC/D (D ) acts as D input. SC/D has the

a

same timing as D

.

0−7

SVS

TTL In

Send Violation Symbol. If SVS is HIGH when CKW rises, a Violation symbol is encoded and sent

while the data on the parallel inputs is ignored. If SVS is LOW, the state of D and SC/D determines

the code sent. In normal or test mode, this pin overrides the BIST generator and forces the trans-

mission of a Violation code. When MODE is HIGH (placing the transmitter in unencoded mode),

(D )

j

0−7

SVS (D ) acts as the D input. SVS has the same timing as D .

j

0−7

ENA

ENN

Enable Parallel Data. If ENA is LOW on the rising edge of CKW, the data is loaded, encoded, and

sent. If ENA and ENN are HIGH, the data inputs are ignored and the Transmitter will insert a Null

character (K28.5) to fill the space between user data. ENA may be held HIGH/LOW continuously or

it may be pulsed with each data byte to be sent. If ENA is being used for data control, ENN will

normally be strapped HIGH, but can be used for BIST function control.

Enable Next Parallel Data. If ENN is LOW, the data appearing on D

at the next rising edge of

0−7

CKW is loaded, encoded, and sent. If ENA and ENN are HIGH, the data appearing on D

at the

0−7

next rising edge of CKW will be ignored and the Transmitter will insert a Null character to fill the space

between user data. ENN may be held HIGH/LOW continuously or it may be pulsed with each data

byte sent. If ENN is being used for data control, ENA will normally be strapped HIGH, but can be

used for BIST function control.

CKW

TTL In

Clock Write. CKW is both the clock frequency reference for the multiplying PLL that generates the

high−speed transmit clock, and the byte rate write signal that synchronizes the parallel data input.

CKW must be connected to a crystal controlled time base that runs within the specified frequency

range of the Transmitter and Receiver.

FOTO

Fiber Optic Transmitter Off. FOTO determines the function of two of the three PECL transmitter

output pairs. If FOTO is LOW, the data encoded by the Transmitter will appear at the outputs con-

tinuously. If FOTO is HIGH, OUTA± and OUTB± are forced to their “logic zero” state (OUT+ = LOW

and OUT− = HIGH), causing a fiber optic transmit module to extinguish its light output. OUTC is

unaffected by the level on FOTO, and can be used as a loop-back signal source for board-level

diagnostic testing.

3

CY7B923

CY7B933

CY7B923 HOTLink Transmitter (continued)

Name

I/O

Description

OUTA±

OUTB±

OUTC±

PECL Out Differential Serial Data Outputs. These PECL 100K outputs (+5V referenced) are capable of driving

terminated transmission lines or commercial fiber optic transmitter modules. Unused pairs of outputs

can be wired to V to reduce power if the output is not required. OUTA± and OUTB± are controlled by the

CC

level on FOTO, and will remain at their “logical zero” states when FOTO is asserted. OUTC± is unaffected

by the level on FOTO. (OUTA+ and OUTB+ are used as a differential test clock input while in Test mode, i.e.,

MODE=UNCONNECTED or forced to V /2.)

CC

MODE

3-Level In Encoder Mode Select. The level on MODE determines the encoding method to be used. When

wired to GND, MODE selects 8B/10B encoding. When wired to V , data inputs bypass the encoder

CC

and the bit pattern on D goes directly to the shifter. When left floating (internal resistors hold the input at

a-j

V

/2) the internal bit-clock generator is disabled and OUTA+/OUTB+ become the differential bit clock to be

CC

used for factory test. In typical applications MODE is wired to V or GND.

CC

BISTEN

TTL In

Built-In Self-Test Enable. When BISTEN is LOW and ENA and ENN are HIGH, the transmitter sends an

alternating 1−0 pattern (D10.2 or D21.5). When either ENA or ENN is set LOW and BISTEN is LOW, the

transmitter begins a repeating test sequence that allows the Transmitter and Receiver to work together to test

the function of the entire link. In normal use this input is held HIGH or wired to V . The BIST generator is

CC

a free-running pattern generator that need not be initialized, but if required, the BIST sequence can be

initialized by momentarily asserting SVS while BISTEN is LOW. BISTEN has the same timing as D

.

0−7

RP

TTL Out

Read Pulse. RP is a 60% LOW duty-cycle byte-rate pulse train suitable for the read pulse in CY7C42X

FIFOs. The frequency on RP is the same as CKW when enabled by ENA, and duty cycle is independent of

the CKW duty cycle. Pulse widths are set by logic internal to the transmitter. In BIST mode, RP will remain

HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time per BIST loop.

V

Power for output drivers.

Power for internal circuitry.

Ground.

CCN

CCQ

GND

CY7B933 HOTLink Receiver

Name

I/O

Description

Q Parallel Data Output. Q contain the most recently received data. These outputs change synchro-

0−7

Q

TTL Out

0−7

(Q

)

nously with CKR. When MODE is HIGH, Q

become Q

respectively.

b − h

0, 1, ...7

b, c,...h

SC/D(Q )

TTL Out

Special Character/Data Select. SC/D indicates the context of received data. HIGH indicates a Control

(Special Character) code, LOW indicates a Data character. When MODE is HIGH (placing the receiver in

a

Unencoded mode), SC/D acts as the Q output. SC/D has the same timing as Q

.

a

0−7

RVS (Q)

Received Violation Symbol. A HIGH on RVS indicates that a code rule violation has been detected

in the received data stream. A LOW shows that no error has been detected. In BIST mode, a LOW

on RVS indicates correct operation of the Transmitter, Receiver, and link on a byte-by-byte basis.

j

When MODE is HIGH (placing the receiver in Unencoded mode), RVS acts as the Q output. RVShas

j

the same timing as Q

.

0−7

RDY

TTL Out

Data Output Ready. A LOW pulse on RDY indicates that new data has been received and is ready to be

delivered. A missing pulse on RDY shows that the received data is the Null character (normally inserted by

the transmitter as a pad between data inputs). In BIST mode RDY will remain LOW for all but the last byte

of a test loop and will pulse HIGH one byte time per BIST loop.

CKR

A/B

TTL Out

PECL in

Clock Read. This byte rate clock output is phase and frequency aligned to the incoming serial data

stream. RDY, Q , SC/D, and RVS all switch synchronously with the rising edge of this output.

0−7

Serial Data Input Select. This PECL 100K (+5V referenced) input selects INA or INB as the active

data input. If A/B is HIGH, INA is connected to the shifter and signals connected to INA will be decoded. If

A/B is LOW INB is selected.

INA±

Diff In

Serial Data Input A. The differential signal at the receiver end of the communication link may be

connected to the differential input pairs INA± or INB±. Either the INA pair or the INB pair can be used as

the main data input and the other can be used as a loopback channel or as an alternative data input selected

by the state of A/B.

4

CY7B923

CY7B933

CY7B933 HOTLink Receiver (continued)

Name

INB

I/O

Description

Serial Data Input B. This pin is either a single-ended PECL data receiver (INB) or half of the INB

PECL in

(Diff In)

(INB+)

differential pair. If SO is wired to V , then INB± can be used as differential line receiver interchangeably

CC

with INA±. If SO is normally connected and loaded, INB becomes a single-ended PECL 100K (+5V refer-

enced) serial data input. INB is used as the test clock while in Test mode.

SI

(INB−)

PECL in

(Diff In)

Status Input. This pin is either a single-ended PECL status monitor input (SI) or half of the INB

differential pair. If SO is wired to V , then INB± can be used as differential line receiver interchangeably

CC

with INA±. IfSOisnormallyconnectedandloaded,SIbecomesasingle-endedPECL100K(+5Vreferenced)

status monitor input, which is translated into a TTL-level signal at the SO pin.

SO

RF

TTL Out

TTL In

Status Out. SO is the TTL-translated output of SI. It is typically used to translate the Carrier Detect

output from a fiber-optic receiver connected to SI. When this pin is normally connected and loaded

(without any external pull-up resistor), SO will assume the same logical level as SI and INB will

become a single-ended PECL serial data input. If the status monitor translation is not desired, then

SO may be wired to V and the INB± pair may be used as a differential serial data input.

CC

Reframe Enable. RF controls the Framer logic in the Receiver. When RF is held HIGH, each SYNC

(K28.5) symbol detected in the shifter will frame the data that follows. If is HIGH for 2,048 consecutive

bytes, the internal framer switches to double-byte mode. When RF is held LOW, the reframing logic

is disabled. The incoming data stream is then continuously deserialized and decoded using byte

boundaries set by the internal byte counter. Bit errors in the data stream will not cause alias SYNC

characters to reframe the data erroneously.

REFCLK

MODE

TTL In

Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL.

REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream.

REFCLK must be connected to a crystal-controlled time base that runs within the frequency limits of

the Tx/Rx pair, and the frequency must be the same as the transmitter CKW frequency (within

CKW±0.1%).

3-Level In Decoder Mode Select. The level on the MODE pin determines the decoding method to be used.

When wired to GND, MODE selects 8B/10B decoding. When wired to V , registered shifter contents

CC

bypass the decoder and are sent to Q directly. When left floating (internal resistors hold the MODE pin at

a−j

V

/2)theinternalbitclockgeneratorisdisabledandINBbecomesthebitratetestclocktobeusedfor factory

CC

test. In typical applications, MODE is wired to V or GND.

CC

BISTEN

TTL In

Built-In Self-Test Enable. When BISTEN is LOW the Receiver awaits a D0.0 (sent once per BIST loop)

character and begins a continuous test sequence that tests the functionality of the Transmitter, the Receiver,

and the link connecting them. In BIST mode the status of the test can be monitored with RDY and RVS

outputs. In normal use BISTEN is held HIGH or wired to V . BISTEN has the same timing as Q

.

CC

0−7

V

Power for output drivers.

Power for internal circuitry.

Ground.

CCN

CCQ

GND

In BIST mode, the Input register becomes the signature pat-

tern generator by logically converting the parallel Input register

into a Linear Feedback Shift Register (LFSR). When enabled,

this LFSR will generate a 511-byte sequence that includes all

Data and Special Character codes, including the explicit viola-

tion symbols. This pattern provides a predictable but pseu-

do-random sequence that can be matched to an identical

LFSR in the Receiver.

CY7B923 HOTLink Transmitter Block Diagram

Description

Input Register

The Input register holds the data to be processed by the HOT-

Link transmitter and allows the input timing to be made consis-

tent with standard FIFOs. The Input register is clocked by CKW

and loaded with information on the D , SC/D, and SVS pins.

0−7

Two enable inputs (ENA and ENN) allow the user to choose when

data is loaded in the register. Asserting ENA (Enable, active LOW)

causes the inputs to be loaded in the register on the rising edge of

CKW. If ENN (Enable Next, active LOW) is asserted when CKW

rises, the data present on theinputs on the next rising edge of CKW

will be loaded into the Input register. If neither ENA nor ENN are

asserted LOW on the rising edge of CKW, then a SYNC (K28.5)

character is sent. These two inputs allow proper timing and function

for compatibility with either asynchronous FIFOs or clocked FIFOs

without external logic, as shown in Figure 5.

Encoder

The Encoder transforms the input data held by the Input reg-

ister into a form more suitable for transmission on a serial in-

terface link. The code used is specified by ANSI X3.230 (Fibre

Channel) and the IBM ESCON channel (code tables are at the

end of this datasheet). The eight D

data inputs are converted

0−7

to either aData symbol or a Special Character, depending upon the

state of the SC/D input. If SC/D is HIGH, the data inputs represent

a control code and are encoded using the Special Character code

5

CY7B923

CY7B933

table. If SC/D is LOW, the data inputs are converted using the Data

code table. If a byte time passes with the inputs disabled, the En-

coder will output a Special Character Comma K28.5 (or SYNC) that

will maintain link synchronization. SVS input forces the transmis-

sion of a specified Violation symbol to allow the user to check error

handling system logic in the controller or for proprietary applications.

pulse stream will insure correct data transfers between asynchro-

nous FIFOs and the transmitter input latch with no external logic.

Test Logic

Test logic includes the initialization and control for the Built-In

Self-Test (BIST) generator, the multiplexer for Test mode clock

distribution, and control logic to properly select the data encod-

ing. Test logic is discussed in more detail in the CY7B923

HOTLink Transmitter Operating Mode Description.

The 8B/10B coding function of the Encoder can be bypassed

for systems that include an external coder or scrambler func-

tion as part of the controller. This bypass is controlled by set-

ting the MODE select pin HIGH. When in bypass mode, D

(note that bit order is specified in the Fibre Channel 8B/10B code)

a−j

CY7B933 HOTLink Receiver Block Diagram

Description

become the ten inputs to the Shifter, with D being the first bit to be

a

shifted out.

Serial Data Inputs

Shifter

Two pairs of differential line receivers are the inputs for the

serial data stream. INA± or INB± can be selected with the A/B

input. INA± is selected with A/B HIGHand INB± is selected with A/B

LOW. The threshold of A/B is compatiblewith the ECL 100Ksignals

from PECL fiber optic interface modules. TTL logic elements can be

used to select the A or B inputs by adding a resistor pull-up to the

TTL driver connected to A/B. The differential threshold of INA± and

INB± will accommodate wire interconnect with filtering losses or

The Shifter accepts parallel data from the Encoder once each

byte time and shifts it to the serial interface output buffers using

a PLL multiplied bit clock that runs at ten (10) times the byte

clock rate. Timing for the parallel transfer is controlled by the

counter included in the Clock Generator and is not affected by

signal levels or timing at the input pins.

OutA, OutB, OutC

transmission line attenuation greater than 20 db (V

> 50 mv) or

DIF

can be directly connected to fiber optic interface modules (any ECL

logic family, not limited to ECL 100K). The common mode tolerance

will accommodate a wide range of signal termination voltages. The

The serial interface PECL output buffers (ECL100K referenced

to +5V) are the drivers for the serial media. They are all con-

nected to the Shifter and contain the same serial data. Two of

the output pairs (OUTA± and OUTB±) are controllable by the

FOTO input and can be disabled by the system controller to force a

logical zero (i.e., “light off”) at the outputs. The third output pair

(OUTC±) is not affected by FOTO and will supply a continuous data

stream suitable for loop-back testing of the subsystem.

highest HIGH input that can be tolerated is V = V , and the low-

IN

CC

est LOW input that can be interpreted correctly is V = GND+2.0V.

IN

PECL-TTL Translator

The function of the INB(INB+) input and the SI(INB−) input is

defined by the connections on the SO output pin. If the

PECL/TTL translator function is not required, the SO output is

wired to VCC. A sensor circuit will detect this connection and

cause the inputs to become INB± (a differential line-receiver seri-

al-data input). If the PECL/TTL translator function is required, the

SOoutputisconnectedtoitsnormal TTLload(typicallyoneor more

TTL inputs, but nopull-upresistor) and the INB+input becomesINB

(single-ended ECL 100K, serial data input) and the INB− input be-

comes SI (single-ended, ECL 100K status input).

OUTA± and OUTB± will respond to FOTO input changes within a

few bit times. However, since FOTO is not synchronized with the

transmitter data stream, the outputs will be forced off or turned on

at arbitrary points in a transmitted byte. This function is intended to

augment anexternallasersafetycontroller andasanaidfor Receiv-

er PLL testing.

In wire-based systems, control of the outputs may not be re-

quired, and FOTO can be strapped LOW. The three outputs

are intended to add system and architectural flexibility by of-

fering identical serial bit streams with separate interfaces for

redundant connections or for multiple destinations. Unneeded

outputs can be wired to VCC to disable and power down the un-

used output circuitry.

This positive-referenced PECL-to-TTL translator is provided to

eliminate external logic between an PECL fiber-optic interface

module “carrier detect” output and the TTL input in the control

logic. The input threshold is compatible with ECL 100K levels

(+5V referenced). It can also be used as part of the link status

indication logic for wire connected systems.

Clock Generator

The clock generator is an embedded phase-locked loop (PLL)

that takes a byte-rate reference clock (CKW) and multiplies it

by ten (10) to create a bit rate clock for driving the serial shifter.

The byte rate reference comes from CKW, the rising edge of

which clocks data into the Input register. This clock must be a

crystal referenced pulse stream that has a frequency between

the minimum and maximum specified for the HOTLink Trans-

mitter/Receiver pair. Signals controlled by this block form the

bit clock and the timing signals that control internal data trans-

fers between the Input register and the Shifter.

Clock Synchronization

The Clock Synchronization function is performed by an em-

bedded phase-locked loop (PLL) that tracks the frequency of

the incoming bit stream and aligns the phase of its internal bit

rate clock to the serial data transitions. This block contains the

logic to transfer the data from the Shifter to the Decode register

once every byte. The counter that controls this transfer is ini-

tialized by the Framer logic. CKR is a buffered output derived

from the bit counter used to control the Decode register and

the output register transfers.

The read pulse (RP) is derived from the feedback counter used in

the PLL multiplier. It is a byte-rate pulse stream with the proper

phase and pulse widths to allow transfer of data from an asynchro-

nous FIFO. Pulse width is independent of CKW duty cycle, since

proper phase and duty cycle is maintained by the PLL. The RP

Clock output logic is designed so that when reframing causes

the counter sequence to be interrupted, the period and pulse

width of CKR will never be less than normal. Reframing may

stretch the period of CKR by up to 90%, and either CKR Pulse

Width HIGH or Pulse Width LOW may be stretched, depending

on when reframe occurs.

6

CY7B923

CY7B933

The REFCLK input provides a byte-rate reference frequency

to improve PLL acquisition time and limit unlocked frequency

excursions of the CKR when no data is present at the serial

inputs. The frequency of REFCLK is required to be within

±0.1% of the frequency of the clock that drives the transmitter

CKW pin.

Decoder

Parallel data is transformed from ANSI-specified X3.230

8B/10B codes back to “raw data” in the Decoder. This block

uses the standard decoder patterns shown in the Valid Data

Characters and Valid Special Character Codes and Sequenc-

es sections of this datasheet. Data patterns are signaled by a

LOW on the SC/D output and Special Character patterns are sig-

naled by a HIGH on the SC/D output. Unused patterns or disparity

errors are signaled as errors by a HIGH on the RVS output and by

specific Special Character codes.

Framer

Framer logic checks the incoming bit stream for the pattern

that defines the byte boundaries. This combinatorial logic filter

looks for the X3.230 symbol defined as a Special Character

Comma (K28.5). When it is found, the free-running bit counter

in the Clock Synchronization block is synchronously reset to

its initial state, thus framing the data correctly on the correct

byte boundaries.

Output Register

The Output register holds the recovered data (Q − , SC/D, and

0 7

RVS) and aligns it with the recovered byte clock (CKR). This syn-

chronization insures proper timing to match a FIFO interface or oth-

er logic that requires glitch free and specified output behavior. Out-

puts change synchronously with the rising edge of CKR.

Random errors that occur in the serial data can corrupt some

data patterns into a bit pattern identical to a K28.5, and thus

cause an erroneous data-framing error. The RF input prevents

this by inhibiting reframing during times when normal message

data is present. When RF is held LOW, the HOTLink receiver

will deserialize the incoming data without trying to reframe the

data to incoming patterns. When RF rises, RDYwill be inhibited

until a K28.5 has been detected, after which RDY will resume its

normal function. While RF is HIGH, it is possible that an error could

cause misframing, after which all data will be corrupted. Likewise,

a K28.7 followed by D11.x, D20.x, or an SVS (C0.7) followed by

D11.x will create alias K28.5 characters and cause erroneous fram-

ing. These sequences must be avoided while RF is HIGH.

In BIST mode, this register becomes the signature pattern

generator and checker by logically converting itself into a Lin-

ear Feedback Shift Register (LFSR) pattern generator. When

enabled, this LFSR will generate a 511-byte sequence that

includes all Data and Special Character codes, including the

explicit violation symbols. This pattern provides a predictable

but pseudo-random sequence that can be matched to an iden-

tical LFSR in the Transmitter. When synchronized, it checks

each byte in the Decoder with each byte generated by the

LFSR and shows errors at RVS. Patterns generated by the

LFSR are compared after being buffered to the output pins and

then fed back to the comparators, allowing test of the entire

receive function.

If RF remains HIGH for greater than 2048 bytes, the framer

converts to double-byte framing, requiring two K28.5 charac-

ters aligned on the same byte boundary within 5 bytes in order

to reframe. Double-byte framing greatly reduces the possibility

of erroneously reframing to an aliased K28.5 character.

In BIST mode, the LFSR is initialized by the first occurrence of

the transmitter BIST loop start code D0.0 (D0.0 is sent only

once per BIST loop). Once the BIST loop has been started,

RVS will be HIGH for pattern mismatches between the re-

ceived sequence and the internally generated sequence.

Code rule violations or running disparity errors that occur as

part of the BIST loop will not cause an error indication. RDY

will pulse HIGH once per BIST loop and can be used to check test

pattern progress. The receiver BIST generator can be reinitialized

by leaving and re-entering BIST mode.

Shifter

The Shifter accepts serial inputs from the Serial Data inputs

one bit at a time, as clocked by the Clock Synchronization log-

ic. Data is transferred to the Framer on each bit, and to the

Decode register once per byte.

Decode Register

Test Logic

The Decode register accepts data from the Shifter once per

byte as determined by the logic in the Clock Synchronization

block. It is presented to the Decoder and held until it is trans-

ferred to the output latch.

Test logic includes the initialization and control for the Built-In

Self-Test (BIST) generator, the multiplexer for Test mode clock

distribution, and control logic for the decoder. Test logic is dis-

cussed in more detail in the CY7B933 HOTLink Receiver Op-

erating Mode Description

7

CY7B923

CY7B933

[1]

CY7B923/CY7B933 Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

2.4

Max.

Unit

TTL OUTs, CY7B923: RP; CY7B933: Q , SC/D, RVS, RDY, CKR, SO

0−7

V

Output HIGH Voltage

I

= − 2 mA

V

OHT

OH

OL

V

Output LOW Voltage

= 4 mA

0.45

OLT

[2]

I

Output Short Circuit Current

V

=0V

−15

−90

mA

OST

OUT

TTL INs, CY7B923: D , SC/D, SVS, ENA, ENN, CKW, FOTO, BISTEN; CY7B933: RF, REFCLK, BISTEN

0−7

V

Input HIGH Voltage

Com’l, Ind’l, & Mil

2.0

2.2

V

IHT

CC

Ind’l & Mil (CKWandFOTO,only)

V

Input LOW Voltage

Input HIGH Current

Input LOW Current

−0.5

−10

0.8

+10

V

ILT

I

V

= V

CC

µA

IHT

IN

= 0.0V

− 500

ILT

Transmitter PECL-Compatible Output Pins: OUTA+, OUTA−, OUTB+, OUTB−, OUTC+, OUTC−

V

Output HIGH Voltage

Load =50Ωto Com’l

V − 2V

CC

V

−1.03

−1.05

−1.86

−1.96

V

−0.83

V

OHE

CC

(V referenced)

CC

Ind’l & Mil

Load =50Ωto Com’l

V − 2V

CC

−0.83

−1.62

V

Output LOW Voltage

OLE

(V referenced)

CC

Ind’l & Mil

Load = 50 ohms to V − 2V

V

Output Differential Voltage

0.6

ODIF

CC

|(OUT+) − (OUT−)|

Receiver PECL-Compatible Input Pins: A/B, SI, INB

V

Input HIGH Voltage

Com’l

V

−1.165

V

IHE

CC

Ind’l & Mil

Com’l

V

−1.14

CC

V

Input LOW Voltage

2.0

V

−1.475

V

ILE

CC

Ind’l & Mil

2.0

+0.5

50

V

−1.50

V

CC

[3]

IHE

[3]

ILE

I

Input HIGH Current

Input LOW Current

V

= V Max.

+500

µA

IN

IHE

= V Min.

ILE

Differential Line Receiver Input Pins: INA+, INA−, INB+, INB−

V

Input Differential Voltage

mV

DIFF

|(IN+) − (IN−)|

V

Highest Input HIGH Voltage

Lowest Input LOW Voltage

Input HIGH Current

V

IHH

ILL

CC

2.0

I

V

= V Max.

750

µA

IHH

[4]

ILL

IN

IHH

Input LOW Current

= V Min.

−200

Typ.

65

ILL

Miscellaneous

Max.

85

[5]

I

Transmitter Power Supply

Current

Freq. = Max.

Com’l

mA

CCT

Ind’l & Mil

Com’l

75

95

[6]

I

Receiver Power Supply

Current

120

135

155

160

CCR

Ind’l & Mil

Notes:

1. See the last page of this specification for Group A subgroup testing information.

2. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

3. Applies to A/B only.

4. Input currents are always positive at all voltages above V_CC/2.

5. Maximum I_CCTis measured with V_CC= Max., one PECL output pair loaded with 50 ohms to V_CC− 2.0V, and other PECL outputs tied to V_CC. Typical I_CCTis measured with

V_CC= 5.0V, T_A= 25°C, one output pair loaded with 50 ohms to V_CC− 2.0V, others tied to V_CC, BISTEN = LOW. I_CCTincludes current into V_CCQ(pin 9 and pin 22) only. Current

into V_CCNis determined by PECL load currents, typically 30 mA with 50 ohms to V_CC− 2.0V. Each additional enabled PECL pair adds 5 mA to I_CCTand an additional load

currenttoV_CCNasdescribed.WhencalculatingthecontributionofPECL loadcurrentstochippowerdissipation,theoutputload current shouldbemultipliedby1VinsteadofV_CC

6. Maximum I_CCRis measured with V_CC= Max., RF = LOW, and outputs unloaded. Typical I_CCRis measured with V_CC= 5.0V, T_A= 25°C, RF = LOW, BISTEN = LOW, and

outputs unloaded. I_CCRincludes current into V_CCQ(pins 21 and 24). Current into V_CCN(pin 9) is determined by the total TTL output buffer quiescent current plus the sum of all

the load currents for each output pin. The total buffer quiescent current is 10mA max., and max. TTL load current for each output pin can be calculated as follows: Where

.

I

0.95) (V

*

5)*0.3

V

I CCN

CCN

2

+

)

C

*

)

1.5 * F

* 1.1

L

TTLPin

R

L

R_L=equivalent load resistance, C_L=capacitive load, and F_pin=frequency in MHz of data on pin. A derating factor of 1.1 has been included to account for worst

process corner and temperature condition.

8

CY7B923

CY7B933

Capacitance^[7]

Parameter

Description

Input Capacitance

Test Conditions

T = 25°C, f = 1 MHz, V = 5.0V

Max.

Unit

C

10

pF

IN

A

0

CC

AC Test Loads and Waveforms

5V

R1

R2

OUTPUT

V

2

−

CC

R1=910

R2=510

C < 30 pF

L

R =50

Ω

L

Ω

C

L

R

L

C

C < 5 pF

L

(Includes fixture and

probe capacitance)

(Includes fixture and

probe capacitance)

[8]

(a) TTL AC Test Load

(b) PECL AC Test Load

B923–8

3.0V

V

IHE

V

3.0V

IHE

2.0V

80%

1.0V

20%

< 1 ns

20%

< 1 ns

GND

< 1 ns

ILE

V

ILE

< 1 ns

B923–10

B923–9

(c) TTL Input Test Waveform

(d) PECL Input Test Waveform

[1]

Transmitter Switching Characteristics Over the Operating Range

7B923-155

7B923

7B923-400

Parameter

Description

Min.

62.5

6.25

6.5

5

Max

66.7

6.67

Min.

30.3

Max

Min.

25

2.5

6.5

5

Max Unit

t

Write Clock Cycle

62.5

6.25

ns

ps

CKW

B

[9]

Bit Time

3.03 6.25

CKW Pulse Width HIGH

CKW Pulse Width LOW

6.5

5

CPWH

CPWL

SD

[10]

Data Set-Up Time

[10]

Data Hold Time

0

HD

[11]

Enable Set-Up Time (to insure correct RP)

6t + 8

SENP

HENP

PDR

PPWH

PDF

RISE

FALL

DJ

B

[11]

Enable Hold Time (to insure correct RP)

0

[12]

Read Pulse Rise Alignment

−4

2

−4

2

−4

2

[12]

Read Pulse HIGH

4t −3

B

[12]

Read Pulse Fall Alignment

6t −3

B

[7]

PECL Output Rise Time 20−80% (PECL Test Load)

1.2

35

1.2

35

1.2

35

[7]

PECL Output Fall Time 80−20% (PECL Test Load)

[7, 13]

Deterministic Jitter (peak-peak)

[7, 14]

Random Jitter (peak-peak)

175

20

175

20

175

20

RJ

[7,14]

Random Jitter (σ)

RJ

Notes:

7. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.

8. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.

9. Transmitter t_Bis calculated as t_CKW/10. The byte rate is one tenth of the bit rate.

10. Data includes D₀₋₇, SC/D, SVS, ENA, ENN, and BISTEN. t_SDand t_HDminimum timing assures correct data load on rising edge of CKW, but not RP function or timing.

11. t_SENPand t_HENPtiming insures correct RP function and correct data load on the rising edge of CKW.

12. Loading on RPis the standard TTL test load shown in part (a) of AC Test Loads and Waveforms except C_L= 15 pF.

13. While sending continuous K28.5s, RP unloaded, outputs loaded to 50Ω to V_CC−2.0V, over the operating range.

14. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to CKW input, over the operating

range.

9

CY7B923

CY7B933

[1]

Receiver Switching Characteristics Over the Operating Range

7B933-155

Min. Max

7B933

7B933-400

Parameter

Description

Min.

Max.

Min.

Max. Unit

t

Read Clock Period (No Serial Data Input), REFCLK

as Reference

−1

+1

−1

+1

−1

+1

%

CKR

[15]

[16]

t

Bit Time

6.25 6.67

5t −3

3.03

6.25

2.5

6.25

ns

B

Read Clock Pulse HIGH

Read Clock Pulse LOW

RDY Hold Time

5t −3

B

CPRH

CPRL

RH

B

5t −3

B

t −2.5

B

RDY Pulse Fall to CKR Rise

RDY Pulse Width HIGH

5t −3

B

PRF

PRH

A

B

4t −3

B

[17, 18]

Data Access Time

2t −2 2t + 2t −2

2t +4

2t −2

2t +4

B

4

[17, 18]

t

Data Hold Time

t −2.5

ns

%

ROH

B

[17, 18]

Data Hold Time from CKR Rise

2t −3

H

B

REFCLK Clock Period Referenced to CKW of

−0.1 +0.1

−0.1

+0.1

−0.1

+0.1

CKX

[19]

Transmitter

t

REFCLK Clock Pulse HIGH

6.5

20

6.5

ns

CPXH

CPXL

DS

REFCLK Clock Pulse LOW

Propagation Delay SI to SO (note PECL and TTL

20

[20]

thresholds)

[7, 21]

t

Static Alignment

100

ps

SA

[7, 22]

Error Free Window

0.9t

B

EFW

B

Notes:

15. The period of t_CKRwill match the period of the transmitter CKW when the receiver is receiving serial data. When data is interrupted, CKR may drift to one of the range limits

above.

16. Receiver t_Bis calculated as t_CKR/10 if no data is being received, or t_CKW/10 if data is being received. See note.

17. Data includes Q₀₋₇, SC/D, and RVS.

18. t_A, t_ROH, and t_Hspecifications are only valid if all outputs (CKR, RDY, Q₀₋₇, SC/D, and RVS) are loaded with similar DC and AC loads.

19. REFCLK has no phase or frequency relationship with CKR and only acts as a centering reference to reduce clock synchronization time. REFCLK must be

within 0.1% of the transmitter CKW frequency, necessitating a ±500-PPM crystal.

20. The PECL switching threshold is the midpoint between the PECL− V_OH, and V_OLspecification (approximately V_CC− 1.35V). The TTL switching threshold is 1.5V.

21. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in

3,000 nominal transitions until a byte error occurs.

22. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured

over the operating range, input jitter < 50% Dj.

10

CY7B923

CY7B933

Switching Waveforms for the CY7B923 HOTLink Transmitter

t

CKW

t

CPWH

t

CPWL

CKW

ENA

t

SENP

t

HENP

SD

NOTES 10,11

D –D ,

0

7

SC/D,

SVS,

VALID DATA

BISTEN

t

HD

SD

DISABLED

ENABLED

t

PDF

RP

t

PDR

B923–11

t

PPWH

t

CKW

t

CPWH

t

CPWL

CKW

ENN

t

HD

SD

D –D ,

0

7

SC/D,

SVS,

VALID DATA

BISTEN

B923–12

t

HD

SD

11

CY7B923

CY7B933

Switching Waveforms for the CY7B933 HOTLink Receiver

t

CKR

t

CPRH

t

CPRL

CKR

RDY

t

PRH

RH

t

PRF

t

A

t

ROH

t

H

Q

Q ,

7

−

0

SC/D,RVS,

B923–13

t

CKX

t

CPXL

t

CPXH

REFCLK

B923–14

SI

V

BB

t

DS

NOTE

20

1.5V

SO

B923–15

Static Alignment

Error-Free Window

t /2

B

t

SA

−

t /2

B

t

SA

−

t

EFW

INA

INB

±

INA

INB

,

±

t

B

BIT CENTER

B923–16

SAMPLE WINDOW

B923–17

12

CY7B923

CY7B933

DATA LATCHED IN

TRANSMITTER LATENCY = 21 t

10ns

−

B

CKW

ENA

D0 7,

−

SC/D,

SVS

DATA

RP

DATA

K28.5

DATA SENT

Figure 2. CY7B923 Transmitter Data Pipeline

K28.5

OUTX

±

B923–18

ceiver on the INx± inputs. The receiver PLL locks onto the

serial bit stream and generates an internal bit rate clock. The

bit stream is deserialized, decoded and then presented at the

parallel output pins. A byte rate clock (bit clock ÷ 10) synchro-

nous with the parallel data is presented at the CKR pin. The

RDY pin will be asserted to LOW to indicate that data or control

characters are present on the outputs. RDY will not be assert-

ed LOW in a field of K28.5s except for any single K28.5 or the

last one in a continuous series of K28.5’s. The latency through

HOTLink CY7B923 Transmitter and CY7B933

Receiver Operation

The CY7B923 Transmitter operating with the CY7B933 Re-

ceiver form a general purpose data communications sub-

system capable of transporting user data at up to 33Mbytes

per second (40 Mbytes per second for -400 devices) over sev-

eral types of serial interface media. Figure 2 illustrates the flow

of data through the HOTLink CY7B923 transmitter pipeline. Data is

latched into the transmitter on the rising edge of CKW when enabled

by ENA or ENN. RP is asserted LOW with a 60% LOW/40% HIGH

duty cycle when ENA is LOW. RP may be used as a read strobe for

accessing data stored in a FIFO. The parallel data flows through the

encoder and is then shifted out of the OUTx± PECL drivers. The

bit-rate clock is generated internally from a multiply-by-ten PLL clock

generator. The latency through the transmitter is approximately 21tB

− 10 ns over the operating range. A more complete description is

found in the section CY7B923 HOTLink Transmitter Operating Mode

Description.

the receiver is approximately 24t + 10 ns over the operating

B

range. A more complete description of the receiver is in the

section CY7B933 HOTLink Receiver Operating Mode De-

scription

The HOTLink Receiver has a built-in byte framer that synchro-

nizes the Receiver pipeline with incoming SYNC (K28.5) char-

acters. Figure 4 illustrates the HOTLink CY7B933 Receiver framing

operation. The Framer is enabled when the RF pin is asserted HIGH.

RF is latched into the receiver on the falling edge of CKR. The framer

looks for K28.5charactersembedded in the serial datastream. When

a K28.5 is found, the framer sets the parallel byte boundary for sub-

sequent data to the K28.5 boundary. While the framer is enabled, the

RDY pin indicates the status of the framing operation.

Figure 3 illustrates the data flow through the HOTLink

CY7B933 receiver pipeline. Serial data is sampled by the re-

SERIAL DATA IN

RECEIVER LATENCY= 24t + 10 ns

B

INX

DATA

±

CKR

Q0 7,

SC/D,

RVS

−

DATA

K28.5

DATA

RDY

RDY IS HIGH IN FIELD OF K28.5S

RDY IS LOW FOR LAST K28.5

RDY IS LOW FOR DATA

PARALLEL

DATA OUT

B923–19

Figure 3. CY7B933 Receiver Data Pipeline in Encoded Mode

13

CY7B923

CY7B933

CKR STRETCHES AS

DATA BOUNDARY CHANGES

RF LATCHED ON

FALLING EDGE OF CKR

CKR

RF

Q0 7,

−

SC/D,

RVS

DATA

K28.5

DATA

RDY IS HIGH WHILE WAITING FOR K28.5

RDY

RDY IS LOW

FOR K28.5

RDY RESUMES

NORMAL

OPERATION

B923–20

Figure 4. CY7B933 Framing Operation in Encoded Mode

When the RF pin is asserted HIGH, RDY leaves it normal mode

of operationand isassertedHIGH while the framer searches thedata

stream for a K28.5 character. After the framer has synchronized to a

K28.5 character, the Receiver will assert the RDY pin LOW when the

K28.5 character is present at the parallel output. The RDY pin will

then resume its normal operation as dictated by the MODE and BIS-

TEN pins.

receive eight (8) bit data and control information without first

converting it to transmission characters. The Bypass mode is

used for systems in which the encoding and decoding is per-

formed in an external protocol controller.

In either mode, data is loaded into the Input register of the

Transmitter on the rising edge of CKW. The input timing and

functional response of the Transmitter input can be made to

match the timing and functionality of either an asynchronous

FIFO or a clocked FIFO by an appropriate connection of input

signals (See Figure 5). Proper operation of the FIFO interface de-

pends upon various FIFO-specific access and response specifica-

tions.

The normal operation of the RDYpin in encoded mode is to signal

when parallel data is present at the output pins by pulsing LOW with

a 60% LOW/40% HIGH duty cycle. RDY does not pulse LOW in a

field of K28.5 characters; however, RDY does pulse LOW for the last

K28.5 character in the field or for any single K28.5. In unencoded

mode, the normal operation of the RDY pin is to signal when any

K28.5 is at the parallel output pins.

Encoded Mode Operation

In Encoded mode the input data is interpreted as eight bits of

The Transmitter and Receiver parallel interface timing and

functionality can be made to match the timing and functionality

of either an asynchronous FIFO or a clocked FIFO by appro-

priately connecting signals (See Figure 5). Proper operation of

the FIFO interface depends upon various FIFO-specific access and

response specifications.

data (D − D ), a context control bit (SC/D), and a system diagnostic

0

7

input bit (SVS). If the context of the data is to be normal message

data, the SC/D input should be LOW, and the data should be encod-

ed usingthe valid datacharacter set described in theValid Data Char-

acters section of this datasheet. If the context of the data is to be

control or protocol information, the SC/D input will be HIGH, and the

data will be encoded using the valid special character set described

in the Valid Special Character Codes and Sequences section. Spe-

cial characters include all protocol characters necessary to encode

packets for Fibre Channel, ESCON, proprietary systems, and diag-

nostic purposes.

The HOTLink Transmitter and Receiver serial interface pro-

vides a seamless interface to various types of media. A mini-

mal number of external components are needed to properly

terminate transmission lines and provide PECL loads. For

proper power supply decoupling, a single 0.01 µF for each de-

vice is all that is required to bypass the VCC and GND pins. Figure

6 illustrates a HOTLink Transmitter and Receiver interface to fiber op-

tic and copper media. More information on interfacing HOTLink to

various media can be found in the HOTLink Design Considerations

application note.

The diagnostic characters and sequences available as Special

Characters include those for Fibre Channel link testing, as well

as codes to be used for testing system response to link errors

and timing. A Violation symbol can be explicitly sent as part

of a user data packet (i.e., send C0.7; D

= 111 00000 and

7−0

SC/D = 1), or it can be sent in response to an external system using

the SVS input. This will allow system diagnostic logic to evaluate the

errors in an unambiguous manner, and will not require any modifica-

tion to the transmission interface to force transmission errors for test-

ing purposes.

CY7B923 HOTLink Transmitter Operating Mode

Description

In normal operation, the Transmitter can operate in either of

two modes. The Encoded mode allows a user to send and

14

CY7B923

CY7B933

ASYNCHRONOUS FIFO

7C42X/3X/6X/7X

CLOCKED FIFO

7C44X/5X

R

Q

ENR

ENN

CKR

Q

0 − 8

9

ENA

CKW

RP

D

,SC/D

CKW

D

,SC/D

0 − 7

7B923

HOTLINK TRANSMITTER

HOTLINK RECEIVER

7B933

HOTLINK RECEIVER

7B933

CKR

RDY

Q

,SC/D

9

CKR

RDY

Q

,SC/D

9

0 − 7

W

7C42X/3X/6X/7X

D

0 − 8

CKW

ENW

D

0 − 8

7C44X/5X

B923–21

ASYNCHRONOUS FIFO

CLOCKED FIFO

Figure 5. Seamless FIFO Interface

Bypass Mode Operation

to maintain proper link synchronization (in Bypass mode the proper

senseof running disparity cannot be guaranteedfor the first pad char-

acter, but is correct for all pad characters that follow). This automatic

insertion of pad characters can be inhibited byinsuring that the Trans-

mitter is always enabled (i.e., ENA or ENN is hard-wired LOW).

In Bypass mode the input data is interpreted as ten (10) bits

(D ), SC/D (Da), and SVS (Dj) of pre-encoded transmission data to

b-h

be serialized and sent over the link. This data can use any encoding

method suitable to the designer. The only restrictions upon the data

encoding method is that it contain suitable transition density for the

Receiver PLL data synchronizer (one per 10 bit byte), and that it be

compatible with the transmission media.

PECL Output Functional and Connection Options

The three pairs of PECL outputs all contain the same informa-

tion and are intended for use in systems with multiple connec-

tions. Each output pair may be connected to a different serial

media, each of which may be a different length, link type, or

interface technology. For systems that do not require all three

Data loaded into the Input register on the rising edge of CKW

will be loaded into the Shifter on the subsequent rising edges

of CKW. It will then be shifted to the outputs one bit at a time

using the internal clock generated by the clock generator. The

first bit of the transmission character (Da)will appear at theoutput

(OUTA±, OUTB±, and OUTC±) after the next CKW edge.

output pairs, the unused pairs should be wired to V

to mini-

CC

mize the power dissipated by the output circuit, and to minimize un-

wanted noise generation. An internal voltage comparator detects

While in either the Encoded mode or Bypass mode, if a CKW

edge arrives when the inputs are not enabled (ENA and ENN

both HIGH), the Encoder will insert a pad character K28.5 (e.g., C5.0)

when an output differential pair is wired to V , causing the current

source for that pair to be disabled. This results in a power savings of

around 5 mA for each unused pair.

CC

15

CY7B923

CY7B933

In systems that require the outputs to be shut off during some

periods when link transmission is prohibited (e.g., for laser

safety functions), the FOTO input can be asserted. While it is

possible to insure that the output state of the PECL drivers is

LOW (i.e., light is off) by sending all 0’s in Bypass mode, it is

often inconvenient to insert this level of control into the data

transmission channel, and it is impossible in Encoded mode.

FOTO is provided to simplify and augment this control function

(typically found in laser-based transmission systems). FOTO

will force OUTA+ and OUTB+ to go LOW, OUTA− and OUTB−

to go HIGH, while allowing OUTC±to continue to function normal-

ly (OUTC is typically used as a diagnostic feedback and cannot be

disabled). This separation of function allows various system configu-

rations without undue load on the control function or data channel

logic.

rial data output is controlled by an internal Phase-Locked Loop

that multiplies the frequency of CKW by ten (10) to maintain

the proper bit clock frequency. The jitter characteristics (in-

cluding both PLL and logic components) are shown below:

Deterministic Jitter (D) < 35 ps (peak-peak). Typically mea-

j

sured while sending a continuous K28.5 (C5.0).

Random Jitter (R ) < 175 ps (peak-peak). Typically measured

j

while sending a continuous K28.7 (C7.0).

Transmitter Test Mode Description

The CY7B923 Transmitter offers two types of test mode oper-

ation, BIST mode and Test mode. In a normal system applica-

tion, the Built-In Self-Test (BIST) mode can be used to check

the functionality of the Transmitter, the Receiver, and the link

connecting them. This mode is available with minimal impact

on user system logic, and can be used as part of the normal

system diagnostics. Typical connections and timing are shown

in Figure 7.

Transmitter Serial Data Characteristics

The CY7B923 HOTLink Transmitter serial output conforms to

the requirements of the Fibre Channel specification. The se-

.01UF

4 9 22

7

VCC

Tx PECL Load

.01UF

Config

MODE

VCC

82

130

25

5

24

23

8

Fiber Optic

Tx

FOTO

BISTEN

ENN

Fiber

TX

A

B

27

26

Control

&

Status

OUTA+

OUTA–

TX+

TX–

ENA

RP

82

130

CY7B923

Transmitter

GND

Unused Output Left

Open to Minimize

Power Dissipation

28

1

.01UF

19

18

17

16

15

14

13

12

11

10

21

OUTB+

OUTB–

SC/D (Da)

D0 (Db)

D1 (Dc)

D2 (Dd)

D3 (De)

D4 (Di)

D5 (Df)

D6 (Dg)

D7 (Dh)

SVS(Dj)

CKW

Tx PECL Load

3

2

Coax or

Twisted Pair

OUTC+

OUTC–

270

A

B

Data

270

.01UF

GND

6 20

649

1500

Transmission

Line

Termination

RL/2

Coax or

Twisted Pair

.01UF

C

9 2124

VCC

26

25

MODE

REFCLK

D

E

Config

Optional

Signal Det.

4

23

3

5

BISTEN

SO

A/B

RF

RDY

Control

&

Status

CY7B933

Receiver

28

27

7

IB+

IB–

E

19

18

17

16

15

14

13

12

11

10

22

270

130

SC/D (Qa)

D0 (Qb)

D1 (Qc)

D2 (Qd)

D3 (Qe)

D4 (Qi)

.01UF

VCC

Fiber

82

Fiber Optic

Rx

SIG

RX+

RX–

2

1

C

D

RX

IA+

IA–

Data

82

130

D5 (Qf)

GND

D6 (Qg)

D7 (Qh)

RVS(Qj)

.01UF

CKR

GND

Fiber Optic

PECL Load

6 8 20

B923–22

Figure 6. HOTLink Connection Diagram

16

CY7B923

CY7B933

CY7B923

DON'T CARE

FOTO

MODE

BIST

LOOP

WITHIN SPEC.

CKW

RP

DON'T CARE

SC/D

OUTA

OUTB

OUTC

D

0 − 7

8

LOW

SVS

ENA

ENN

HIGH

Tx

START

Tx

STOP

BISTEN

CY7B933

WITHIN SPEC.

DON'T CARE

LOW

REFCLK

MODE

RF

SO

CKR

DON'T CARE

SC/D

INA

Q

0 − 7

8

ERROR

INB

A/B

RVS

LOW

BIST

LOOP

TEST

START

RDY

BISTEN

TEST

END

Rx

BEGIN

TEST

B923–23

Figure 7. Built In Self-Test Illustration

BIST Mode

3. Allow the Transmitter to run through several BIST loops or

until the Receiver test is complete. RP will pulse LOW once

per BIST loop, and can be used by an external counter to

monitor the number of test pattern loops.

BIST mode functions as follows:

1. Set BISTEN LOW to begin test pattern generation. Trans-

mitter begins sending bit rate ...1010...

4. When testing is completed, set BISTENHIGH and ENA and

ENN HIGH and resume normal function.

2. Set either ENA or ENN LOW to begin pattern sequence

generation (use of the Enable pin not being used for normal

FIFO or system interface can minimize logic delays be-

tween the controller and transmitter).

Note: It may be advisable to send violation characters to test

the RVS output in the Receiver. This can be done by explicitly

sending a violation with the SVS input, or allowing the trans-

17

CY7B923

CY7B933

mitter BIST loop to run while the Receiver runs in normal

mode. The BIST loop includes deliberate violation symbols

and will adequately test the RVS function.

CY7B933 HOTLink Receiver Operating Mode

Description

In normal user operation, the Receiver can operate in either of

two modes. The Encoded mode allows a user system to send

and receive 8-bit data and control information without first con-

verting it to transmission characters. The Bypass mode is

used for systems in which the encoding and decoding is per-

formed by an external protocol controller.

BIST mode is intended to check the entire function of the

Transmitter (except the Transmitter input pins and the bypass

function in the Encoder), the serial link, and the Receiver. It

augments normal factory ATE testing and provides the design-

er with a rigorous test mechanism to check the link transmis-

sion system without requiring any significant system overhead.

In either mode, serial data is received at one of the differential

line receiver inputs and routed to the Shifter and the Clock

Synchronization. The PLL in the Clock Synchronizer aligns

the internally generated bit rate clock with the incoming data

stream and clocks the data into the shifter. At the end of a byte

time (ten bit times), the data accumulated in the shifter is trans-

ferred to the Decode register.

While in Bypass mode, the BIST logic will function in the same

way as in the Encoded mode. MODE = HIGH and BISTEN =

LOW causes the Transmitter to switch to Encoded mode and begin

sending the BIST pattern, as if MODE = LOW. When BISTEN re-

turns to HIGH, the Transmitter resumes normal Bypass operation. In

Test mode the BIST function works as in the Normal mode. For more

information on BIST, consult the “HOTLink Built-In Self-Test” Applica-

tion Note.

To properly align the incoming bit stream to the intended byte

boundaries, the bit counter in the Clock Synchronizer must be

initialized. The Framer logic block checks the incoming bit

stream for the unique pattern that defines the byte boundaries.

This combinatorial logic filter looks for the X3.230 symbol de-

fined as “Special Character Comma” (K28.5). Once K28.5 is

found, the free running bit counter in the Clock Synchronizer

block is synchronously reset to its initial state, thus “framing”

the data to the correct byte boundaries.

Test Mode

The MODE input pin selects between three transmitter func-

tional modes. When wired to VCC, the D( ) inputs bypass the

a−j

Encoder and load directly from the Input register into the Shifter.

When wired to GND, the inputs D , SVS, and SC/D are encoded

0−7

using the Fibre Channel 8B/10B codes and sequences (shown at the

end of this datasheet). Since the Transmitter is usually hard wired to

Encoded or Bypass mode and not switched between them, a third

function is provided for the MODE pin. Test mode is selected by float-

ing the MODE pin (internal resistors hold the MODE pin at VCC/2).

Test mode is used for factory or incoming device test.

Since noise-induced errors can cause the incoming data to be

corrupted, and since many combinations of error and legal

data can create an alias K28.5, an option is included to disable

resynchronization of the bit counter. The Framer will be inhib-

ited when the RF input is held LOW. When RF rises, RDY will

be inhibited until a K28.5 has been detected, and RDY will

resume its normal function. Data will continue to flow through

the Receiver while RDY is inhibited.

Test mode causes the Transmitter to function in its Encoded

mode, but with OutA+/OutB+ (used as a differential test clock

input) as the bit rate clock input instead of the internal

PLL-generated bit clock. In this mode, inputs are clocked by

CKW and transfers between the Input register and Shifter are

timed by the internal counters. The bit-clock and CKW must

maintain a fixed phase and divide-by-ten ratio. The phase and

pulse width of RP are controlled by phases of the bit counter (PLL

feedback counter) as in Normal mode. Input and output patterns can

be synchronized withinternal logicbyobservingthe state of RP or the

device can be initialized to match an ATE test pattern using the follow-

ing technique:

Encoded Mode Operation

In Encoded mode the serial input data is decoded into eight

bits of data (Q − Q ), a context control bit (SC/D), and a system

0

7

diagnostic output bit (RVS). If the pattern in the Decode register is

found in the Valid Data Characters table, the context of the data is

decoded as normal message data and the SC/D output will be

LOW. If the incoming bit pattern is found in the Valid Special Char-

acter Codes and Sequences table, it is interpreted as “control” or

“protocol information,” and the SC/D output will be HIGH. Special

characters include all protocol characters defined for use in packets

for Fibre Channel, ESCON, and other proprietary and diagnostic

purposes.

1. With the MODE pin either HIGH or LOW, stop CKW and

bit-clock.

2. Force the MODE pin to MID (open or V /2) while the

CC

clocks are stopped.

3. Start the bit-clock and let it run for at least 2 cycles.

4. Start the CKW clock at the bit-clock/10 rate.

The Violation symbol that can be explicitly sent as part of a

user data packet (i.e., Transmitter sending C0.7; D

= 111

7−0

00000 and SC/D = 1; or SVS = 1) will be decoded and indicated in

exactly the same way as a noise-induced error in the transmission

link. This function will allow system diagnostics to evaluate the error

in an unambiguous manner, and will not require any modification to

the receiver data interface for error-testing purposes.

Test mode is intended to allow logical, DC, and AC testing of

the Transmitter without requiring that the tester check output

data patterns at the bit rate, or accommodate the PLL lock,

tracking, and frequency range characteristics that are required

when the HOTLink part operates in its normal mode. To use

OutA+/OutB+ as the test clock input, the FOTO input is held

HIGH while in Test mode. This forces the two outputs to go to

an “PECL LOW,” which can be ignored while the test system

creates a differential input signal at some higher voltage.

Bypass Mode Operation

In Bypass mode the serial input data is not decoded, and is

transferred directly from the Decode register to the Output reg-

ister’s 10 bits (Q( ). It is assumed that the data has been pre-en-

a−j

coded prior to transmission, and will be decoded in subsequent log-

ic external to HOTLink. This data can use any encoding method

suitable to the designer. The only restrictions upon the data encod-

ing method is that it contain suitable transition density for the Receiv-

18

CY7B923

CY7B933

er PLL data synchronizer (one per 10 bit byte) and that it be com-

patible with the transmission media.

RVS SC/D Qouts Name

1. Good Data code received

with good Running Disparity

(RD)0000−FFD0.0−31.7

The framer function in Bypass mode is identical to Encoded

mode, so a K28.5 pattern can still be used to re-frame the

serial bit stream.

2. Good Special Character

code received with good RD

0

1

00−0B C0.0−11.0

Parallel Output Function

3. K28.7 immediately following

The 10 outputs (Q , SC/D, andRVS) all transition simultaneous-

0−7

K28.1 (ESCON Connect_SOF)0

27

C7.1

ly, and are aligned with RDY and CKR with timing allowances to

interface directly with either an asynchronous FIFO or a clocked

FIFO. Typical FIFO connections are shown in Figure 5.

4. K28.7 immediately following

K28.5 (ESCON Passive_SOF)0

1

47

C7.2

C0.7

Data outputs can be clocked into the system using either the

rising or falling edge of CKR, or the rising or falling edge of

RDY. If CKR is used, RDY can be used as an enable for the receiv-

ing logic. A LOW pulse on RDY shows that new data has been

received and is ready to be delivered. The signal on RDY is a

60%−LOW duty cycle byte-rate pulse train suitable for the write

pulse in asynchronous FIFOs such as the CY7C42X, or the enable

writeinput onClockedFIFOssuchastheCY7C44X. HIGHon RDY

shows that the received data appearing at the outputs is the null

character (normally inserted by the transmitter as a pad between

data inputs) and should be ignored.

5. Unassigned code received

1

E0

6. −K28.5+ received when

RD was +

1

E1

E2

E4

C1.7

C2.7

C4.7

7. +K28.5− received when

RD was −

8. Good code received

with wrong RD

Receiver Serial Data Requirements

The CY7B933 HOTLink Receiver serial input capability con-

forms to the requirements of the Fibre Channel specification.

The serial data input is tracked by an internal Phase-Locked

Loop that is used to recover the clock phase and to extract the

data from the serial bit stream. Jitter tolerance characteristics

(including both PLL and logic component requirements) are

shown below:

When the Transmitter is disabled it will continuously send pad

characters (K28.5). To assure that the receive FIFO will not

be overfilled with these dummy bytes, the RDY pulse output is

inhibited during fill strings. Data at the Q

outputs will reflect the

0−7

correct received data, but will not appear to change, since a string

of K28.5s all are decoded as Q7−0 =000 00101 and SC/D = 1

(C5.0). When new data appears (not K28.5), the RDY output will

resume normal function. The “last” K28.5 will be accompanied by

a normal RDY pulse.

• Deterministic Jitter tolerance (D) >40% of t . Typically mea-

j

B

sured while receiving data carried by a bandwidth-limited chan-

nel(e.g., acoaxialtransmission line)whilemaintainingaBitError

−12

Fill characters are defined as any K28.5 followed by another

K28.5. All fill characters will not cause RDYto pulse. Any K28.5

followed by any other character (including violation or illegal charac-

ters) will be interpreted as usable data and will cause RDY to pulse.

Rate (BER) <10

.

• Random Jitter tolerance (R) > 90% of t . Typically measured

j

B

while receiving data carried by a random-noise-limited channel

(e.g., a fiber-optic transmission system withlow lightlevels)while

−12

maintaining a Bit Error Rate (BER) <10

.

As noted above, RDY can also be used as an indication of correct

framing of received data. While the Receiver is awaiting receipt of

a K28.5 with RF HIGH, the RDY outputs will be inhibited. When

RDY resumes, the received data will be properly framed and will be

decoded correctly. In Bypass mode with RF HIGH, RDY will pulse

once for each K28.5 received. For more information on the RDY

pin, consult the “HOTLink CY7B933 RDY Pin Description” applica-

tion note.

• Total Jitter tolerance >90% of t . Total of D + R.

B

j

• PLL-Acquisition time <500-bit times from worst-case phase

or frequency change in the serial input data stream, to re-

−12

ceiving data within BER objective of 10 . Stable power

supplies within specifications, stable REFCLK input frequency

and normal data framing protocols are assumed. Note: Acqui-

sition time is measured from worst-case phase or frequency

change to zero phase and frequency error. As a result of the

receiver’s widejittertolerance, validdatawillappearatthe receiv-

er’s outputs a few byte times after a worst-case phase change.

Code rule violations and reception errors will be indicated as

follows:

19

CY7B923

CY7B933

logic and test pattern inputs can be synchronized by sending

a SYNC pattern and allowing the Framer to align the logic to

the bit stream. The flow is as follows:

Receiver Test Mode Description

The CY7B933 Receiver offers two types of test mode opera-

tion, BIST mode and Test mode. In a normal system applica-

tion, the Built-In Self-Test (BIST) mode can be used to check

the functionality of the Transmitter, the Receiver and the link

connecting them. This mode is available with minimal impact

on user system logic, and can be used as part of the normal

system diagnostics. Typical connections and timing are shown

in Figure 7.

1. Assert Test mode for several test clock cycles to establish

normal counter sequence.

2. Assert RF to enable reframing.

3. Input a repeating sequence of bits representing K28.5

(Sync).

4. RDY falling shows the byte boundary established by the

K28.5 input pattern.

BIST Mode

5. Proceed with pattern, voltage and timing tests as is conve-

nient for the test program and tester to be used.

BIST Mode function is as follows:

1. Set BISTEN LOW to enable self-test generation and await

RDY LOW indicating that the initialization code has been

received.

(While in Test mode and in BIST mode with RF HIGH, the Q

,

0-7

RVS, and SC/D outputs reflect various internal logic states and not

the received data.)

2. Monitor RVS and check for any byte time with the pin HIGH

to detect pattern mismatches. RDY will pulse HIGH once

per BIST loop, and can be used by an external counter to

monitor test pattern progress. Q

expected pattern and may be useful for debug purposes.

Test mode is intended to allow logical, DC, and AC testing of

the Receiver without requiring that the tester generate input

data at the bit rate or accommodate the PLL lock, tracking and

frequency range characteristics that are required when the

part operates in its normal mode.

and SC/D will show the

0−7

3. When testing is completed, set BISTEN HIGH and resume

normal function.

X3.230 Codes and Notation Conventions

Note: A specific test of the RVS output may be required to

assure an adequate test. To perform this test, it is only neces-

sary to have the Transmitter send violation (SVS = HIGH) for

a few bytes before beginning the BIST test sequence. Alter-

natively, the Receiver could enter BIST mode after the Trans-

mitter has begun sending BIST loop data, or be removed be-

fore the Transmitter finishes sending BIST loops, each of

which contain several deliberate violations and should cause

RVS to pulse HIGH.

Information to be transmitted over a serial link is encoded eight

bits at a time into a 10-bit Transmission Character and then

sent serially, bit by bit. Information received over a serial link

is collected ten bits at a time, and those Transmission Charac-

ters that are used for data (Data Characters) are decoded into

the correct eight-bit codes. The 10-bit Transmission Code sup-

ports all 256 8-bit combinations. Some of the remaining Trans-

mission Characters (Special Characters) are used for func-

tions other than data transmission.

BIST mode is intended to check the entire function of the

Transmitter, serial link, and Receiver. It augments normal fac-

tory ATE testing and provides the user system with a rigorous

test mechanism to check the link transmission system, without

requiring any significant system overhead.

The primary rationale for use of a Transmission Code is to

improve the transmission characteristics of a serial link. The

encoding defined by the Transmission Code ensures that suf-

ficient transitions are present in the serial bit stream to make

clock recovery possible at the Receiver. Such encoding also

greatly increases the likelihood of detecting any single or mul-

tiple bit errors that may occur during transmission and recep-

tion of information. In addition, some Special Characters of

the Transmission Code selected by Fibre Channel Standard

consist of a distinct and easily recognizable bit pattern (the

Special Character Comma) that assists a Receiver in achiev-

ing word alignment on the incoming bit stream.

When in Bypass mode, the BIST logic will function in the same

way as in the Encoded mode. MODE = HIGH and BISTEN =

LOW causes the Receiver to switch to Encoded mode and begin

checking the decoded received data of the BIST pattern, as if

MODE = LOW. When BISTEN returns to HIGH, the Receiver re-

sumes normal Bypass operation. In Test mode the BIST function

works as in the normal mode.

Test Mode

Notation Conventions

The MODE input pin selects between three receiver functional

modes. When wired to VCC, the Shifter contents bypass the

The documentation for the 8B/10B Transmission Code uses

letter notation for the bits in an 8-bit byte. Fibre Channel Stan-

dard notation uses a bit notation of A, B, C, D, E, F, G, H for

the 8-bit byte for the raw 8-bit data, and the letters a, b, c, d, e,

i, f, g, h, j for encoded 10-bit data. There is a correspondence

between bit A and bit a, B and b, C and c, D and d, E and e, F

and f, G and g, and H and h. Bits i and j are derived, respec-

tively, from (A,B,C,D,E) and (F,G,H).

Decoder and go directly from the Decoder latch to the Q inputs

a−j

of the Output latch. When wired to GND, the outputs are decoded

using the 8B/10B codes shown at the end of this datasheet and

become Q , RVS, and SC/D. The third function is Test mode,

0−7

used for factoryor incomingdevicetest. This modecanbeselected

byleaving the MODE pinopen (internal circuitry forcesthe open pin

to VCC/2).

The bit labeled A in the description of the 8B/10B Transmission

Code corresponds to bit 0 in the numbering scheme of the

FC-2 specification, B corresponds to bit 1, as shown below.

Test mode causes the Receiver to function in its Encoded

mode, but with INB (INB+) as the bit rate Test clock instead of

the Internal PLL generated bit clock. In this mode, transfers

between the Shifter, Decoder register and Output register are

controlled by their normal logic, but with an external bit rate

clock instead of the PLL (the recovered bit clock). Internal

FC-2 bit designation—

HOTLink D/Q designation— 7

8B/10B bit designation—

7

6

5

4

E

3

D

2

C

1

B

0

A

H

G F

20

CY7B923

CY7B933

To clarify this correspondence, the following example shows

the conversion from an FC-2 Valid Data Byte to a Transmission

Character (using 8B/10B Transmission Code notation)

Transmission Order

Within the definition of the 8B/10B Transmission Code, the bit

positions of the Transmission Characters are labeled a, b, c, d,

e, i, f, g, h, j. Bit “a” shall be transmitted first followed by bits b,

c, d, e, i, f, g, h, and j in that order. (Note that bit i shall be

transmitted between bit e and bit f, rather than in alphabetical

order.)

FC-2 45

Bits: 7654 3210

0100 0101

Converted to 8B/10B notation (note carefully that the order of

bits is reversed):

Valid and Invalid Transmission Characters

Data Byte Name

D5.2

The following tables define the valid Data Characters and valid

Special Characters (K characters), respectively. The tables

are used for both generating valid Transmission Characters

(encoding) and checking the validity of received Transmission

Characters (decoding). In the tables, each Valid-Data-byte or

Special-Character-code entry has two columns that represent

two (not necessarily different) Transmission Characters. The

two columns correspond to the current value of the running

disparity (“Current RD−” or “Current RD+”). Running disparity

is a binary parameter with either the value negative (−) or the

value positive (+).

Bits:ABCDEFGH

10100 010

Translated to a transmission Character in the 8B/10B Trans-

mission Code:

Bits: abcdeifghj

1010010101

Each valid Transmission Character of the 8B/10B Transmis-

sion Code has been given a name using the following conven-

tion: cxx.y, where c is used to show whether the Transmission

Character is a Data Character (c is set to D, and the SC/D pin

is LOW) or a Special Character (c is set to K, and the SC/D pin is

HIGH). When c is set to D, xx is the decimal value of the binary

number composedof the bitsE, D, C, B, and A in that order, and the

y is the decimal value of the binary number composed of the bits H,

G, and F in that order. When c is set to K, xx and y are derived by

comparing the encoded bit patterns of the Special Character to

those patterns derived from encoded Valid Data bytes and selecting

the names of the patterns most similar to the encoded bit patterns

of the Special Character.

After powering on, the Transmitter may assume either a posi-

tive or negative value for its initial running disparity. Upon

transmission of any Transmission Character, the transmitter

will select the proper version of the Transmission Character

based on the current running disparity value, and the Trans-

mitter shall calculate a new value for its running disparity

based on the contents of the transmitted character. Special

Character codes C1.7 and C2.7 can be used to force the trans-

mission of a specific Special Character with a specific running

disparity as required for some special sequences in X3.230.

Under the above conventions, the Transmission Character

used for the examples above, is referred to by the name D5.2.

The Special Character K29.7 is so named because the first six

bits (abcdei) of this character make up a bit pattern similar to

that resulting from the encoding of the unencoded 11101 pat-

tern (29), and because the second four bits (fghj) make up a

bit pattern similar to that resulting from the encoding of the

unencoded 111 pattern (7).

After powering on, the Receiver may assume either a positive

or negative value for its initial running disparity. Upon recep-

tion of any Transmission Character, the Receiver shall decide

whether the Transmission Character is valid or invalid accord-

ing to the following rules and tables and shall calculate a new

value for its Running Disparity based on the contents of the

received character.

The following rules for running disparity shall be used to cal-

culate the new running-disparity value for Transmission Char-

acters that have been transmitted (Transmitter’s running dis-

parity) and that have been received (Receiver’s running

disparity).

Note: This definition of the 10-bit Transmission Code is based

on (and is in basic agreement with) the following references,

which describe the same 10-bit transmission code.

A.X. Widmer and P.A. Franaszek. “A DC-Balanced, Parti-

tioned-Block, 8B/10B Transmission Code” IBM Journal of Re-

search and Development, 27, No. 5: 440−451 (September, 1983).

Running disparity for a Transmission Character shall be calcu-

lated from sub-blocks, where the first six bits (abcdei) form one

sub-block and the second four bits (fghj) form the other

sub-block. Running disparity at the beginning of the 6-bit

sub-block is the running disparity at the end of the previous

Transmission Character. Running disparity at the beginning of

the 4-bit sub-block is the running disparity at the end of the

6-bit sub-block. Running disparity at the end of the Transmis-

sion Character is the running disparity at the end of the 4-bit

sub-block.

U.S. Patent 4, 486, 739. Peter A. Franaszek and Albert X. Wid-

mer. “Byte-Oriented DC Balanced (0.4) 8B/10B Partitioned

Block Transmission Code” (December 4, 1984).

Fibre Channel Physical and Signaling Interface (dpANS

X3.230−199X ANSI FC−PH Standard).

IBM Enterprise Systems Architecture/390 ESCON I/O Inter-

face (document number SA22−7202).

8B/10B Transmission Code

Running disparity for the sub-blocks shall be calculated as fol-

lows:

The following information describes how the tables shall be

used for both generating valid Transmission Characters (en-

coding) and checking the validity of received Transmission

Characters (decoding). It also specifies the ordering rules to

be followed when transmitting the bits within a character and

the characters within the higher-level constructs specified by

the standard.

1. Running disparity at the end of any sub-block is positive if

the sub-block contains more ones than zeros. It is also

positiveat the end of the 6-bitsub-block if the 6-bit sub-block

is 000111, and it is positive at the end of the 4-bit sub-block

if the 4-bit sub-block is 0011.

2. Running disparity at the end of any sub-block is negative if

the sub-block contains more zeros than ones. It is also

21

CY7B923

CY7B933

negative at the end of the 6-bit sub-block if the 6-bit

sub-block is 111000, and it is negative at the end of the 4-bit

sub-block if the 4-bit sub-block is 1100.

ceiver’s current running disparity for the next received Trans-

mission Character.

Table 1. Valid Transmission Characters

Data

3. Otherwise, running disparity at the end of the sub-block is

the same as at the beginning of the sub-block.

D

or Q

OUT

IN

Use of the Tables for Generating Transmission Characters

Byte Name

765

43210

Hex Value

The appropriate entry in the table shall be found for the Valid

Data byte or the Special Character byte for which a Transmis-

sion Character is to be generated (encoded). The current val-

ue of the Transmitter’s running disparity shall be used to select

the Transmission Character from its corresponding column.

For each Transmission Character transmitted, a new value of

the running disparity shall be calculated. This new value shall

be used as the Transmitter’s current running disparity for the

next Valid Data byte or Special Character byte to be encoded

and transmitted. Table 1 shows naming notations and examples

of valid transmission characters.

D0.0

000

00000

00

D1.0

D2.0

000

00001

00010

01

02

.

D5.2

010

00010

1

45

Use of the Tables for Checking the Validity of Received

Transmission Characters

.

The column corresponding to the current value of the Receiv-

er’s running disparity shall be searched for the received Trans-

mission Character. If the received Transmission Character is

found in the proper column, then the Transmission Character

is valid and the associated Data byte or Special Character

code is determined (decoded). If the received Transmission

Character is not found in that column, then the Transmission

Character is invalid. This is called a code violation. Indepen-

dent of the Transmission Character’s validity, the received

Transmission Character shall be used to calculate a new value

of running disparity. The new value shall be used as the Re-

D30.7

D31.7

111

11110

11111

FE

FF

Detection of a code violation does not necessarily show that

the Transmission Character in which the code violation was

detected is in error. Code violations may result from a prior

error that altered the running disparity of the bit stream which

did not result in a detectable error at the Transmission Char-

acter in which the error occurred. Table 2 shows an example of

this behavior.

Table 2. Code Violations Resulting from Prior Errors

RD

−

Character

D21.1

RD

−

Character

D10.2

RD

−

Character

D23.5

RD

+

Transmitted data character

Transmitted bit stream

Bit stream after error

−

101010 1001

101010 1011

D21.0

−

010101 0101

D10.2

−

111010 1010

Code Violation

+

−

+

Decoded data character

−

+

22

CY7B923

CY7B933

Valid Data Characters (SC/D = LOW)

Data

Byte

Name

Bits

Current RD−

Current RD+

HGF EDCBA

abcdei

fghj

abcdei

fghj

D0.0

D1.0

000

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

100111

0100

1011

0100

1011

0100

1011

0100

1011

0100

1011

0100

1011

0100

011000

100010

010010

110001

001010

101001

011001

000111

000110

100101

010101

110100

001101

101100

011100

101000

100100

100011

010011

110010

001011

101010

011010

000101

001100

100110

010110

001001

001110

010001

100001

010100

1011

011101

101101

110001

110101

101001

011001

111000

111001

100101

010101

110100

001101

101100

011100

010111

011011

100011

010011

110010

001011

101010

011010

111010

110011

100110

010110

110110

001110

101110

011110

101011

1011

0100

1011

0100

1011

0100

1011

0100

1011

0100

1011

0100

1011

D2.0

D3.0

D4.0

D5.0

D6.0

D7.0

D8.0

D9.0

D10.0

D11.0

D12.0

D13.0

D14.0

D15.0

D16.0

D17.0

D18.0

D19.0

D20.0

D21.0

D22.0

D23.0

D24.0

D25.0

D26.0

D27.0

D28.0

D29.0

D30.0

D31.0

23

CY7B923

CY7B933

Valid Data Characters (SC/D = LOW) (continued)

Data

Byte

Name

Bits

Current RD−

Current RD+

HGF EDCBA

abcdei

fghj

abcdei

fghj

D0.1

D1.1

001

010

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

00000

00001

100111

1001

0101

011000

100010

010010

110001

001010

101001

011001

000111

000110

100101

010101

110100

001101

101100

011100

101000

100100

100011

010011

110010

001011

101010

011010

000101

001100

100110

010110

001001

001110

010001

100001

010100

011000

100010

1001

011101

101101

110001

110101

101001

011001

111000

111001

100101

010101

110100

001101

101100

011100

010111

011011

100011

010011

110010

001011

101010

011010

111010

110011

100110

010110

110110

001110

101110

011110

101011

100111

011101

1001

0101

D2.1

D3.1

D4.1

D5.1

D6.1

D7.1

D8.1

D9.1

D10.1

D11.1

D12.1

D13.1

D14.1

D15.1

D16.1

D17.1

D18.1

D19.1

D20.1

D21.1

D22.1

D23.1

D24.1

D25.1

D26.1

D27.1

D28.1

D29.1

D30.1

D31.1

D0.2

D1.2

24

CY7B923

CY7B933

Valid Data Characters (SC/D = LOW) (continued)

Data

Byte

Name

Bits

Current RD−

Current RD+

HGF EDCBA

abcdei

fghj

abcdei

fghj

D2.2

D3.2

010

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

101101

0101

010010

110001

001010

101001

011001

000111

000110

100101

010101

110100

001101

101100

011100

101000

100100

100011

010011

110010

001011

101010

011010

000101

001100

100110

010110

001001

001110

010001

100001

010100

0101

110001

110101

101001

011001

111000

111001

100101

010101

110100

001101

101100

011100

010111

011011

100011

010011

110010

001011

101010

011010

111010

110011

100110

010110

110110

001110

101110

011110

101011

0101

D4.2

D5.2

D6.2

D7.2

D8.2

D9.2

D10.2

D11.2

D12.2

D13.2

D14.2

D15.2

D16.2

D17.2

D18.2

D19.2

D20.2

D21.2

D22.2

D23.2

D24.2

D25.2

D26.2

D27.2

D28.2

D29.2

D30.2

D31.2

25

CY7B923

CY7B933

Valid Data Characters (SC/D = LOW) (continued)

Data

Byte

Name

Bits

Current RD−

Current RD+

HGF EDCBA

abcdei

fghj

abcdei

fghj

D0.3

D1.3

011

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

100111

0011

1100

0011

1100

0011

1100

0011

1100

0011

1100

0011

1100

0011

011000

100010

010010

110001

001010

101001

011001

000111

000110

100101

010101

110100

001101

101100

011100

101000

100100

100011

010011

110010

001011

101010

011010

000101

001100

100110

010110

001001

001110

010001

100001

010100

1100

011101

101101

110001

110101

101001

011001

111000

111001

100101

010101

110100

001101

101100

011100

010111

011011

100011

010011

110010

001011

101010

011010

111010

110011

100110

010110

110110

001110

101110

011110

101011

1100

0011

1100

0011

1100

0011

1100

0011

1100

0011

1100

0011

1100

D2.3

D3.3

D4.3

D5.3

D6.3

D7.3

D8.3

D9.3

D10.3

D11.3

D12.3

D13.3

D14.3

D15.3

D16.3

D17.3

D18.3

D19.3

D20.3

D21.3

D22.3

D23.3

D24.3

D25.3

D26.3

D27.3

D28.3

D29.3

D30.3

D31.3

26

CY7B923

CY7B933

Valid Data Characters (SC/D = LOW) (continued)

Data

Byte

Name

Bits

Current RD−

Current RD+

HGF EDCBA

abcdei

fghj

abcdei

fghj

D0.4

D1.4

100

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

100111

0010

1101

0010

1101

0010

1101

0010

1101

0010

1101

0010

1101

0010

011000

100010

010010

110001

001010

101001

011001

000111

000110

100101

010101

110100

001101

101100

011100

101000

100100

100011

010011

110010

001011

101010

011010

000101

001100

100110

010110

001001

001110

010001

100001

010100

1101

011101

101101

110001

110101

101001

011001

111000

111001

100101

010101

110100

001101

101100

011100

010111

011011

100011

010011

110010

001011

101010

011010

111010

110011

100110

010110

110110

001110

101110

011110

101011

1101

0010

1101

0010

1101

0010

1101

0010

1101

0010

1101

0010

1101

D2.4

D3.4

D4.4

D5.4

D6.4

D7.4

D8.4

D9.4

D10.4

D11.4

D12.4

D13.4

D14.4

D15.4

D16.4

D17.4

D18.4

D19.4

D20.4

D21.4

D22.4

D23.4

D24.4

D25.4

D26.4

D27.4

D28.4

D29.4

D30.4

D31.4

27

CY7B923

CY7B933

Valid Data Characters (SC/D = LOW) (continued)

Data

Byte

Name

Bits

Current RD−

Current RD+

HGF EDCBA

abcdei

fghj

abcdei

fghj

D0.5

D1.5

101

110

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

00000

00001

00010

100111

1010

0110

011000

100010

010010

110001

001010

101001

011001

000111

000110

100101

010101

110100

001101

101100

011100

101000

100100

100011

010011

110010

001011

101010

011010

000101

001100

100110

010110

001001

001110

010001

100001

010100

011000

100010

010010

1010

011101

101101

110001

110101

101001

011001

111000

111001

100101

010101

110100

001101

101100

011100

010111

011011

100011

010011

110010

001011

101010

011010

111010

110011

100110

010110

110110

001110

101110

011110

101011

100111

011101

101101

1010

0110

D2.5

D3.5

D4.5

D5.5

D6.5

D7.5

D8.5

D9.5

D10.5

D11.5

D12.5

D13.5

D14.5

D15.5

D16.5

D17.5

D18.5

D19.5

D20.5

D21.5

D22.5

D23.5

D24.5

D25.5

D26.5

D27.5

D28.5

D29.5

D30.5

D31.5

D0.6

D1.6

D2.6

28

CY7B923

CY7B933

Valid Data Characters (SC/D = LOW) (continued)

Data

Byte

Name

Bits

Current RD−

Current RD+

HGF EDCBA

abcdei

fghj

abcdei

fghj

D3.6

D4.6

110

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

110001

0110

110001

001010

101001

011001

000111

000110

100101

010101

110100

001101

101100

011100

101000

100100

100011

010011

110010

001011

101010

011010

000101

001100

100110

010110

001001

001110

010001

100001

010100

0110

110101

101001

011001

111000

111001

100101

010101

110100

001101

101100

011100

010111

011011

100011

010011

110010

001011

101010

011010

111010

110011

100110

010110

110110

001110

101110

011110

101011

0110

D5.6

D6.6

D7.6

D8.6

D9.6

D10.6

D11.6

D12.6

D13.6

D14.6

D15.6

D16.6

D17.6

D18.6

D19.6

D20.6

D21.6

D22.6

D23.6

D24.6

D25.6

D26.6

D27.6

D28.6

D29.6

D30.6

D31.6

29

CY7B923

CY7B933

Valid Data Characters (SC/D = LOW) (continued)

Data

Byte

Name

Bits

Current RD−

Current RD+

HGF EDCBA

abcdei

fghj

abcdei

fghj

D0.7

D1.7

111

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

100111

0001

1110

0001

1110

0001

1110

0001

0111

1110

0111

1110

0001

1110

0001

1110

0001

011000

100010

010010

110001

001010

101001

011001

000111

000110

100101

010101

110100

001101

101100

011100

101000

100100

100011

010011

110010

001011

101010

011010

000101

001100

100110

010110

001001

001110

010001

100001

010100

1110

011101

101101

110001

110101

101001

011001

111000

111001

100101

010101

110100

001101

101100

011100

010111

011011

100011

010011

110010

001011

101010

011010

111010

110011

100110

010110

110110

001110

101110

011110

101011

1110

0001

1110

0001

1110

0001

1000

0001

1000

1110

0001

1110

0001

1110

0001

1110

D2.7

D3.7

D4.7

D5.7

D6.7

D7.7

D8.7

D9.7

D10.7

D11.7

D12.7

D13.7

D14.7

D15.7

D16.7

D17.7

D18.7

D19.7

D20.7

D21.7

D22.7

D23.7

D24.7

D25.7

D26.7

D27.7

D28.7

D29.7

D30.7

D31.7

30

CY7B923

CY7B933

)

Valid Special Character Codes and Sequences (SC/D = HIGH)^{[23, 24]}

Bits

EDCBA

Current RD−

fghj

0100

Current RD+

fghj

1011

S.C. Byte Name

K28.0

S.C. Code Name

HGF

000

abcdei

001111

111010

110110

101110

011110

abcdei

110000

000101

001001

010001

100001

C0.0

(C00)

(C01)

(C02)

(C03)

(C04)

(C05)

(C06)

(C07)

(C08)

(C09)

(C0A)

(C0B)

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

K28.1

C1.0

C2.0

C3.0

C4.0

C5.0

C6.0

C7.0

C8.0

C9.0

C10.0

C11.0

000

1001

0101

0011

0010

1010

0110

1000

0110

1010

1100

1101

0101

1001

0111

K28.2

K28.3

K28.4

K28.5

K28.6

K28.7

K23.7

K27.7

K29.7

K30.7

[25]

[26]

Idle

C0.1

C1.1

(C20)

(C21)

001

00000

00001

−K28.5+,D21.4,D21.5,D21.5,repeat

−K28.5+,D21.4,D10.2,D10.2,repeat

R_RDY

[27]

EOFxx

C−SOF

P−SOF

C2.1

(C22)

001

00010

−K28.5,Dn.xxx0 +K28.5,Dn.xxx1

Follows K28.1 for ESCON Connect−SOF (Rx indication only)

C7.1 (C27) 001 00111 001111

1000

110000

0111

Follows K28.5 for ESCON Passive−SOF (Rx indication only)

C7.2

(C47)

010

00111

001111

Code Rule Violation and SVS Tx Pattern

[28]

[29]

[30]

Exception

−K28.5

C0.7

C1.7

C2.7

(CE0)

(CE1)

(CE2)

111

00000

00001

00010

100111

001111

110000

1000

1010

0101

011000

001111

110000

0111

1010

0101

[29]

[30]

+K28.5

Running Disparity Violation Pattern

[31]

Exception

C4.7

(CE4)

111

00100

110111

0101

001000

1010

Notes:

23. All codes not shown are reserved.

24. Notation for Special Character Byte Name is consistent with Fibre Channel and ESCON naming conventions. Special Character Code Name is intended to

describe binary information present on I/O pins. Common usage for the name can either be in the form used for describing Data patterns (i.e., C0.0 through

C31.7), or in hex notation (i.e., Cnn where nn=the specified value between 00 and FF).

25. C0.1 = Transmit Negative K28.5 (−K28.5+) disregarding Current RD when input is held for only one byte time. If held longer, transmitter begins sending the

repeating transmit sequence −K28.5+, D21.4, D21.5, D21.5, (repeat all four bytes)... defined in X3.230 as the primitive signal “Idle word.” This Special

Character input must be held for four (4) byte times or multiples of four bytes or it will be truncated by the new data. The receiver will never output this Special

Character, since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.

26. C1.1 = Transmit Negative K28.5 (−K28.5+) disregarding Current RD when input is held for only one byte time. If held longer, transmitter begins sending the

repeating transmit sequence −K28.5+, D21.4, D10.2, D10.2,(repeat all four bytes)... defined in X3.230 as the primitive signal “Receiver_Ready (R_RDY).”

This Special Character input must be held for four (4) byte times or multiples of four bytes or it will be truncated by the new data.

The receiver will never output this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7 and the subsequent bytes are decoded as data.

27. C2.1 = Transmit either −K28.5+ or +K28.5− as determined by Current RD and modify the Transmission Character that follows, by setting its least significant

bit to 1 or 0. If Current RD at the start of the following character is plus (+) the LSB is set to 0, and if Current RD is minus (−) the LSB becomes 1. This

modification allows construction of X3.230 “EOF” frame delimiters wherein the second data byte is determined by the Current RD.

For example, to send “EOFdt” the controller could issue the sequence C2.1−D21.4− D21.4−D21.4, and the HOTLink Transmitter will send either

K28.5−D21.4−D21.4−D21.4 or K28.5−D21.5− D21.4−D21.4 based on Current RD. Likewise to send “EOFdti” the controller could issue the sequence

C2.1−D10.4−D21.4−D21.4, and the HOTLink Transmitter will send either K28.5−D10.4−D21.4− D21.4 or K28.5−D10.5−D21.4− D21.4 based on Current RD.

The receiver will never output this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.

28. C0.7 = Transmit a deliberate code rule violation. The code chosen for this function follows the normal Running Disparity rules. Transmission of this Special

Character has the same effect as asserting SVS = HIGH.

The receiver will only output this Special Character if the Transmission Character being decoded is not found in the tables.

31

CY7B923

CY7B933

Ordering Information

Package

Name

Operating

Range

Speed

Ordering Code

Package Type

28-Lead Plastic Leaded Chip Carrier

28-Lead Small Outline IC

Standard

CY7B923-JC

J64

S21

L64

J64

Commercial

CY7B923-JI

Industrial

CY7B923-SC

Commercial

Military

CY7B923-LMB

CY7B923-400JC

CY7B923-400JI

CY7B923-155JC

CY7B923-155JI

28-Square Leadless Chip Carrier

28-Lead Plastic Leaded Chip Carrier

400

155

Commercial

Industrial

Commercial

Industrial

Operating

Speed

Ordering Code

CY7B933-JC

Package Name

Package Type

28-Lead Plastic Leaded Chip Carrier

28-Lead Small Outline IC

Range

Commercial

Industrial

Standard

J64

S21

L64

J64

CY7B933-JI

CY7B933-SC

Commercial

Military

CY7B933-LMB

CY7B933-400JC

CY7B933-400JI

CY7B933-155JC

CY7B933-155JI

28-Square Leadless Chip Carrier

28-Lead Plastic Leaded Chip Carrier

28-Lead plastic Leaded Chip Carrier

28-Lead Plastic Leaded Chip Carrier

400

Commercial

Industrial

155

Commercial

Industrial

Notes:

29. C1.7 = Transmit Negative K28.5 (−K28.5+) disregarding Current RD.

The receiver will only output this Special Character if K28.5 is received with the wrong running disparity. The receiver will output C1.7 if −K28.5 is received

with RD+, otherwise K28.5 is decoded as C5.0 or C2.7.

30. C2.7 = Transmit Positive K28.5 (+K28.5−) disregarding Current RD.

The receiver will only output this Special Character if K28.5 is received with the wrong running disparity. The receiver will output C2.7 if +K28.5 is received

with RD−, otherwise K28.5 is decoded as C5.0 or C1.7

31. C4.7 = Transmit a deliberate code rule violation to indicate a Running Disparity violation.

The receiver will only output this Special Character if the Transmission Character being decoded is found in the tables, but Running Disparity does not match.

This might indicate that an error occurred in a prior byte.

32

CY7B923

CY7B933

MILITARY SPECIFICATIONS

Group A Subgroup Testing

Switching Characteristics

Parameter

Subgroup

9, 10, 11

t

CKW

DC Characteristics

9, 10, 11

B

Parameter

Subgroup

1, 2, 3

CPWH

CPWL

SD

V

OHT

V

1, 2, 3

1, 2

OLT

V

OHE

HD

V

1, 2, 3

OLE

SENP

HENP

PDR

PPWH

PDF

RISE

FALL

CKR

CPRH

CPRL

RH

V

ODIF

I

OST

V

IHT

ILT

IHE

ILE

I

IHT

ILT

IHE

ILE

CC

PRF

PRH

A

V

DIFF

IHH

ILL

ROH

H

CKX

CPXH

CPXL

DS

Document #: 38−00189−I

33

CY7B923

CY7B933

Package Diagrams

28-Lead Plastic Leaded Chip Carrier J64

51-85001-A

28-Square Leadless Chip Carrier L64

MIL-STD-1835 C-4

51-80051

34

CY7B923

CY7B933

Package Diagrams (continued)

28-Lead (300-Mil) Molded SOIC S21

51-85026-A

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	CY7B933-400JXCT
厂家：	CYPRESS
描述：	Telecom Circuit, 1-Func, BICMOS, PQCC28, LCC-28
文件：	总35页 (文件大小：630K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7B933-400JXCT [CYPRESS]

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