CY7B993V-2AXIT_技术文档

RoboClock^

CY7B993V

CY7B994V

High-speed Multi-phase PLL Clock Buffer

Features

Functional Description

• 500-ps max. Total Timing Budget™ (TTB™) window

The CY7B993V and CY7B994V High-speed Multi-phase PLL

Clock Buffers offer user-selectable control over system clock

functions. This multiple-output clock driver provides the

system integrator with functions necessary to optimize the

timing of high-performance computer and communication

systems.

• 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V)

input/output operation

• Matched pair output skew < 200 ps

• Zero input-to-output delay

These devices feature a guaranteed maximum TTB window

specifying all occurrences of output clocks with respect to the

input reference clock across variations in output frequency,

supply voltage, operating temperature, input edge rate, and

process.

Eighteen configurable outputs each drive terminated trans-

mission lines with impedances as low as 50Ω while delivering

minimal and specified output skews at LVTTL levels. The outputs

are arranged in five banks. Banks 1 to 4 of four outputs allow

a divide function of 1 to 12, while simultaneously allowing

phase adjustments in 625–1300-ps increments up to 10.4 ns.

One of the output banks also includes an independent clock

invert function. The feedback bank consists of two outputs,

which allows divide-by functionality from 1 to 12 and limited

phase adjustments. Any one of these eighteen outputs can be

connected to the feedback input as well as driving other inputs.

• 18 LVTTL outputs driving 50Ω terminated lines

• 16 outputs at 200 MHz: Commercial temperature

• 6 outputs at 200 MHz: Industrial temperature

• 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable

reference inputs

• Phaseadjustmentsin625-/1300-psstepsupto±10.4 ns

• Multiply/divide ratios of 1–6, 8, 10, 12

• Individual output bank disable

• Output high-impedance option for testing purposes

• Fully integrated phase-locked loop (PLL) with lock

indicator

• <50-ps typical cycle-to-cycle jitter

• Single 3.3V ± 10% supply

• 100-pin TQFP package

Selectable reference input is a fault tolerance feature that

allows smooth change-over to secondary clock source, when

the primary clock source is not in operation. The reference

inputs and feedback inputs are configurable to accommodate

both LVTTL or Differential (LVPECL) inputs. The completely

integrated PLL reduces jitter and simplifies board layout.

• 100-lead BGA package

FBKA+

Functional

FBKA–

LOCK

FBKB+

Block Diagram

FBKB–

Control Logic

VCO

Phase

FBSEL

Freq.

Divide and Phase

Generator

Filter

FS

REFA+

REFA–

Detector

REFB+

REFB–

REFSEL

3

OUTPUT_MODE

Divide and

Phase

FBF0

3

QFA0

QFA1

FBDS0

FBDS1

FBDIS

Feedback Bank

Bank 4

Select

Matrix

4QA0

4QA1

4F0

3

Divide and

Phase

4F1

4DS0

4DS1

DIS4

4QB0

4QB1

Select

Matrix

3QA0

3QA1

3F0

3F1

3DS0

3DS1

DIS3

INV3

3

Divide and

Phase

Bank 3

Bank 2

Select

3QB0

3QB1

Matrix

3

2QA0

2QA1

3

2F0

Divide and

Phase

2F1

2DS0

2DS1

DIS2

Select

2QB0

2QB1

Matrix

1QA0

1QA1

1F0

1F1

1DS0

1DS1

DIS1

3

Divide and

Phase

Bank 1

Select

1QB0

1QB1

Matrix

Cypress Semiconductor Corporation

Document #: 38-07127 Rev. *F

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 10, 2005

RoboClock^

CY7B993V

CY7B994V

Pin Configurations

100-pin TQFP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

GND

3F1

4F1

1

2

3

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VCCQ

REFA+

REFA –

REFSEL

REFB–

REFB+

2F0

FS

GND

2QA0

VCCN

2QA1

GND

3F0

4F0

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

4DS1

3DS1

GND

4QB1

VCCN

4QB0

GND

4QA1

VCCN

4QA0

GND

2DS1

1DS1

VCCQ

4DS0

3DS0

2DS0

CY7B993/4V

GND

2QB0

VCCN

2QB1

GND

FBF0

1F0

GND

VCCQ

FBDIS

DIS4

1DS0

GND

24

25

DIS3

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Document #: 38-07127 Rev. *F

Page 2 of 15

RoboClock^

CY7B993V

CY7B994V

Pin Configurations (continued)

100-lead BGA

1

2

3

4

5

6

7

8

9

10

1QB1

1QB0

1QA1

1QA0

QFA0

QFA1

FBKB+ VCCQ FBKA– FBKA+

A

B

C

D

E

F

VCCN

GND

VCCN

GND

VCCQ

DIS1

VCCN

GND

VCCN

GND

VCCQ FBKB– FBSEL REFA+

GND

4F0

GND

3F1

VCCQ

2F0

GND

REFA–

FBDS1 FBDS0

LOCK

4QB1

4QB0

4QA1

VCCQ REFSEL REFB–

(3_level) (3_level)

(3_level) (3_level) (3_level)

4DS1

VCCN

3F0

4F1

FS

GND

VCCN REFB+

(3_level)

(3_level) (3_level)

3DS1

VCCN

FBF0

GND

VCCN

2QA0

2QA1

2QB0

2QB1

DIS4

(3_level)

2DS1

VCCQ

1F0

VCCQ

(3_level)

G

H

J

OUTPUT

1DS1

1DS0

4QA0

4DS0

GND

VCCQ MODE FBDIS

(3_level)

(3_level) (3_level)

3DS0

2DS0

INV3

VCCN

3QA0

VCCN

3QA1

GND

DIS3

(3_level) (3_level) (3_level)

(3_level)

2F1

1F1

DIS2

3QB0

3QB1

(3_level) (3_level)

K

[1]

Pin Definitions

Pin Name

FBSEL

I/O

Input

Pin Type

LVTTL

Pin Description

Feedback Input Select: When LOW, FBKA inputs are selected. When HIGH, the FBKB

inputs are selected. This input has an internal pull-down.

FBKA+, FBKA–

FBKB+, FBKB–

Input

LVTTL/ Feedback Inputs: One pair of inputs selected by the FBSEL is used to feedback the clock

LVDIFF output xQn to the phase detector. The PLL will operate such that the rising edges of the

reference and feedback signals are aligned in both phase and frequency. These inputs

can operate as differential PECL or single-ended TTL inputs. When operating as a

single-ended LVTTL input, the complementary input must be left open.

REFA+, REFA–

REFB+, REFB–

Input

LVTTL/ Reference Inputs: These inputs can operate as differential PECL or single-ended TTL

LVDIFF reference inputs to the PLL. When operating as a single-ended LVTTL input, the comple-

mentary input must be left open.

REFSEL

FS

LVTTL

Reference Select Input: The REFSEL input controls how the reference input is

configured. When LOW, it will use the REFA pair as the reference input. When HIGH, it

will use the REFB pair as the reference input. This input has an internal pull-down.

Input

3-level

Input

Frequency Select: This input must be set according to the nominal frequency (f_NOM) (see

Table 1).

FBF0

3-level

Feedback Output Phase Function Select: This input determines the phase function of

the Feedback bank’s QFA[0:1] outputs (see Table 3).

Input

Note:

1. For all three-state inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination

CC

circuitry holds an unconnected input to V /2.

CC

Document #: 38-07127 Rev. *F

Page 3 of 15

RoboClock^

CY7B993V

CY7B994V

Pin Definitions (continued)^[1]

Pin Name

I/O

Pin Type

Pin Description

FBDS[0:1]

Input

3-level

Feedback Divider Function Select: These inputs determine the function of the QFA0

Input

and QFA1 outputs (see Table 4).

FBDIS

Input

LVTTL

Feedback Disable: This input controls the state of QFA[0:1]. When HIGH, the QFA[0:1]

is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is determined by

OUTPUT_MODE. When LOW, the QFA[0:1] is enabled (see Table 5). This input has an

internal pull-down.

[1:4]F[0:1]

[1:4]DS[0:1]

DIS[1:4]

Input

3-level

Input

Output Phase Function Select: Each pair controls the phase function of the respective

bank of outputs (see Table 3).

3-level

Output Divider Function Select: Each pair controls the divider function of the respective

bank of outputs (see Table 4).

Output Disable: Each input controls the state of the respective output bank. When HIGH,

the output bank is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is deter-

mined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled (see Table 5).

These inputs each have an internal pull-down.

Input

LVTTL

INV3

Input

3-level

Input

Invert Mode: This input only affects Bank 3. When this input is LOW, each matched output

pair will become complementary (3QA0+, 3QA1–, 3QB0+, 3QB1–). When this input is

HIGH, all four outputs in the same bank will be inverted. When this input is MID all four

outputs will be non inverting.

LOCK

Output LVTTL

PLL Lock Indicator: When HIGH, this output indicates the internal PLL is locked to the

reference signal. When LOW, the PLL is attempting to acquire lock.

OUTPUT_MODE Input

3-Level Output Mode: This pin determines the clock outputs’ disable state. When this input is

Input

HIGH, the clock outputs will disable to high-impedance (HI-Z). When this input is LOW,

the clock outputs will disable to “HOLD-OFF” mode. When in MID, the device will enter

factory test mode.

QFA[0:1]

Output LVTTL

Clock Feedback Output: This pair of clock outputs is intended to be connected to the

FB input. These outputs have numerous divide options and three choices of phase adjust-

ments. The function is determined by the setting of the FBDS[0:1] pins and FBF0.

[1:4]Q[A:B][0:1]

Clock Output: These outputs provide numerous divide and phase select functions deter-

mined by the [1:4]DS[0:1] and [1:4]F[0:1] inputs.

VCCN

VCCQ

GND

PWR

Output Buffer Power: Power supply for each output pair.

Internal Power: Power supply for the internal circuitry.

Device Ground.

The REF inputs can be changed dynamically. When changing

from one reference input to the other of the same frequency,

the PLL is optimized to ensure that the clock output period will

not be less than the calculated system budget (t_MIN= t_REF

Block Diagram Description

Phase Frequency Detector and Filter

These two blocks accept signals from the REF inputs (REFA+,

REFA–, REFB+, or REFB–) and the FB inputs (FBKA+,

FBKA–, FBKB+, or FBKB–). Correction information is then

generated to control the frequency of the voltage-controlled

oscillator (VCO). These two blocks, along with the VCO, form

a PLL that tracks the incoming REF signal.

The CY7B993V/994V have a flexible REF and FB input

scheme. These inputs allow the use of either differential

LVPECL or single-ended LVTTL inputs. To configure as

single-ended LVTTL inputs, the complementary pin must be

left open (internally pulled to 1.5V). The other input pin can

then be used as an LVTTL input. The REF inputs are also

tolerant to hot insertion.

(nominal reference clock period) – t_CCJ(cycle-to-cycle jitter) –

t_PDEV(max. period deviation)) while reacquiring the lock.

VCO, Control Logic, Divider, and Phase Generator

The VCO accepts analog control inputs from the PLL filter

block. The FS control pin setting determines the nominal

operational frequency range of the divide by one output (f_NOM

)

of the device. f_NOMis directly related to the VCO frequency.

There are two versions: a low-speed device (CY7B993V)

where f_NOMranges from 12 MHz to 100 MHz, and a

high-speed device (CY7B994V) that ranges from 24 MHz to

200 MHz. The FS setting for each device is shown in Table 1.

The f_NOMfrequency is seen on “divide-by-one” outputs. For

the CY7B994V, the upper f_NOMrange extends from 96 MHz to

200 MHz.

Document #: 38-07127 Rev. *F

Page 4 of 15

RoboClock^

CY7B993V

CY7B994V

Table 1. Frequency Range Select

CY7B993V

Table 3. Output Skew Select Function

CY7B994V

f_NOM(MHz)

Function

Selects

Output Skew Function

f

_NOM(MHz)

FS^[2]

LOW

Min.

12

Max.

26

Min.

Max.

52

[1:4]F0

Feed-

back

Bank

and

24

48

96

[1:4]F1 FBF0

Bank1 Bank2 Bank3 Bank4

MID

24

52

100

200

LOW

MID

–4t_U

–3t_U

–2t_U

–1t_U

0t_U

–4t_U

–3tu

–2t_U

–8t_U

–7t_U

–6t_U

–8t_U

–7t_U

–6t_U

–4t_U

NA

0tu

NA

+4t_U

HIGH

48

100

Time Unit Definition

LOW HIGH

Selectable skew is in discrete increments of time unit (t_U). The

value of a t_Uis determined by the FS setting and the maximum

nominal output frequency. The equation to be used to

determine the t_Uvalue is as follows:

MID

LOW

MID

–1t_UBK1^[3]BK1^[3]

0t_U0t_U0t_U

+1t_UBK2^[3]BK2^[3]

HIGH

+1t_U

+2t_U

+3t_U

+4t_U

t_U= 1/(f_NOM*N).

N is a multiplication factor which is determined by the FS

setting. f_NOMis nominal frequency of the device. N is defined

in Table 2.

HIGH LOW

HIGH MID

HIGH HIGH

+2t_U

+3t_U

+4t_U

+6t_U

+7t_U

+8t_U

+6t_U

+7t_U

+8t_U

Table 2. N Factor Determination

CY7B993V

CY7B994V

Table 4. Output Divider Function

Function

f

_NOM(MHz) at

f_NOM(MHz) at

FS

LOW

MID

N

which t_U=1.0 ns

15.625

N

32

16

8

which t_U=1.0 ns

Selects

Output Divider Function

64

32

16

31.25

62.5

125

[1:4]DS1 [1:4]DS0

Feed-

back

Bank

31.25

62.5

and

Bank

1

Bank Bank Bank

FBDS1

FBDS0

2

/1

3

/1

4

/1

HIGH

LOW

MID

LOW

MID

/1

/2

/1

/2

Divide and Phase Select Matrix

/2

The Divide and Phase Select Matrix is comprised of five

independent banks: four banks of clock outputs and one bank

for feedback. Each clock output bank has two pairs of

low-skew, high-fanout output buffers ([1:4]Q[A:B][0:1]), two

phase function select inputs ([1:4]F[0:1]), two divider function

selects ([1:4]DS[0:1]), and one output disable (DIS[1:4]).

HIGH

LOW

MID

/3

/4

MID

/5

MID

HIGH

LOW

MID

/6

The feedback bank has one pair of low-skew, high-fanout

output buffers (QFA[0:1]). One of these outputs may connect

to the selected feedback input (FBK[A:B]±). This feedback

bank also has one phase function select input (FBF0), two

divider function selects FSDS[0:1], and one output disable

(FBDIS).

HIGH

/8

/10

/12

/10

/12

/10

/12

/10

/12

/10

/12

HIGH

The phase capabilities that are chosen by the phase function

select pins are shown in Table 3. The divide capabilities for

each bank are shown in Table 4.

Figure 1 illustrates the timing relationship of programmable

skew outputs. All times are measured with respect to REF with

the output used for feedback programmed with 0t_Uskew. The

PLL naturally aligns the rising edge of the FB input and REF

input. If the output used for feedback is programmed to

another skew position, then the whole t_Umatrix will shift with

respect to REF. For example, if the output used for feedback

is programmed to shift –8t_U, then the whole matrix is shifted

forward in time by 8t_U. Thus an output programmed with 8t_U

of skew will effectively be skewed 16t_Uwith respect to REF.

Notes:

2. The level to be set on FS is determined by the “nominal” operating frequency (f

) of the V and Phase Generator. f always appears on an output when

NOM

CO

the output is operating in the undivided mode. The REF and FB are at f

when the output connected to FB is undivided.

NOM

3. BK1, BK2 denotes following the skew setting of Bank1 and Bank2, respectively.

Document #: 38-07127 Rev. *F

Page 5 of 15

RoboClock^

CY7B993V

CY7B994V

FBInput

REFInput

1F[1:0]

2F[1:0]

3F[1:0]

4F[1:0]

LL

–8t_U

–7t_U

–6t_U

(N/A)

LM

LH

(N/A)

–4t_U

–3t_U

LL

LM

–2t

(N/A)

MM

LH

U

–1t

ML

U

MM

0t

U

+1t

(N/A)

MH

(N/A)

+2t

+3t

HL

HM

U

+4t

+6t

HH

U

(N/A)

HL

(N/A)

HM

HH

+7t

+8t

U

Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output^[4]

Output Disable Description

HOLD-OFF state, non-inverting outputs are driven to a logic

LOW state on its falling edge. Inverting outputs are driven to a

logic HIGH state on its rising edge. This ensures the output

clocks are stopped without glitch. When a bank of outputs is

disabled to HI-Z state, the respective bank of outputs will go

HI-Z immediately.

The feedback Divide and Phase Select Matrix Bank has two

outputs, and each of the four Divide and Phase Select Matrix

Banks have four outputs. The outputs of each bank can be

independently put into a HOLD-OFF or high-impedance state.

The combination of the OUTPUT_MODE and DIS[1:4]/FBDIS

inputs determines the clock outputs’ state for each bank. When

the DIS[1:4]/FBDIS is LOW, the outputs of the corresponding

bank will be enabled. When the DIS[1:4]/FBDIS is HIGH, the

outputs for that bank will be disabled to a high-impedance

(HI-Z) or HOLD-OFF state depending on the OUTPUT_MODE

input. Table 5 defines the disabled output functions.

Table 5. DIS[1:4]/FBDIS Pin Functionality

OUTPUT_MODE

HIGH/LOW

HIGH

DIS[1:4]/FBDIS

Output Mode

ENABLED

HI-Z

HOLD-OFF

FACTORY TEST

LOW

HIGH

X

LOW

MID

The HOLD-OFF state is intended to be a power saving feature.

An output bank is disabled to the HOLD-OFF state in a

maximum of six output clock cycles from the time when the

disable input (DIS[1:4]/FBDIS) is HIGH. When disabled to the

Note:

4. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).

Document #: 38-07127 Rev. *F

Page 6 of 15

RoboClock^

CY7B993V

CY7B994V

INV3 Pin Function

Factory Test Reset

Bank3 has signal invert capability. The four outputs of Bank3

will act as two pairs of complementary outputs when the INV3

pin is driven LOW. In complementary output mode, 3QA0 and

3QB0 are non-inverting; 3QA1and 3QB1 are inverting outputs.

All four outputs will be inverted when the INV3 pin is driven

HIGH. When the INV3 pin is left in MID, the outputs will not

invert. Inversion of the outputs are independent of the skew

and divide functions. Therefore, clock outputs of Bank3 can be

inverted, divided, and skewed at the same time.

When in factory test mode (OUTPUT_MODE = MID), the

device can be reset to a deterministic state by driving the DIS4

input HIGH. When the DIS4 input is driven HIGH in factory test

mode, all clock outputs will go to HI-Z; after the selected

reference clock pin has five positive transitions, all the internal

finite state machines (FSM) will be set to a deterministic state.

The deterministic state of the state machines will depend on

the configurations of the divide selects, skew selects, and

frequency select input. All clock outputs will stay in

high-impedance mode and all FSMs will stay in the determin-

istic state until DIS4 is deasserted. When DIS4 is deasserted

(with OUTPUT_MODE still at MID), the device will re-enter

factory test mode.

Lock Detect Output Description

The LOCK detect output indicates the lock condition of the

integrated PLL. Lock detection is accomplished by comparing

the phase difference between the reference and feedback

inputs. Phase error is declared when the phase difference

between the two inputs is greater than the specified device

propagation delay limit (t_PD).

When in the locked state, after four or more consecutive

feedback clock cycles with phase-errors, the LOCK output will

be forced LOW to indicate out-of-lock state.

When in the out-of-lock state, 32 consecutive phase-errorless

feedback clock cycles are required to allow the LOCK output

to indicate lock condition (LOCK = HIGH).

If the feedback clock is removed after LOCK has gone HIGH,

a “Watchdog” circuit is implemented to indicate the out-of-lock

condition after a time-out period by deasserting LOCK LOW.

This time out period is based upon a divided down reference

clock.

Safe Operating Zone

Figure 2 illustrates the operating condition at which the device

does not exceed its allowable maximum junction temperature

of 150°C. Figure 2 shows the maximum number of outputs that

can operate at 185 MHz (with 25-pF load and no air flow) or

200 MHz (with 10-pF load and no air flow) at various ambient

temperatures. At the limit line, all other outputs are configured

to divide-by-two (i.e., operating at 92.5 MHz) or lower

frequencies. The device will operate below maximum

allowable junction temperature of 150°C when its configu-

ration (with the specified constraints) falls within the shaded

region (safe operating zone). Figure 2 shows that at 85°C, the

maximum number of outputs that can operate at 200 MHz is

6; and at 70°C, the maximum number of outputs that can

operate at 185 MHz is 16 (with 25-pF load and 0-m/s air flow).

This assumes that there is activity on the selected REF input.

If there is no activity on the selected REF input then the LOCK

detect pin may not accurately reflect the state of the internal

PLL.

Typical Safe Operating Zone

(25-pF Load, 0-m/s air flow)

100

95

90

85

80

75

70

Factory Test Mode Description

The device will enter factory test mode when the

OUTPUT_MODE is driven to MID. In factory test mode, the

device will operate with its internal PLL disconnected; input

level supplied to the reference input will be used in place of the

PLL output. In TEST mode the selected FB input(s) must be

tied LOW. All functions of the device are still operational in

factory test mode except the internal PLL and output bank

disables. The OUTPUT_MODE input is designed to be a static

input. Dynamically toggling this input from LOW to HIGH may

temporarily cause the device to go into factory test mode

(when passing through the MID state).

Safe Operating Zone

65

60

55

50

2

4

6

8

10

12

14

16

18

Number of Outputs at 185 MHz

Figure 2. Typical Safe Operating Zone

Document #: 38-07127 Rev. *F

Page 7 of 15

RoboClock^

CY7B993V

CY7B994V

Absolute Maximum Conditions^[5]

Output Current into Outputs (LOW)............................. 40 mA

Static Discharge Voltage........................................... > 1100V

(Above which the useful life may be impaired. For user guide-

(per MIL-STD-883, Method 3015)

lines, not tested.)

Latch-up Current.................................................. > ± 200 mA

Storage Temperature ................................–40°C to + 125°C

Operating Range

Ambient Temperature with

Power Applied............................................–40°C to + 125°C

Range

Commercial

Industrial

Ambient Temperature

V_CC

Supply Voltage to Ground Potential.............. –0.5V to + 4.6V

DC Input Voltage....................................–0.3V to V_CC+ 0.5V

0°C to +70°C

3.3V ± 10%

–40°C to +85°C

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

Max.

Unit

LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)

V_OH

V_OL

I_OZ

LVTTL HIGH Voltage QFA[0:1], [1:4]Q[A:B][0:1]

V_CC= Min., I_OH= –30 mA

_OH= –2 mA, V_CC= Min.

V_CC= Min., I_OL= 30 mA

_OL= 2 mA, V_CC= Min.

2.4

–

–100

–

0.5

100

V

µA

LOCK

LVTTL LOW Voltage QFA[0:1], [1:4]Q[A:B][0:1]

LOCK

I

High-impedance State Leakage Current

LVTTL Compatible Input Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4])

V_IH

LVTTL Input HIGH

FBK[A:B]±, REF[A:B]±

Min. < V_CC< Max.

2.0

V_CC+ 0.3

V

REFSEL, FBSEL, FBDIS,

DIS[1:4]

V_IL

LVTTL Input LOW

LVTTL V_IN>V_CC

FBK[A:B]±, REF[A:B]±

REFSEL, FBSEL, FBDIS, DIS[1:4]

FBK[A:B]±, REF[A:B]±

REFSEL, FBSEL, FBDIS, DIS[1:4] V_IN= V_CC

Min. < V_CC< Max.

–0.3

–

0.8

100

500

–

V

I_I

I_lH

V_CC= GND, V_IN= 3.63V

V_CC= Max., V_IN= V_CC

µA

LVTTL Input HIGH

Current

I_lL

LVTTL Input LOW

Current

FBK[A:B]±, REF[A:B]±

REFSEL, FBSEL, FBDIS, DIS[1:4]

V_CC= Max., V_IN= GND

–500

–

Three-level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST))

V_IHH

V_IMM

V_ILL

I_IHH

Three-level Input HIGH^[6]

Three-level Input MID^[6]

Three-level Input LOW^[6]

Min. < V_CC< Max.

0.87*V_CC

0.47*V_CC0.53*V_CC

–

V

µA

–

–50

–100

–200

–400

0.13*V_CC

Three-level Input

Three-level input pins excl. FBF0 V_IN= V_CC

FBF0

200

400

50

100

–

HIGH Current

I_IMM

I_ILL

Three-level Input

MID Current

Three-level input pins excl. FBF0 V_IN= V_CC/2

FBF0

Three-level Input

LOW Current

Three-level input pins excl. FBF0 V_IN= GND

FBF0

–

LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±)

V_DIFF

V_IHHP

V_ILLP

Input Differential Voltage

Highest Input HIGH Voltage

Lowest Input LOW Voltage

400

1.0

V_CC

mV

V

GND V_CC– 0.4

0.8 V_CC

V_COM

Common Mode Range (crossing voltage)

V

Notes:

5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

6. These inputs are normally wired to V , GND, or left unconnected (actual threshold voltages vary as a percentage of V ). Internal termination resistors hold

CC

the unconnected inputs at V /2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t

CC

time

LOCK

before all data sheet limits are achieved.

Document #: 38-07127 Rev. *F

Page 8 of 15

RoboClock^

CY7B993V

CY7B994V

Electrical Characteristics Over the Operating Range (continued)

Parameter Description

Operating Current

Test Conditions

Min.

Max.

Unit

[7]

I_CCI

Internal Operating

CY7B993V

CY7B994V

CY7B993V

CY7B994V

V_CC= Max., f_MAX

–

250

40

mA

Current

I_CCN

Output Current

V_CC= Max.,

Dissipation/Pair^[8]

C_LOAD= 25 pF,

50

R_LOAD= 50Ω at V_CC/2,

f_MAX

Capacitance

Parameter

C_IN

Description

Input Capacitance

Test Conditions

T_A= 25°C, f = 1 MHz, V_CC= 3.3V

Min.

Max.

5

Unit

pF

Switching Characteristics Over the Operating Range^{[9, 10, 11, 12, 13]}

CY7B993/4V-2

CY7B993/4V-5

Parameter

f_in

Description

Min. Typ. Max. Min. Typ. Max.

Unit

MHz

ps

Clock Input Frequency

CY7B993V

CY7B994V

CY7B993V

CY7B994V

12

24

12

24

–

100

200

100

200

250

12

24

12

24

–

100

200

100

200

250

550

f_out

Clock Output Frequency

t_SKEWPR

t_SKEWBNK

t_SKEW0

Matched-Pair Skew^{[14, 15]}

Intrabank Skew^{[14, 15]}

Output-Output Skew (same frequency and phase, rise to

–

ps

–

rise, fall to fall)^{[14, 15]}

t_SKEW1

t_SKEW2

Output-Output Skew (same frequency and phase, other

banks at different frequency, rise to rise, fall to fall)^{[14, 15]}

Output-Output Skew (invert to nominal of different banks,

compared banks at same frequency, rising edge to falling

edge aligned, other banks at same frequency)^{[14, 15]}

–

250

–

650

700

ps

t_SKEW3

Output-Output Skew (all output configurations outside of

–

500

200

150

100

–

800

300

ps

[14, 15]

t_SKEW1and t_SKEW2)

t_SKEWCPRComplementary Outputs Skew (crossing to crossing,

complementary outputs of the same bank)^{[14, 15, 16, 17]}

Cycle-to-Cycle Jitter (divide by 1 output frequency,

FB = divide by 1, 2, 3)

Cycle-to-Cycle Jitter (divide by 1 output frequency,

FB = divide by 4, 5, 6, 8, 10, 12)

Propagation Delay, REF to FB Rise

t_CCJ1-3

–

50

–

150 ps Peak

100 ps Peak

t_CCJ4-12

–

t_PD

–250

–

250 –500

500

ps

Notes:

7. I

measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (f

= 100 MHz for CY7B993V, f

= 200 MHz for

CCI

NOM

CY7B994V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.

8. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum I

at maximum frequency and maximum

CCN

load of 25 pF terminated to 50Ω at V /2.

CC

9. This is for non-three level inputs.

10. Assumes 25-pF max. load capacitance up to 185 MHz. At 200 MHz the max. load is 10 pF.

11. Both outputs of pair must be terminated, even if only one is being used.

12. Each package must be properly decoupled.

13. AC parameters are measured at 1.5V unless otherwise indicated.

14. Test Load C = 25 pF, terminated to V /2 with 50Ω up to185 MHz and 10-pF load to 200 MHz.

L

CC

15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when

all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.

16. Complementary output skews are measured at complementary signal pair intersections.

17. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-07127 Rev. *F

Page 9 of 15

RoboClock^

CY7B993V

CY7B994V

Switching Characteristics Over the Operating Range^{[9, 10, 11, 12, 13]}(continued)

CY7B993/4V-2

CY7B993/4V-5

Parameter

TTB

Description

Min. Typ. Max. Min. Typ. Max.

Unit

ps

Total Timing Budget window (same frequency and phase)^[17,

–

500

–

700

18]

t_PDDELTA

t_REFpwh

t_REFpwl

t_r/t_f

t_LOCK

t_RELOCK1

Propagation Delay difference between two devices^[17]

REF input (Pulse Width HIGH)^[19]

REF input (Pulse Width LOW)^[19]

Output Rise/Fall Time^[20]

PLL Lock Time From Power-up

PLL Relock Time (from same frequency, different phase)

with Stable Power Supply

–

2.0

0.15

–

200

–

2.0

10

500

–

2.0

0.15

–

200

–

2.0

10

500

ps

ns

ms

µs

–

t_RELOCK2

PLL Relock Time (from different frequency, different phase)

–

1000

–

1000

µs

with Stable Power Supply^[21]

t_ODCV

t_PWH

t_PWL

Output duty cycle deviation from 50%^[13]

Output HIGH time deviation from 50%^[22]

Output LOW time deviation from 50%^[22]

–1.0

1.0

1.5

2.0

–1.0

1.0

1.5

2.0

ns

UI

–

t_PDEV

Period deviation when changing from reference to

0.025

reference^[23]

t_OAZ

DIS[1:4]/FBDIS HIGH to output high-impedance from

ACTIVE^{[14, 24]}

1.0

0.5

10

14

1.0

0.5

10

14

ns

DIS[1:4]/FBDIS LOW to output ACTIVE from output

high-impedance^{[24, 25]}

AC Test Loads and Waveform^[26]

3.3V

R1

R2

For LOCK output only

R1 = 910Ω

For all other outputs

OUTPUT

R1 = 100Ω

R2 = 100Ω

C

L

R2 = 910Ω

C < 30 pF

L

C < 25 pF to 185 MHz

L

or 10 pF at 200 MHz

(Includes fixture and

probe capacitance)

(a) LVTTL AC Test Load

3.3V

GND

2.0V

0.8V

2.0V

0.8V

< 1 ns

(b)TTL Input Test Waveform

Notes:

18. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,

operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle

jitter, and dynamic phase error. TTB will be equal to or smaller than the maximum specified value at a given frequency.

19. Tested initially and after any design or process changes that may affect these parameters.

20. Rise and fall times are measured between 2.0V and 0.8V.

21. f

22. t

must be within the frequency range defined by the same FS state.

NOM

PWH

is measured at 2.0V. t

is measured at 0.8V.

PWL

23. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.

24. Measured at 0.5V deviation from starting voltage.

25. For t

minimum, C = 0 pF. For t

maximum, C = 25 pF to 185 MHz or 10 pF to 200 MHz.

OZA

L

OZA L

26. These figures are for illustrations only. The actual ATE loads may vary.

Document #: 38-07127 Rev. *F

Page 10 of 15

RoboClock^

CY7B993V

CY7B994V

AC Timing Diagrams^[13]

t

REFpwl

QFA0 or

t

REFpwh

[1:4]Q[A:B]0

REF

t_PD

t

SKEWPR

t

PWH

t

PWL

QFA1 or

[1:4]Q[A:B]1

2.0V

FB

Q

0.8V

t

CCJ1-3,4-12

[1:4]QA[0:1]

t

SKEWBNK

[1:4]QB[0:1]

Q

REF TO DEVICE 1 and 2

t

ODCV

t

ODCV

t

PD

FB DEVICE1

FB DEVICE2

t

SKEW0,1

t

SKEW0,1

t

PDELTA

t

PDELTA

Other Q

t

SKEWCPR

COMPLEMENTARY A

COMPLEMENTARY B

crossing

Q

t

SKEW2

t

SKEW2

crossing

INVERTED Q

Ordering Information

Propagation Max. Speed

Delay (ps)

250

(MHz)

100

200

Ordering Code

CY7B993V-2AC

CY7B993V-2ACT

CY7B993V-2AI

CY7B993V-2AIT

CY7B994V-2AC

CY7B994V-2ACT

CY7B994V-2BBC

CY7B994V-2BBCT

CY7B994V-2AI

Package Type

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-ball Thin Ball Grid Array

100-ball Thin Ball Grid Array - Tape and Reel

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-ball Thin Ball Grid Array

100-ball Thin Ball Grid Array -Tape and Reel

Operating Range

Commercial

Industrial

250

Industrial

Commercial

Industrial

250

CY7B994V-2AIT

CY7B994V-2BBI

CY7B994V-2BBIT

Document #: 38-07127 Rev. *F

Page 11 of 15

RoboClock^

CY7B993V

CY7B994V

Ordering Information (continued)

Propagation Max. Speed

Delay (ps)

500

(MHz)

100

200

Ordering Code

CY7B993V-5AC

CY7B993V-5ACT

CY7B993V-5AI

CY7B993V-5AIT

CY7B994V-5AC

CY7B994V-5ACT

CY7B994V-5BBC

CY7B994V-5BBCT

CY7B994V-5BBI

CY7B994V-5BBIT

CY7B994V-5AI

Package Type

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-ball Thin Ball Grid Array

100-ball Thin Ball Grid Array - Tape and Reel

100-ball Thin Ball Grid Array

100-ball Thin Ball Grid Array -Tape and Reel

100-lead Thin Quad Flat Pack

Operating Range

Commercial

Industrial

500

Industrial

Commercial

Industrial

500

CY7B994V-5AIT

100-lead Thin Quad Flat Pack - Tape and Reel

Lead-free

250

100

200

100

200

CY7B993V-2AXC

CY7B993V-2AXCT

CY7B993V-2AXI

CY7B993V-2AXIT

CY7B994V-2AXC

CY7B994V-2AXCT

CY7B994V-2BBXC

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-ball Thin Ball Grid Array

Commercial

Industrial

250

500

Industrial

Commercial

Industrial

CY7B994V-2BBXCT 100-ball Thin Ball Grid Array - Tape and Reel

CY7B994V-2AXI

CY7B994V-2AXIT

CY7B994V-2BBXI

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-ball Thin Ball Grid Array

CY7B994V-2BBXIT 100-ball Thin Ball Grid Array -Tape and Reel

CY7B993V-5AXC

CY7B993V-5AXCT

CY7B993V-5AXI

CY7B993V-5AXIT

CY7B994V-5AXC

CY7B994V-5AXCT

CY7B994V-5BBXC

CY7B994V-5BBXCT 100-ball Thin Ball Grid Array -Tape and Reel

CY7B994V-5BBXI 100-ball Thin Ball Grid Array

CY7B994V-5BBXIT 100-ball Thin Ball Grid Array - Tape and Reel

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

100-ball Thin Ball Grid Array

Commercial

Industrial

Commercial

Industrial

CY7B994V-5AXI

CY7B994V-5AXIT

100-lead Thin Quad Flat Pack

100-lead Thin Quad Flat Pack - Tape and Reel

Document #: 38-07127 Rev. *F

Page 12 of 15

RoboClock^

CY7B993V

CY7B994V

Package Diagrams

100-pin Thin Plastic Quad Flat Pack (TQFP) A100

51-85048-*B

Document #: 38-07127 Rev. *F

Page 13 of 15

RoboClock^

CY7B993V

CY7B994V

Package Diagrams (continued)

100-ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100

51-85107-*B

RoboClock is a registered trademark, and TTB and Total Timing Budget are trademarks, of Cypress Semiconductor. All product

and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-07127 Rev. *F

Page 14 of 15

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

RoboClock^

CY7B993V

CY7B994V

Document History Page

Document Title: RoboClock^CY7B994V/CY7B993V High-speed Multi-phase PLL Clock Buffer

Document Number: 38-07127

Orig. of

REV.

**

*A

*B

*C

ECN NO. Issue Date Change

Description of Change

Changed from Spec number: 38-00747 to 38-07127

Added three industrial packages

Added TTB Features

Power-up requirements to operating conditions information

109957

114376

116570

122794

123694

12/16/01

05/06/02

09/04/02

12/14/02

03/04/03

SZV

CTK

HWT

RBI

*D

RGL

Added min. F_outvalue of 12 MHz for CY7B993V and 24 MHz for CY7B994V

to switching characteristics table

Corrected prop delay limit parameter from (t_PDSL,M,H) to t_PDin the Lock Detect

Output Description paragraph

*E

*F

128462

391560

07/29/03

See ECN

RGL

Added clock input frequency (f_in) specifications in the switching characteristics

table

Added Lead-free devices

Added typical values for jitter

Document #: 38-07127 Rev. *F

Page 15 of 15


型号：	CY7B993V-2AXIT
厂家：	CYPRESS
描述：	High-speed Multi-phase PLL Clock Buffer 高速多相位锁相环时钟缓冲器时钟
文件：	总15页 (文件大小：392K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7B993V-2AXIT [CYPRESS]

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CY7B993V-5ACT

CY7B993V-5AI

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CY7B993V-5AXI

CY7B993V-5AXIT

CY7B993V-7AC

CY7B993V_05

CY7B993V_11

CY7B9940V