CY7B9940V [CYPRESS]
High-Speed Multi-Frequency PLL Clock Buffer; 高速多频PLL时钟缓冲器
| 型号： | CY7B9940V |
| 厂家： | 
CYPRESS |
| 描述： | High-Speed Multi-Frequency PLL Clock Buffer |
| 文件： | 总9页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RoboClockII™ Junior
CY7B9930V
CY7B9940V
High-Speed Multi-Frequency PLL Clock Buffer
Features
Functional Description
• 12–100MHz (CY7B9930V), or 24–200 MHz (CY7B9940V)
input/output operation
• Matched pair output skew < 200 ps
• Zero input-to-output delay
• 10 LVTTL 50% duty-cycle outputs capable of driving
50ω terminated lines
The CY7B9930V and CY7B9940V High-Speed Multi-
Frequency PLL Clock Buffers offer user-selectable control
over system clock functions. This multiple-output clock driver
provides the system integrator with functions necessary to
optimize the timing of high-performance computer or commu-
nication systems.
Ten configurable outputs can each drive terminated trans-
mission lines with impedances as low as 50Ω while delivering
minimal and specified output skews at LVTTL levels. The outputs
are arranged in three banks. The FB feedback bank consists
of two outputs, which allows divide-by functionality from 1 to
12. Any one of these ten outputs can be connected to the
feedback input as well as driving other inputs.
• Commercial temp. range with eight outputs at 200 MHz
• Industrial temp. range with eight outputs at 200 MHz
• 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and
hot insertable reference inputs
• Multiply ratios of (1–6, 8, 10, 12)
• Operation up to 12x input frequency
• Individual output bank disable for aggressive power
management and EMI reduction
• Output high-impedance option for testing purposes
• Fully integrated PLL with lock indicator
• Low cycle-to-cycle jitter (<100 ps peak-peak)
• Single 3.3V ± 10% supply
Selectable reference input is a fault tolerance feature that
allows smooth change over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs are configurable to accommodate both LVTTL or Differ-
ential (LVPECL) inputs. The completely integrated PLL
reduces jitter and simplifies board layout.
• 44-pin TQFP package
Functional Block Diagram
Pin Configuration
44-Pin TQFP
FBKA
LOCK
Control Logic
Divide
Generator
Phase
Freq.
Detector
VCO
Filter
FS
REFA+
REFA–
REFB+
3
3
REFB–
44 43 42 41 40 39 38 37 36 35 34
Output_Mode
REFSEL
GND
2QB1
VCCN
2QB0
GND
1
33
32
31
30
29
28
27
26
25
24
23
VCCQ
REFA+
REFA –
REFSEL
REFB–
REFB+
FS
2
3
QFA0
QFA1
Divide
Matrix
3
3
FBDS0
FBDS1
Feedback Bank
Bank 2
4
5
CY7B9930V/40V
GND
6
2QA0
2QA1
2QA1
VCCN
2QA0
GND
7
8
GND
2QB0
2QB1
9
VCCQ
DIS2
10
11
DIS2
DIS1
GND
DIS1
1QA0
1QA1
12 13
14 15
22
16 17 18
20 21
19
Bank 1
1QB0
1QB1
Cypress Semiconductor Corporation
Document #: 38-07271 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 25, 2002
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RoboClockII™ Junior
CY7B9930V
CY7B9940V
Pin Definitions[1]
Name
I/O
Type
Description
FBKA
Input LVTTL
Feedback Input.
REFA+, REFA– Input LVTTL/ Reference Inputs: These inputs can operate as differential PECL or single-ended TTL
REFB+, REFB–
REFSEL
LVDIFF reference inputs to the PLL. When operating as a single-ended LVTTL input, the comple-
mentary input must be left open.
Input LVTTL
Reference Select Input: The REFSEL input controls how the reference input is configured.
When LOW, it will use the REFA pair as the reference input. When HIGH, it will use the
REFB pair as the reference input. This input has an internal pull-down.
FS
Input 3-level
Input
Frequency Select: This input must be set according to the nominal frequency (fNOM). See
Table 1.
FBDS[0:1]
DIS[1:2]
Input 3-level
Input
Feedback Divider Function Select. These inputs determine the function of the QFA0 and
QFA1 outputs. See Table 2.
Input LVTTL
Output Disable: Each input controls the state of the respective output bank. When HIGH,
the output bank is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is deter-
mined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled. See Table 3.
These inputs each have an internal pull-down.
LOCK
Output LVTTL
PLL Lock Indicator: When HIGH, this output indicates the internal PLL is locked to the
reference signal. When LOW, the PLL is attempting to acquire lock.
Output_Mode
Input 3-Level Output Mode: This pindetermines the clock outputs’disable state. When this input is HIGH,
Input
the clock outputs will disable to high-impedance (HI-Z). When this input is LOW, the clock
outputs will disable to “HOLD-OFF” mode. When in MID, the device will enter factory test
mode.
QFA[0:1]
Output LVTTL
Clock Feedback Output: This pair of clock outputs is intended to be connected to the FB
input. These outputs have numerous divide options. The function is determined by the
setting of the FBDS[0:1] pins.
[1:2]Q[A:B][0:1] Output LVTTL
Clock Output.
VCCN
VCCQ
GND
PWR
PWR
PWR
Output Buffer Power: Power supply for each output pair.
Internal Power: Power supply for the internal circuitry.
Device Ground.
VCO, Control Logic, and Divide Generator
Block Diagram Description
Phase Frequency Detector and Filter
The VCO accepts analog control inputs from the PLL filter
block. The FS control pin setting determines the nominal
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+ or REFB–) and the FB input (FBKA).
Correction information is then generated to control the
frequency of the Voltage Controlled Oscillator (VCO). These
two blocks, along with the VCO, form a Phase-Locked Loop
(PLL) that tracks the incoming REF signal.
operational frequency range of the divide by one output (fNOM
)
of the device. fNOM is directly related to the VCO frequency.
There are two versions of the RoboClockII Junior, a low-speed
device (CY7B9930V) where fNOM ranges from 12 MHz to 100
MHz, and a high-speed device (CY7B9940V) which ranges
from 24 MHz to 200 MHz. The FS setting for each device is
shown in Table 1. The fNOM frequency is seen on
“divide-by-one” outputs.
The RoboClockII Junior has a flexible REF input scheme.
These inputs allow the use of either differential LVPECL or
single-ended LVTTL inputs. To configure as single-ended
LVTTL inputs, the complementary pin must be left open (inter-
nally pulled to 1.5V), then the other input pin can be used as
a LVTTL input. The REF inputs are also tolerant to hot
insertion.
Table 1. Frequency Range Select
CY7B9930V
fNOM (MHz)
CY7B9940V
fNOM (MHz)
FS[2]
LOW
Min.
Max.
26
Min.
Max.
52
The REF inputs can be changed dynamically. When changing
from one reference input to the other reference input of the
same frequency, the PLL is optimized to ensure that the clock
outputs period will not be less than the calculated system
budget (tMIN = tREF (nominal reference clock period) – tCCJ
(cycle-to-cycle jitter) – tPDEV (max. period deviation)) while
12
24
48
24
48
96
MID
52
100
200[3]
HIGH
100
reacquiring lock.
Note:
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO. fNOM always appears on an output when the output is operating
in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided.
3. The maximum output frequency is 200 MHz.
Document #: 38-07271 Rev. *B
Page 2 of 9
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RoboClockII™ Junior
CY7B9930V
CY7B9940V
Divide Matrix
Lock Detect Output Description
The Divide Matrix is comprised of three independent banks:
two banks of clock outputs and one bank for feedback. Each
clock output bank has two pairs of low-skew, high-fanout
output buffers ([1:2]Q[A:B][0:1]), and an output disable
(DIS[1:2]).
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit (tPD).
The feedback bank has one pair of low-skew, high-fanout
output buffers (QFA[0:1]). One of these outputs may connect
to the selected feedback input (FBKA+). This feedback bank
also has two divider function selects FBDS[0:1].
When in the locked state, after four or more consecutive
feedback clock cycles with phase-errors, the LOCK output will
be forced LOW to indicate out-of-lock state.
The divide capabilities for each bank are shown in Table 2.
Table 2. Output Divider Function
Function
When in the out-of-lock state, 32 consecutive phase-errorless
feedback clock cycles are required to allow the LOCK output
to indicate lock condition (LOCK = HIGH).
If the feedback clock is removed after LOCK has gone HIGH,
a “Watchdog” circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW.
This time out period is based upon a divided down reference
clock.
Selects
Output Divider Function
Feedback
Bank
FBDS1
FBDS0
LOW
MID
Bank1
/1
Bank2
/1
LOW
LOW
LOW
MID
/1
/2
This assumes that there is activity on the selected REF input.
If there is no activity on the selected REF input then the LOCK
detect pin may not accurately reflect the state of the internal
PLL.
/1
/1
HIGH
LOW
MID
/1
/1
/3
/1
/1
/4
MID
/1
/1
/5
Factory Test Mode Description
MID
HIGH
LOW
MID
/1
/1
/6
The device will enter factory test mode when the
OUTPUT_MODE is driven to MID. In factory test mode, the
device will operate with its internal PLL disconnected; input
level supplied to the reference input will be used in place of the
PLL output. In TEST mode the selected FB input must be tied
LOW. All functions of the device are still operational in factory
test mode except the internal PLL and output bank disables.
The OUTPUT_MODE input is designed to be a static input.
Dynamically toggling this input from LOW to HIGH may tempo-
rarily cause the device to go into factory test mode (when
passing through the MID state).
HIGH
HIGH
HIGH
/1
/1
/8
/1
/1
/10
/12
HIGH
/1
/1
Output Disable Description
The outputs of Bank 1 and Bank 2 can be independently put
into a HOLD-OFF or high-impedance state. The combination
of the Output_Mode and DIS[1:2] inputs determines the clock
outputs’ state for each bank. When the DIS[1:2] is LOW, the
outputs of the corresponding bank will be enabled. When the
DIS[1:2] is HIGH, the outputs for that bank will be disabled to
a high-impedance (HI-Z) or HOLD-OFF state depending on
the Output_Mode input. Table 3 defines the disabled output
functions.
Factory Test Reset
When in factory test mode (OUTPUT_MODE = MID), the
device can be reset to a deterministic state by driving the DIS2
input HIGH. When the DIS2 input is driven HIGH in factory test
mode, all clock outputs will go to HI-Z; after the selected
reference clock pin has 5 positive transitions, all the internal
finite state machines (FSM) will be set to a deterministic state.
The deterministic state of the state machines will depend on
the configurations of the divide selects and frequency select
input. All clock outputs will stay in high-impedance mode and
all FSMs will stay in the deterministic state until DIS2 is
deasserted. When DIS2 is deasserted (with OUTPUT_MODE
still at MID), the device will re-enter factory test mode.
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a
maximum of six output clock cycles from the time when the
disable input (DIS[1:2]) is HIGH. When disabled to the
HOLD-OFF state, outputs are driven to a logic LOW state on
its falling edge. This ensures the output clocks are stopped
without glitch. When a bank of outputs is disabled to HI-Z state,
the respective bank of outputs will go HI-Z immediately.
Table 3. DIS[1:2] Pin Functionality
OUTPUT_MODE
HIGH/LOW
HIGH
DIS[1:2]/FBDIS
Output Mode
ENABLED
LOW
HIGH
HIGH
X
HI-Z
LOW
HOLD-OFF
FACTORY TEST
MID
Document #: 38-07271 Rev. *B
Page 3 of 9
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RoboClockII™ Junior
CY7B9930V
CY7B9940V
Static Discharge Voltage............................................ >2000V
(per MIL-STD-883, Method 3015)
Absolute Maximum Conditions
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... >±200mA
Operating Range
Storage Temperature .....................................−40°C to +125°C
Ambient Temperature with Power Applied..−40°C to +125°C
Supply Voltage to Ground Potential .................−0.5V to +4.6V
DC Input Voltage ..........................................−0.3V to VCC+0.5V
Output Current into Outputs (LOW) .............................40 mA
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
3.3V ±10%
3.3V ±10%
–40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
VOH
VOL
IOZ
LVTTL HIGH Voltage QFA[0:1], [1:2]Q[A:B][0:1]
VCC = Min., IOH = –30 mA
IOH = –2 mA, VCC = Min.
VCC = Min., IOL= 30 mA
2.4
2.4
–
–
V
V
LOCK
LVTTL LOW Voltage QFA[0:1], [1:2]Q[A:B][0:1]
LOCK
–
0.5
0.5
100
V
I
OL= 2 mA, VCC = Min.
–
V
High-Impedance State Leakage Current
–100
µA
LVTTL Compatible Input Pins (FBKA, REFA±, REFB±, REFSEL, DIS[1:2])
VIH
LVTTL Input HIGH
LVTTL Input LOW
LVTTL VIN >VCC
FBKA+, REF[A:B]±
Min. < VCC < Max.
2.0
2.0
VCC+0.3
VCC+0.3
V
V
REFSEL,
DIS[1:2]
VIL
FBKA+, REF[A:B]±
Min. < VCC < Max.
–0.3
–0.3
0.8
0.8
V
V
REFSEL,
DIS[1:2]
II
FBKA+, REF[A:B]±
FBKA+, REF[A:B]±
VCC = GND, VIN = 3.63V
VCC = Max., VIN = VCC
VIN = VCC
–
–
–
100
500
500
µA
µA
µA
IlH
LVTTL Input HIGH
Current
REFSEL,
DIS[1:2]
IlL
LVTTL Input LOW
Current
FBKA+, REF[A:B]±
VCC = Max., VIN = GND
–500
–500
–
–
µA
µA
REFSEL,
DIS[1:2]
3-Level Input Pins (FBDS[0:1], FS, Output_Mode)
VIHH
VIMM
VILL
IIHH
Three Level Input HIGH[4]
Three Level Input MID[4]
Three Level Input LOW[4]
Min. < VCC < Max.
Min. < VCC < Max.
Min. < VCC < Max.
VIN = VCC
0.87*VCC
–
V
V
0.47*VCC 0.53*VCC
0.13*VCC
V
Three Level Input
HIGH Current
3-level input pins
–
200
50
–
µA
IIMM
IILL
Three Level Input
MID Current
3-level input pins
3-level input pins
VIN = VCC/2
VIN = GND
–50
–200
µA
µA
Three Level Input
LOW Current
LVDIFF Input Pins (REF[A:B]±)
VDIFF
VIHHP
VILLP
Input Differential Voltage
Highest Input HIGH Voltage
400
1.0
VCC
VCC
mV
V
Lowest Input LOW Voltage
GND
0.8
VCC – 0.4
VCC
V
VCOM
Common Mode Range (crossing voltage)
V
Note:
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK
time before all data sheet limits are achieved.
Document #: 38-07271 Rev. *B
Page 4 of 9
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RoboClockII™ Junior
CY7B9930V
CY7B9940V
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
Operating Current
[5]
ICCI
Internal Operating
Current
CY7B9930V
CY7B9940V
CY7B9930V
CY7B9940V
VCC = Max., fMAX
–
–
–
–
200
200
40
mA
mA
mA
mA
ICCN
Output Current
VCC = Max.,
CLOAD = 25 pF,
R
Dissipation/Pair[6]
50
LOAD = 50Ω at VCC/2,
fMAX
Capacitance
Parameter
Description
Test Conditions
Min.
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
–
5
pF
Switching Characteristics Over the Operating Range[7, 8, 9, 10, 11]
CY7B9930/40V-2 CY7B9930/40V-5
Parameter
fin
Description
Min.
12
24
12
24
–
Max.
100
200
100
200
185
200
250
Min.
12
24
12
24
–
Max.
100
200
100
200
185
250
550
Unit
MHz
MHz
MHz
MHz
ps
Clock Input Frequency
Clock Output Frequency
CY7B9930V
CY7B9940V
CY7B9930V
CY7B9940V
fout
tSKEWPR
tSKEWBNK
tSKEW0
Matched-Pair Skew[12, 13]
Intrabank Skew[12, 13]
–
–
ps
Output-Output Skew (same frequency and phase, rise to rise, fall
to fall)[12, 13]
–
–
ps
tSKEW1
tCCJ1-3
Output-Output Skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall)[12, 13]
–
–
250
150
–
–
650
150
ps
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
ps
Peak-
Peak
tCCJ4-12
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
–
100
–
100
ps
Peak-
Peak
tPD
Propagation Delay, REF to FB Rise
Propagation Delay difference between two devices[14]
REF input (Pulse Width HIGH)[15]
REF input (Pulse Width LOW)[15]
Output Rise/Fall Time[16]
–250
–
250
200
–
–500
500
200
–
ps
ps
ns
ns
ns
ms
µs
tPDDELTA
tREFpwh
tREFpwl
tr/tf
2.0
2.0
0.15
–
2.0
2.0
0.15
–
–
–
2.0
10
2.0
10
tLOCK
PLL Lock Time From Power-up
tRELOCK1
PLL Re-Lock Time (from same frequency, different phase) with
Stable Power Supply
–
500
–
500
Notes:
5.
ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B9930V, fNOM = 200 MHz for
CY7B9940V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
6. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum
load of 25 pF terminated to 50Ω at VCC/2.
7. This is for non-three level inputs.
8. Assumes 25 pF Max. Load Capacitance up to 185 Mhz. At 200 MHz the max load is 10 pF.
9. Both outputs of pair must be terminated, even if only one is being used.
10. Each package must be properly decoupled.
11. AC parameters are measured at 1.5V, unless otherwise indicated.
12. Test Load CL= 25 pF, terminated to VCC/2 with 50Ω.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when
all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
15. Tested initially and after any design or process changes that may affect these parameters.
16. Rise and fall times are measured between 2.0V and 0.8V.
Document #: 38-07271 Rev. *B
Page 5 of 9
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RoboClockII™ Junior
CY7B9930V
CY7B9940V
Switching Characteristics Over the Operating Range[7, 8, 9, 10, 11] (continued)
CY7B9930/40V-2 CY7B9930/40V-5
Parameter
Description
Min.
Max.
Min.
Max.
Unit
tRELOCK2
PLL Re-Lock Time (from different frequency, different phase) with
Stable Power Supply[17]
–
1000
–
1000
µs
tODCV
tPWH
tPWL
tPDEV
tOAZ
Output duty cycle deviation from 50%[11]
Output HIGH time deviation from 50%[18]
Output LOW time deviation from 50%[18]
Period deviation when changing from reference to reference[19]
DIS[1:2] HIGH to output high-impedance from ACTIVE[12, 20]
–1.0
–
1.0
1.5
–1.0
–
1.0
1.5
ns
ns
ns
UI
ns
ns
–
2.0
–
2.0
–
0.025
10
–
0.025
10
1.0
0.5
1.0
0.5
tOZA
DIS[1:2] LOW to output ACTIVE from output is high-impedance[20,
14
14
21]
AC Test Loads and Waveform[22]
3.3V
R1
For LOCK output only
For all other outputs
OUTPUT
R1 = 910Ω
R2 = 910
R1 = 100Ω
R2 = 100Ω
C
L
Ω
R2
C < 30 pF
L
C < 25 pF up to 185 MHz
L
10 pF from 185 to 200 MHz
(Includes fixture and
probe capacitance)
(a) LVTTL AC Test Load
3.3V
GND
2.0V
0.8V
2.0V
0.8V
< 1 ns
< 1 ns
(b)TTL Input Test Waveform
Notes:
17. NOM must be within the frequency range defined by the same FS state.
f
18. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
19. UI = Unit Interval. Examples: 1 UI is a full period. 0.1 UI is 10% of period.
20. Measured at 0.5V deviation from starting voltage.
21. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 18 MHz, 10 pF from 185 to 200 MHz.
22. These figures are for illustration only. The actual ATE loads may vary.
Document #: 38-07271 Rev. *B
Page 6 of 9
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RoboClockII™ Junior
CY7B9930V
CY7B9940V
AC Timing Diagrams[11]
t
REFpwl
QFA0 or
t
REFpwh
[1:4]Q[A:B]0
REF
t
t
SKEWPR
SKEWPR
t
t
PWH
t
PWL
PD
QFA1 or
2.0V
[1:4]Q[A:B]1
FB
Q
0.8V
t
CCJ1-3,4-12
[1:4]QA[0:1]
t
t
SKEWBNK
SKEWBNK
[1:4]QB[0:1]
REF TO DEVICE 1 and 2
t
ODCV
t
ODCV
t
PD
Q
FB DEVICE1
FB DEVICE2
t
SKEW0,1
t
SKEW0,1
t
PDELTA
t
PDELTA
Other Q
Ordering Information
Propagation
Delay (ps)
Max. Speed
(MHz)
100
100
200
200
100
200
100
200
Ordering Code
CY7B9930V-5AC
CY7B9930V-5AI
CY7B9940V-5AC
CY7B9940V-5AI
CY7B9930V-2AC
CY7B9940V-2AC
CY7B9930V-2AI
CY7B9940V-2AI
Package Name
Package Type
Operating Range
500
500
500
500
250
250
250
250
A44
A44
A44
A44
A44
A44
A44
A44
44-Lead Thin Quad Flat Pack Commercial
44-Lead Thin Quad Flat Pack Industrial
44-Lead Thin Quad Flat Pack Commercial
44-Lead Thin Quad Flat Pack Industrial
44-Lead Thin Quad Flat Pack
Commercial
44-Lead Thin Quad Flat Pack
44-Lead Thin Quad Flat Pack
Industrial
44-Lead Thin Quad Flat Pack
Document #: 38-07271 Rev. *B
Page 7 of 9
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RoboClockII™ Junior
CY7B9930V
CY7B9940V
Package Diagrams
44-Lead Thin Plastic Quad Flat Pack A44
51-85064-*B
RoboClockII is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-07271 Rev. *B
Page 8 of 9
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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RoboClockII™ Junior
CY7B9930V
CY7B9940V
Document History Page
Document Title: CY7B9930V/CY7B9940V RoboClockII™ Junior High-Speed Multi-Frequency PLL Clock Buffer
Document Number: 38-07271
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Change from Spec number: 38-01141
110536
115109
128463
12/02/01
7/03/02
7/29/03
SZV
HWT
RGL
*A
Add 44TQFP package for both CY7B9930/40V – Industrial Operating Range
*B
Added clock input frequency (fin) specifications in the switching character-
istics table.
Added Min. values for the clock output frequency (fout) in the switching
characteristics table.
Document #: 38-07271 Rev. *B
Page 9 of 9
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相关型号：
CY7B9940V-2ACT
PLL Based Clock Driver, 7B Series, 8 True Output(s), 0 Inverted Output(s), PQFP44, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-44
CYPRESS
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