CY7B9950AC [CYPRESS]
2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer; 2.5 / 3.3V ， 200MHz的高速多相位锁相环时钟缓冲器
| 型号： | CY7B9950AC |
| 厂家： | 
CYPRESS |
| 描述： | 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer |
| 文件： | 总9页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RoboClock
CY7B9950
2.5/3.3V, 200-MHz High-Speed Multi-Phase
PLL Clock Buffer
Features
Description
• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• Output-output skew < 100 ps
The CY7B9950 RoboClock is a low-voltage, low-power,
eight-output, 200-MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance computer and communication systems.
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature allows the user to
skew the outputs to lead or lag the reference clock. Any one
of the outputs can be connected to feedback input to achieve
different reference frequency multiplication and divide ratios
and zero input-output delay.
• Cycle-cycle jitter < 100 ps
• ± 2% max output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
• Eight LVTTL outputs driving 50Ω terminated lines
• LVCMOS/LVTTL over-voltage-tolerant reference input
• Phase adjustments in 625-/1250-ps steps up to +7.5 ns
• 2x, 4x multiply and (1/2)x, (1/4)x divide ratios
• Spread-Spectrum-compatible
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin
controls the synchronization of the output signals to either the
rising or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA(3.3V).
• Industrial temp. range: –40°C to +85°C
• 32-pin TQFP package
Pin Configuration
Block Diagram
FS
TEST PE/HD
VDDQ1
3
3
3
REF
FB
PLL
3F1
1
2
3
4
5
6
7
8
24 1F1
23 1F0
4F0
4F1
1Q0
1Q1
3
3
Phase
Select
1F1:0
22
21
20
19
18
17
sOE#
VDDQ1
1Q0
PE/HD
VDDQ4
CY7B9950
4Q1
4Q0
VSS
1Q1
2Q0
2Q1
3
3
Phase
Select
VSS
VSS
2F1:0
3F1:0
4F1:0
3Q0
3Q1
Phase
Select
and /K
3
3
VDDQ3
4Q0
Phase
Select
and /M
3
3
4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation
Document #: 38-07338 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 4, 2003
RoboClock
CY7B9950
Pin Description
Pin
Name
I/O[1]
Type
Description
REF
I
LVTTL/LVCMOS Reference Clock Input.
29
13
27
FB
I
I
LVTTL
Feedback Input.
TEST
Three-level
When MID or HIGH, Disables Phase-locked Loop (PLL) (except for condi-
tions of note 3). REF goes to outputs of Bank 1 and Bank 2. REF goes to
outputs of Bank 3 and Bank 4 through output dividers K and M. Set LOW for
normal operation.
22
4
sOE#
I, PD
Two-level
Three-level
Three-level
SynchronousOutput Enable. WhenHIGH, it stopsclock outputs (except2Q0
and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level
and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual
banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
PE/HD I, PU
Selects Positive or Negative Edge Control and High or Low output drive
strength. When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock, respectively. When at MID level,
the output drive strength is increased and the outputs synchronize with the
positive edge of the reference clock (see Table 6).
24, 23, 26, nF[1:0]
I
Select frequency and phase of the outputs (see Tables 1, 2, 3, 4, and 5).
25, 1, 32, 3,
2
31
FS
I
Three-level
LVTTL
Selects VCO operating frequency range (see Table 4).
Four banks of two outputs (see Tables 1, 2, and 3).
19, 20, 15, nQ[1:0]
16, 10, 11,
O
6, 7
[2]
[2]
[2]
21
VDDQ1
VDDQ3
VDDQ4
PWR
PWR
PWR
Power
Power
Power
Power supply for Bank 1 and Bank 2 output buffers (see Table 7 for supply
level constraints).
12
Power supply for Bank 3 output buffers (see Table 7 for supply level
constraints).
5
Power supply for Bank 4 output buffers (see Table 7 for supply level
constraints).
[2]
14,30
VDD
VSS
PWR
PWR
Power
Power
Power supply for internal circuitry (see Table 7 for supply level constraints).
8,9,17,18,
28
Ground.
The three-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B9950 PLL operating frequency range that
Device Configuration
The outputs of the CY7B9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 1 and Table 2, respectively.
corresponds to each FS level is given in Table 3.
Table 3. Frequency Range Select
FS
L
PLL Frequency Range
24 to 50 MHz
Table 1. Output Divider Settings — Bank 3
3F[1:0]
LL
K — Bank3 Output Divider
M
H
48 to 100 MHz
2
4
1
96 to 200 MHz
HH
Other[4]
Selectable output skew is in discrete increments of time unit
(tU).The value of tU is determined by the FS setting and the
maximum nominal frequency. The equation to be used to
determine the tU value is as follows: tU = 1 / (fNOM x MF)
Table 2. Output Divider Settings — Bank 4
4F[1:0]
LL
Other[4]
M — Bank4 Output Divider
where MF is a multiplication factor, which is determined by the
FS setting as indicated in Table 4.
2
1
Notes:
1. “PD” indicates an internal pull-down and “PU” indicates an internal pull-up. “3” indicates a three-level input buffer
2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4. These states are used to program the phase of the respective banks (see Table 5).
Document #: 38-07338 Rev. *B
Page 2 of 9
RoboClock
CY7B9950
Table 4. MF Calculation
FS
L
MF
32
16
8
f
NOM at which tU is 1.0 ns(MHz)
31.25
62.5
125
M
H
Table 5. Output Skew Settings
nF[1:0]
LL[5]
LM
Skew (1Q[0:1],2Q[0:1])
Skew (3Q[0:1])
Divide By 2
–6tU
Skew (4Q[0:1])
Divide By 2
v6tU
–4tU
–3tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
v2tU
MM
MH
HL
Zero Skew
+1tU
Zero Skew
+2tU
Zero Skew
+2tU
+2tU
+4tU
+4tU
HM
HH
+3tU
+6tU
+6tU
Inverted[6]
+4tU
Divide By 4
In addition to determining whether the outputs synchronize to
the rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as
indicated in Table 6.
Table 7. Power Supply Constraints
[8]
[8]
[8]
VDD
3.3V 3.3V or 2.5V
2.5V 2.5V
VDDQ1
VDDQ3
VDDQ4
3.3V or 2.5V
2.5V
3.3V or 2.5V
2.5V
The CY7B9950 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain
both 3.3V and 2.5V output signals from one device. The core
power supply (VDD) must be set a level that is equal or higher
than on any one of the output power supplies.
Governing Agencies
The following agencies provide specifications that apply to the
CY7B9950. The agency name and relevant specification is
listed below.
Table 6. PE/HD Settings
PE/HD
Synchronization Output Drive Strength[7]
Table 8.
L
M
H
Negative
Positive
Positive
Low Drive
High Drive
Low Drive
Agency Name
Specification
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
JEDEC
IEEE
UL-194_V0
MIL
1596.3 (Jitter Specs)
94 (Moisture Grading)
883E Method 1012.1 (Therma Theta JC)
Notes:
5. LL disables outputs if TEST = MID and sOE# = HIGH.
6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW.
7. Please refer to “DC Parameters” section for IOH/IOL specifications.
8. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V
and VDDQ4 = 2.5V.
Document #: 38-07338 Rev. *B
Page 3 of 9
RoboClock
CY7B9950
Absolute Maximum Conditions
Parameter
VDD
Description
Operating Voltage
Condition
Functional @ 2.5V ± 5%
Functional @ 3.3V ± 10%
Relative to VSS
Min.
2.375
2.97
VSS – 0.3
–
Max.
2.625
3.63
–
Unit
V
VDD
Operating Voltage
V
VIN(MIN)
VIN(MAX)
TS
Input Voltage
V
Input Voltage
Relative to VDD
VDD + 0.3
+150
+85
V
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Non-functional
–65
–40
–
°C
°C
°C
°C/W
°C/W
V
TA
Functional
TJ
Functional
155
ØJC
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
–
42
ØJA
–
105
ESDHBM
UL-94
MSL
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
–
Flammability Rating
Moisture Sensitivity Level
Failure in Time
@1/8 in.
V–0
1
FIT
Manufacturing Testing
10
ppm
DC Electrical Specifications @ 2.5V
Parameter
Description
2.5 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
Conditions
Min.
Max.
Unit
VDD
VIL
2.5V ± 5%
2.375
–
2.625
0.7
–
V
V
REF, FB and sOE# Inputs
VIH
1.7
V
[9]
VIHH
3-Level Inputs
VDD – 0.4
–
V
(TEST, FS, nF[1:0], PE/HD) (These pinsarenormally
wired to VDD,GND or unconnected.)
[9]
VIMM
VDD/2 – 0.2 VDD/2 + 0.2
V
[9]
VILL
Input LOW Voltage
Input Leakage Current
–
–5
–
0.4
5
V
IIL
I3
VIN = VDD/GND,VDD = max. (REF and FB inputs)
µA
µA
µA
µA
µA
µA
V
3-Level Input DC Current HIGH, VIN = VDD
MID, VIN = VDD/2
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV, PE/HD)
200
50
–
–50
–200
–25
–
LOW, VIN = VSS
IPU
IPD
VOL
Input Pull-up Current
Input Pull-down Current
Output LOW Voltage
VIN = VSS, VDD = max.
–
VIN = VDD, VDD = max., (sOE#)
100
0.4
0.4
–
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
IOL = 20 mA (PE/HD = MID),(nQ[0:1])
IOH = –12 mA (PE/HD = L/H),(nQ[0:1])
IOH = –20 mA (PE/HD = MID),(nQ[0:1])
–
–
V
VOH
Output HIGH Voltage
2.0
2.0
V
–
V
IDDQ
IDD
V
DD= max., TEST =MID, REF= LOW, sOE# =LOW,
Quiescent Supply Current
–
2
mA
outputs not loaded
Dynamic Supply Current @ 100 MHz
Input Pin Capacitance
150
4
mA
pF
CIN
Note:
9. These inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
Document #: 38-07338 Rev. *B
Page 4 of 9
RoboClock
CY7B9950
DC Specifications @ 3.3V
Parameter
Description
3.3 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
Condition
Min.
2.97
Max.
3.63
0.8
–
Unit
V
VDD
VIL
3.3V ± 10%
REF, FB and sOE# Inputs
–
V
VIH
2.0
V
[9]
VIHH
3-Level Inputs
VDD – 0.6
–
V
(TEST, FS, nF[1:0], PE/HD) (These pins are normally
wired to VDD,GND or unconected.)
[9]
VIMM
VDD/2 – 0.3 VDD/2 + 0.3
V
[9]
VILL
Input LOW Voltage
Input Leakage Current
–
–5
0.6
5
V
IIL
I3
VIN = VDD/GND,VDD = max. (REF and FB inputs)
µA
µA
µA
µA
µA
µA
V
3-Level Input DC Current HIGH, VIN = VDD
MID, VIN = VDD/2
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV, PE/HD)
–
200
50
–
–50
–200
–100
–
LOW, VIN = VSS
IPU
IPD
VOL
Input Pull-up Current
VIN = VSS, VDD = max.
–
Input Pull-down Current VIN = VDD, VDD = max., (sOE#)
100
0.4
0.4
–
Output LOW Voltage
Output HIGH Voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
IOL = 24 mA (PE/HD = MID),(nQ[0:1])
IOH = –12 mA (PE/HD = L/H),(nQ[0:1])
–
–
V
VOH
IDDQ
2.4
2.4
V
I
OH = –24 mA (PE/HD = MID),(nQ[0:1])
–
V
VDD = max., TEST = MID, REF = LOW, sOE# = LOW,
outputs not loaded
Quiescent Supply Current
–
2
mA
IDD
CIN
Dynamic Supply Current @ 100 MHz
Input Pin Capacitance
230
4
mA
pF
AC Test Loads and Waveforms
VDDQ
Output
150Ω
20pF
Output
20pF
150Ω
For Lock Output
For All Other Outputs
tORISE
tOFALL
tORISE
tOFALL
tPWH
tPWH
1.7V
2.0V
VTH =1.25V
VTH =1.5V
tPWL
tPWL
0.7V
0.8V
2.5V LVTTL OUTPUT WAVEFORM
1 ns
3.3V LVTTL OUTPUT WAVEFORM
1 ns
≤
≤
≤
1 ns
1 ns
≤
2.5V
1.7V
3.0V
2.0V
VTH=1.25V
VTH =1.5V
0.7V
0V
0.8V
0V
2.5V LVTTL INPUT TEST WAVEFORM
Page 5 of 9
3.3V LVTTL INPUT TEST WAVEFORM
Document #: 38-07338 Rev. *B
RoboClock
CY7B9950
AC Input Specifications
Parameter
TR,TF
Description
Condition
Min.
–
Max.
10
Unit
ns/V
ns
Input Rise/Fall Time
Input Clock Pulse
0.8V – 2.0V
TPWC
HIGH or LOW
2
–
TDCIN
Input Duty Cycle
10
6
90
%
FREF
Reference Input Frequency
FS = LOW
FS = MID
FS = HIGH
50
12
24
100
200
MHz
Switching Characteristics
Parameter
FOR
Description
Condition
Min.
6
Max. Unit
Output Frequency Range
VCO Lock Range
200
400
3.5
MHz
MHz
MHz
VCOLR
200
0.25
VCOLBW
tSKEWPR
VCO Loop Bandwidth
Matched-Pair Skew[10]
Skew between the earliest and the latest output transitions within
the same bank.
–
–
100
200
ps
ps
tSKEW0
tSKEW1
Output-Output Skew[10] Skew between the earliest and the latest output transitions
among all outputs at 0tU.
Skew between the earliest and the latest output transitions
among all outputs for which the same phase delay has been
selected.
–
200
ps
tSKEW2
tSKEW3
tSKEW4
Skew between the nominal output rising edge to the inverted
output falling edge
Output-Output Skew[10] Skew between non-inverted outputs running at different
frequencies
–
–
500
500
ps
ps
Skew between nominal to inverted outputs running at different
frequencies
–
–
–
500
650
750
ps
ps
ps
tSKEW5
tPART
Skew between nominal outputs at different power supply levels
Part-Part Skew
Skew between the outputs of any two devices under identical
settings and conditions (VDDQ,VDD,temp, air flow, frequency, etc.)
tPD0
Ref-FB Propagation
Delay[11]
–250 +250
ps
%
tODCV
Output Duty Cycle
Fout < 100 MHz, measured at VDD/2
Fout > 100 MHz, measured at VDD/2
48
45
52
55
tPWH
tPWL
Output High Time
Deviation from 50%
Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V.
Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V.
–
–
1.5
2.0
ns
ns
Output Low Time
Deviation from 50%
tR/tF
tLOCK
tCCJ
Output Rise/Fall Time
PLL lock time[12,13]
Cycle-Cycle Jitter
Measured at 0.8V –2.0V for VDD = 3.3V and 0.7V–1.7V for VDD =2.5V 0.15
1.5
0.5
ns
ms
ps
–
Divide by 1 output frequency, FS = L, FB = divide by 1,2,4
Divide by 1 output frequency, FS = M/H, FB = divide by 1,2,4
–
–
100
150
ps
Notes:
10. Test load = 20 pF, terminated to VCC/2. All outputs are equally loaded.
11. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5 ns between 0.8V – 2.0V.
12. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
13. Lock detector circuit may be unreliable for input frequencies lower than 4 MHz, or for input signals which contain significant jitter.
Document #: 38-07338 Rev. *B
Page 6 of 9
RoboClock
CY7B9950
AC Timing Definitions
tREF
tPWL
tPWH
REF
tPD
t0DCV
t0DCV
FB
tCCJ1-12
Q
tSKEWPR
tSKEWPR
tSKEW0,1
tSKEW0,1
OTHER Q
tSKEW1
tSKEW1
INVERTED Q
tSKEW3
tSKEW3
tSKEW3
REF DIVIDED BY 2
tSKEW1,3,4
tSKEW1,3,4
REF DIVIDED BY 4
Ordering Information
Part Number
CY7B9950AC
Package Type
Product Flow
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial,–40° to 85°C
Industrial,–40° to 85°C
32 TQFP
CY7B9950ACT
CY7B9950AI
32 TQFP – Tape and Reel
32 TQFP
CY7B9950AIT
32 TQFP – Tape and Reel
Document #: 38-07338 Rev. *B
Page 7 of 9
RoboClock
CY7B9950
Package Drawing and Dimension
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-07338 Rev. *B
Page 8 of 9
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
RoboClock
CY7B9950
Document History Page
Document Title: RoboClock CY7B9950 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
Document Number: 38-07338
Orig. of
Change
Rev.
ECN No. Issue Date
Description of Change
**
121663
122548
11/25/02
12/12/02
RGL
New Data Sheet
*A
RGL
Removed the PD#/DIV and DS[1:0] pins in VIHH,VIMM and VILL for both
2.5V and 3.3V DC Electrical Specs tables
*B
124646
03/05/03
RGL
Corrected the description of Pin 27(TEST) in the Pin Description table
Corrected the description of Pin 12 (VDDQ) in the Pin Description table
Corrected the Min and Max values of VDD from 2.25/2.75 to 2.375/2.625
Volts in the Absolute Maximum Conditions table
Document #: 38-07338 Rev. *B
Page 9 of 9
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