CY7B9950_07 [CYPRESS]
2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer; 2.5 / 3.3V , 200MHz的高速多相位锁相环时钟缓冲器型号: | CY7B9950_07 |
厂家: | CYPRESS |
描述: | 2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer |
文件: | 总12页 (文件大小:331K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
RoboClock®, CY7B9950
2.5/3.3V, 200 MHz High-Speed
Multi-Phase PLL Clock Buffer
Features
■ 2.5V or 3.3V operation
Description
The CY7B9950 RoboClock® is a low voltage, low power,
eight-output, 200 MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high performance computer and communication systems.
■ Split output bank power supplies
■ Output frequency range: 6 MHz to 200 MHz
■ 50 ps typical matched-pair Output-output skew
■ 50 ps typical Cycle-cycle jitter
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature allows the user to
skew the outputs to lead or lag the reference clock. Any one
of the outputs can be connected to the feedback input to
achieve different reference frequency multiplications, and
divide ratios and zero input-output delay.
■ 49.5/50.5% typical output duty cycle
■ Selectable output drive strength
■ Selectable positive or negative edge synchronization
■ Eight LVTTL outputs driving 50 Ω terminated lines
■ LVCMOS/LVTTL over-voltage-tolerant reference input
■ Phase adjustments in 625-/1250-ps steps up to +7.5 ns
■ 2x, 4x multiply and (1/2)x, (1/4)x divide ratios
■ Spread-Spectrum compatible
The device also features split output bank power supplies,
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin
controls the synchronization of the output signals to either the
rising, or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA(3.3V).
■ Industrial temp. range: –40°C to +85°C
■ 32-pin TQFP package
Logic Block Diagram
FS
TEST PE/HD
VDDQ1
3
3
3
REF
FB
PLL
1Q0
1Q1
3
3
Phase
Select
1F1:0
2Q0
2Q1
3
3
Phase
Select
2F1:0
3F1:0
4F1:0
3Q0
3Q1
Phase
Select
and /K
3
3
VDDQ3
4Q0
Phase
Select
and /M
3
3
4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation
Document #: 38-07338 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 27, 2007
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CY7B9950
Pinouts
Figure 1. Pin Diagram - 32 Pin TQFP package Top view
3F1
1
2
3
4
5
6
7
8
24 1F1
23 1F0
4F0
4F1
22
21
20
19
18
17
sOE#
VDDQ1
1Q0
PE/HD
VDDQ4
CY7B9950
4Q1
4Q0
VSS
1Q1
VSS
VSS
Document #: 38-07338 Rev. *D
Page 2 of 12
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CY7B9950
Table 1. Pin Definitions
Pin
Name IO[1]
Type
Description
29
13
27
REF
FB
I
I
I
LVTTL/LVCMOS Reference Clock Input.
LVTTL
Feedback Input.
TEST
Three-level
When MID or HIGH, disables Phase-locked Loop (PLL)[3]. REF goes to
outputs of Bank 1 and Bank 2. REF also goes to outputs of Bank 3 and Bank
4 through output dividers K and M. Set LOW for normal operation.
22
4
sOE# I, PD
PE/HD I, PU
Two-level
Three-level
Three-level
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0
and 2Q1) in a LOW state (for PE = H or M) – 2Q0, and 2Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level
and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual
banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
Selects Positive or Negative Edge Control and High or Low Output Drive
Strength. When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock, respectively. When at MID level,
the output drive strength is increased and the outputs synchronize with the
positive edge of the reference clock (see Table 7 on page 4).
24, 23, 26,
25, 1, 32, 3,
2
nF[1:0]
I
Select Frequency and Phase of the Outputs (see Table 2, Table 3, Table 4
on page 4, Table 5 on page 4, and Table 6 on page 4).
31
FS
I
Three-level
LVTTL
Selects VCO Operating Frequency Range (see Table 5 on page 4)
Four Banks of Two Outputs (see Table 2, Table 3, and Table 4 on page 4)
19, 20, 15,
16, 10, 11, 6,
7
nQ[1:0]
O
[2]
21
VDDQ1
VDDQ3
VDDQ4
PWR
PWR
PWR
PWR
PWR
Power
Power
Power
Power
Power
Power Supply for Bank 1 and Bank 2 Output Buffers (see Table 8 on page
4 for supply level constraints).
[2]
[2]
12
Power Supply for Bank 3 Output Buffers (see Table 8 on page 4 for supply
level constraints).
5
Power Supply for Bank 4 Output Buffers (see Table 8 on page 4 for supply
level constraints).
[2]
14,30
VDD
Power Supply for Internal Circuitry (see Table 8 on page 4 for supply level
constraints).
8,9,17,18,28
VSS
Ground
Table 3. Output Divider Settings — Bank 4
Device Configuration
4F[1:0]
LL
Other[4]
M — Bank4 Output Divider
The outputs of the CY7B9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 2 and Table 3, respectively.
2
1
The three-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B9950 PLL operating frequency range that cor-
responds to each FS level is given in Table 4 on page 4.
Table 2. Output Divider Settings — Bank 3
3F[1:0]
LL
K — Bank3 Output Divider
2
4
1
HH
Other[4]
Notes
1. “PD” indicates an internal pull-down and “PU” indicates an internal pull-up. “3” indicates a three-level input buffer
2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic are cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4. These states are used to program the phase of the respective banks (see Table 6 on page 4).
Document #: 38-07338 Rev. *D
Page 3 of 12
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CY7B9950
Table 4. Frequency Range Select
the tU value is: tU = 1 / (fNOM x MF), where MF is a multiplication
factor, which is determined by the FS setting as indicated in
Table 5.
FS
L
PLL Frequency Range
Table 5. MF Calculation
24 to 50 MHz
48 to 100 MHz
96 to 200 MHz
M
H
FS
L
MF
32
16
8
fNOM at which tU is 1.0 ns(MHz)
31.25
62.5
125
M
H
The selectable output skew is in discrete increments of time units
(tU).The value of tU is determined by the FS setting and the
maximum nominal frequency. The equation used to determine
Table 6. Output Skew Settings
nF[1:0]
LL[5]
LM
Skew (1Q[0:1],2Q[0:1])
Skew (3Q[0:1])
Divide By 2
–6tU
Skew (4Q[0:1])
Divide By 2
v6tU
–4tU
–3tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
v2tU
MM
MH
HL
Zero Skew
+1tU
Zero Skew
+2tU
Zero Skew
+2tU
+2tU
+4tU
+4tU
HM
HH
+3tU
+6tU
+6tU
Inverted[6]
+4tU
Divide By 4
In addition to determining whether the outputs synchronize to the
rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as indicated
in Table 7.
Governing Agencies
The following agencies provide specifications that apply to the
CY7B9950. The agency name and relevant specification is listed
below.
The CY7B9950 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain both
3.3V and 2.5V output signals from one device. The core power
supply (VDD) must be set a level that is equal or higher than on
any one of the output power supplies.
Table 9. Governing Agencies and Specifications
Agency Name
Specification
JESD 51 (Theta JA)
JEDEC
Table 7. PE/HD Settings
JESD 65 (Skew, Jitter)
PE/HD
Synchronization Output Drive Strength[7]
IEEE
UL-194_V0
MIL
1596.3 (Jitter Specs)
L
M
H
Negative
Positive
Positive
Low Drive
High Drive
Low Drive
94 (Moisture Grading)
883E Method 1012.1 (Therma Theta JC)
Table 8. Power Supply Constraints
[8]
[8]
[8]
VDD
VDDQ1
VDDQ3
VDDQ4
3.3V 3.3V or 2.5V
3.3V or 2.5V
2.5V
3.3V or 2.5V
2.5V
2.5V
2.5V
Notes:
5. LL disables outputs if TEST = MID and sOE# = HIGH.
6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID and sOE# disables them LOW when PE/HD = LOW.
7. Please refer to “DC Parameters” section for I /I specifications.
OH OL
8. V
V
must not be set at a level higher than that of V . They can be set at different levels from each other, e.g., V = 3.3V, V
= 3.3V, V
= 2.5V and
DDQ1/3/4
DDQ4
DD
DD
DDQ1
DDQ3
= 2.5V.
Document #: 38-07338 Rev. *D
Page 4 of 12
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CY7B9950
Absolute Maximum Conditions
Parameter
VDD
Description
Operating Voltage
Condition
Functional @ 2.5V ± 5%
Functional @ 3.3V ± 10%
Relative to VSS
Min
2.375
2.97
VSS – 0.3
–
Max
Unit
V
2.625
3.63
–
VDD
Operating Voltage
V
VIN(MIN)
VIN(MAX)
TS
Input Voltage
V
Input Voltage
Relative to VDD
VDD + 0.3
+150
+85
V
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Non-functional
–65
–40
–
°C
°C
°C
°C/W
°C/W
V
TA
Functional
TJ
Functional
155
ØJC
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
–
42
ØJA
–
105
ESDHBM
UL-94
MSL
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
–
Flammability Rating
Moisture Sensitivity Level
Failure in Time
At 1/8 in.
V–0
1
FIT
Manufacturing Testing
10
ppm
DC Electrical Specifications at 2.5V
Parameter
Description
2.5 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
Condition
Min
2.375
–
Max
2.625
0.7
–
Unit
V
VDD
VIL
2.5V ± 5%
REF, FB and sOE# Inputs
V
VIH
1.7
V
[9]
VIHH
3-Level Inputs
VDD – 0.4
–
V
(TEST, FS, nF[1:0], PE/HD) (These pins
are normally wired to VDD, GND or uncon-
nected.)
[9]
VIMM
VDD/2 – 0.2 VDD/2 + 0.2
V
[9]
VILL
Input LOW Voltage
–
0.4
5
V
IIL
Input Leakage Current
VIN = VDD/GND
,
–5
μA
VDD = max. (REF and FB inputs)
I3
3-Level Input DC Current
HIGH, VIN = VDD 3-Level Inputs
–
–50
–200
–25
–
200
50
–
μA
μA
μA
μA
μA
V
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
MID, VIN = VDD/2
LOW, VIN = VSS
IPU
IPD
VOL
Input Pull-up Current
Input Pull-down Current
Output LOW Voltage
VIN = VSS, VDD = max.
–
VIN = VDD, VDD = max., (sOE#)
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
100
0.4
0.4
–
–
I
OL = 20 mA (PE/HD = MID), (nQ[0:1])
IOH = –12 mA (PE/HD = L/H), (nQ[0:1])
OH = –20 mA (PE/HD = MID), (nQ[0:1])
–
V
VOH
IDDQ
Output HIGH Voltage
2.0
2.0
V
I
–
V
VDD = max., TEST = MID, REF = LOW,
sOE# = LOW, outputs not loaded
Quiescent Supply Current
–
2
mA
IDD
CIN
Dynamic Supply Current
Input Pin Capacitance
At 100 MHz
150
4
mA
pF
Note
9. These inputs are normally wired to V , GND or unconnected. Internal termination resistors bias unconnected inputs to V /2.
DD
DD
Document #: 38-07338 Rev. *D
Page 5 of 12
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CY7B9950
DC Specifications at 3.3V
Parameter
Description
Condition
Min
2.97
Max
Unit
V
VDD
VIL
3.3 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
3.3V ± 10%
3.63
0.8
–
REF, FB and sOE# Inputs
–
V
VIH
2.0
V
[9]
VIHH
3-Level Inputs
VDD – 0.6
–
V
(TEST, FS, nF[1:0], PE/HD) (These pins
are normally wired to VDD,GND or
unconected.)
[9]
VIMM
VDD/2 – 0.3 VDD/2 +
0.3
V
[9]
VILL
Input LOW Voltage
–
0.6
5
V
IIL
Input Leakage Current
VIN = VDD/GND,VDD = max. (REF and FB
inputs)
–5
μA
I3
3-Level Input DC Current
HIGH, VIN = VDD
MID, VIN = VDD/2
LOW, VIN = VSS
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
–
–50
–200
–100
–
200
50
–
μA
μA
μA
μA
μA
V
IPU
IPD
VOL
Input Pull-up Current
Input Pull-down Current
Output LOW Voltage
VIN = VSS, VDD = max.
–
VIN = VDD, VDD = max., (sOE#)
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
IOL = 24 mA (PE/HD = MID), (nQ[0:1])
IOH = –12 mA (PE/HD = L/H), (nQ[0:1])
100
0.4
0.4
–
–
–
V
VOH
IDDQ
Output HIGH Voltage
2.4
2.4
V
I
OH = –24 mA (PE/HD = MID), (nQ[0:1])
–
V
VDD = max., TEST = MID, REF = LOW,
sOE# = LOW, outputs not loaded
Quiescent Supply Current
–
2
mA
IDD
CIN
Dynamic Supply Current
Input Pin Capacitance
At 100 MHz
230
4
mA
pF
Document #: 38-07338 Rev. *D
Page 6 of 12
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CY7B9950
AC Test Loads and Waveforms
Figure 2. AC Test Loads
VDDQ
Output
150Ω
20 pF
Output
20 pF
150Ω
For Lock Output
For All Other Outputs
Figure 3. Output Waveforms
tORISE
tOFALL
tORISE
tOFALL
tPWH
tPWH
1.7V
2.0V
VTH =1.25V
VTH =1.5V
tPWL
tPWL
0.7V
0.8V
2.5V LVTTL OUTPUT WAVEFORM
3.3V LVTTL OUTPUT WAVEFORM
Figure 4. Test Waveforms
1 ns
1 ns
≤
≤
≤
1 ns
1 ns
≤
2.5V
1.7V
3.0V
2.0V
VTH =1.25V
VTH =1.5V
0.7V
0V
0.8V
0V
2.5V LVTTL INPUT TEST WAVEFORM
3.3V LVTTL INPUT TEST WAVEFORM
AC Input Specifications
Parameter
Description
Input Rise/Fall Time
Input Clock Pulse
Input Duty Cycle
Condition
Min
–
Max
10
Unit
ns/V
ns
T ,T
0.8V – 2.0V
R
F
PWC
DCIN
REF
T
T
F
HIGH or LOW
2
–
10
6
90
%
Reference Input
Frequency
FS = LOW
FS = MID
FS = HIGH
50
12
24
100
200
MHz
Document #: 38-07338 Rev. *D
Page 7 of 12
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CY7B9950
Switching Characteristics
Parameter
Description
Condition
Min
Typ
Max
Unit
FOR
Output Frequency
Range
6
–
200
MHz
VCOLR
VCO Lock Range
200
0.25
–
–
–
400
3.5
MHz
MHz
ps
VCOLBW
tSKEWPR
VCO Loop Bandwidth
Matched-Pair Skew[10] Skew between the earliest and the latest output transi-
50
100
tions within the same bank.
tSKEW0
tSKEW1
Output-Output Skew[10] Skew between the earliest and the latest output transi-
tions among all outputs at 0tU.
–
–
100
100
200
200
ps
ps
Skew between the earliest and the latest output transi-
tions among all outputs for which the same phase delay
has been selected.
tSKEW2
tSKEW3
tSKEW4
tSKEW5
tPART
Skew between the nominal output rising edge to the
inverted output falling edge.
–
–
–
–
–
–
–
–
–
–
500
500
500
650
750
ps
ps
ps
ps
ps
Output-Output Skew[10] Skew between non-inverted outputs running at different
frequencies.
Skew between nominal to inverted outputs running at
different frequencies.
Skew between nominal outputs at different power
supply levels.
Part-Part Skew
Skew between the outputs of any two devices under
identical settings and conditions (VDDQ,VDD,temp, air
flow, frequency, etc.).
tPD0
Ref-FB Propagation
Delay[11]
–250
48
–
+250
52
ps
%
tODCV
Output Duty Cycle
Fout < 100 MHz, measured at VDD/2
Fout > 100 MHz, measured at VDD/2
49.5/
50.5
45
48/
52
55
tPWH
tPWL
tR/tF
Output High Time
Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD
2.5V.
=
=
–
–
–
–
1.5
2.0
1.5
ns
ns
ns
Deviation from 50%
Output Low Time
Deviation from 50%
Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD
2.5V.
–
Output Rise/Fall Time
Measured at 0.8V – 2.0V for VDD = 3.3V and 0.7V–1.7V
for VDD = 2.5V.
0.15
tLOCK
tCCJ
PLL lock time[12,13]
Cycle-Cycle Jitter
–
–
–
0.5
ms
ps
Divide by one output frequency, FS = L, FB = divide by
1, 2, 4.
50
100
Divide by one output frequency, FS = M/H, FB = divide
by 1, 2, 4.
–
70
150
ps
Note
10. Test load = 20 pF, terminated to V /2. All outputs are equally loaded.
CC
11. t is measured at 1.5V for V = 3.3V and at 1.25V for V = 2.5V with REF rise/fall times of 0.5 ns between 0.8V – 2.0V.
PD
DD
DD
12. t
is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
LOCK
13. Lock detector circuit may be unreliable for input frequencies lower than 4 MHz, or for input signals which contain significant jitter.
Document #: 38-07338 Rev. *D
Page 8 of 12
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CY7B9950
AC Timing Definitions
Figure 5. Timing Definitions
tREF
tPWL
tPWH
REF
tPD
t0DCV
t0DCV
FB
tCCJ1-12
Q
tSKEWPR
tSKEWPR
tSKEW0,1
tSKEW0,1
OTHER Q
tSKEW1
tSKEW1
INVERTED Q
tSKEW3
tSKEW3
tSKEW3
REF DIVIDED BY 2
tSKEW1,3,4
tSKEW1,3,4
REF DIVIDED BY 4
Document #: 38-07338 Rev. *D
Page 9 of 12
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CY7B9950
Ordering Information
Part Number
Package Type
Product Flow
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Status
CY7B9950AC
CY7B9950ACT
CY7B9950AI
32 TQFP
Not for new design
Not for new design
Not for new design
Not for new design
32 TQFP – Tape and Reel
32 TQFP
CY7B9950AIT
Pb-free
32 TQFP – Tape and Reel
CY7B9950AXC
CY7B9950V-5AXC
CY7B9950AXCT
CY7B9950AXI
CY7B9950AXIT
32 TQFP
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Active
Active
Active
Active
Active
32 TQFP
32 TQFP – Tape and Reel
32 TQFP
32 TQFP – Tape and Reel
Document #: 38-07338 Rev. *D
Page 10 of 12
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CY7B9950
Package Drawing and Dimension
Figure 6. 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
Document #: 38-07338 Rev. *D
Page 11 of 12
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CY7B9950
Document History Page
Document Title: RoboClock® CY7B9950 2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer
Document Number: 38-07338
Orig. of
Change
Rev.
ECN No. Issue Date
Description of Change
**
121663
122548
11/25/02
12/12/02
RGL
New Data Sheet
Removed the PD#/DIV and DS[1:0] pins in V ,V
*A
RGL
and V for both 2.5V
IHH IMM ILL
and 3.3V DC Electrical Specs tables
Corrected the description of Pin 27(TEST) in the Pin Description table
Corrected the description of Pin 12 (V ) in the Pin Description table
*B
124646
03/05/03
RGL
DDQ
Corrected the Min and Max values of V from 2.25/2.75 to 2.375/2.625
DD
Volts in the Absolute Maximum Conditions table
*C
*D
433662
See ECN
See ECN
RGL
Added Lead-free devices
Added Jitter typical values
1562063
PYG/AESA Added Lead-free CY7B9940V-5AXC to Ordering Information
Added Status column to Ordering Information table
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07338 Rev. *D
Revised September 27, 2007
Page 12 of 12
RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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