CY7C09199V-9AXI [CYPRESS]
3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM; 3.3V 32K / 64K / 128K X 8/9同步双端口静态RAM
| 型号： | CY7C09199V-9AXI |
| 厂家： | 
CYPRESS |
| 描述： | 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM |
| 文件： | 总18页 (文件大小：537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C09079V/89V/99V
CY7C09179V/89V/99V
CY7C09079V/89V/99V
CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9
Synchronous Dual-Port Static RAM
• High-speed clock to data access 6.5[1]/7.5[1]/9/12 ns
(max.)
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 3.3V low operating power
— Active= 115 mA (typical)
• 6 Flow-Through/Pipelined devices
— 32K x 8/9 organizations (CY7C09079V/179V)
— 64K x 8/9 organizations (CY7C09089V/189V)
— 128K x 8/9 organizations (CY7C09099V/199V)
• 3 Modes
— Standby= 10 µA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Flow-Through
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast
100-MHz operation
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• 0.35-micron CMOS for optimum speed/power
• Pb-Free packages available
Logic Block Diagram
R/WL
OEL
R/WR
OER
CE0L
CE0R
1
1
CE1L
CE1R
0
0
0/1
0/1
1
0
0
1
0/1
0/1
FT/PipeL
FT/PipeR
8/9
8/9
[2]
[2]
7/8R
I/O0L–I/O7/8L
I/O0R–I/O
I/O
Control
I/O
Control
15/16/17
15/16/17
[3]
[3]
A0–A
CLKL
A0–A
14/15/16R
14/15/16L
Counter/
Counter/
Address
Register
Decode
CLKR
Address
Register
Decode
True Dual-Ported
ADSL
ADSR
RAM Array
CNTENL
CNTRSTL
CNTENR
CNTRSTR
Notes:
1. See page 6 for Load Conditions.
2. I/O –I/O for x8 devices, I/O –I/O for x9 devices.
0
7
0
8
3. A –A for 32K, A –A for 64K, and A –A for 128K devices.
0
14
0
15
0
16
Cypress Semiconductor Corporation
Document #: 38-06043 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised May 18, 2005
CY7C09079V/89V/99V
CY7C09179V/89V/99V
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. The use of multiple Chip Enables allows easier
banking of multiple chips for depth expansion configurations.
In the pipelined mode, one cycle is required with CE0 LOW and
CE1 HIGH to reactivate the outputs.
Functional Description
The CY7C09079V/89V/99V and CY7C09179V/89V/99V are
high-speed synchronous CMOS 32K, 64K, and 128K x 8/9
dual-port static RAMs. Two ports are provided, permitting
independent, simultaneous access for reads and writes to any
location in memory.[4] Registers on control, address, and data
lines allow for minimal set-up and hold times. In pipelined
output mode, data is registered for decreased cycle time.
Clock to data valid tCD2 = 6.5 ns[1] (pipelined). Flow-through
mode can also be used to bypass the pipelined output register
to eliminate access latency. In flow-through mode data will be
available tCD1 = 18 ns after the address is clocked into the
device. Pipelined output or flow-through mode is selected via
the FT/Pipe pin.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
LOW-to-HIGH transition of the clock signal. The internal write
pulse is self-timed to allow the shortest possible cycle times.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
100-Pin TQFP
(Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
2
NC
A7L
3
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R
GND
NC
A8L
4
A9L
5
A10L
A11L
A12L
A13L
A14L
A15L
A16L
VCC
NC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
[5]
[6]
[5]
[6]
CY7C09099V (128K x 8)
CY7C09089V (64K x 8)
CY7C09079V (32K x 8)
NC
NC
NC
NC
NC
NC
CE0L
CE1L
CE0R
CE1R
CNTRSTL
R/WL
CNTRSTR
R/WR
OEL
OER
[7]
[7]
FT/PIPEL
FT/PIPER
GND
NC
NC
24
25
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes:
4. When writing simultaneously to the same location, the final value cannot be guaranteed.
5. This pin is NC for CY7C09079V.
6. This pin is NC for CY7C09079V and CY7C09089V.
7. For CY7C09079V and CY7C09089V, pin #23 connected to V is pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is pin
CC
compatible with an IDT 5V x16 flow-through device.
Document #: 38-06043 Rev. *B
Page 2 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Pin Configurations (continued)
100-Pin TQFP
(Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
2
NC
A7L
3
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R
GND
NC
A8L
4
A9L
5
A10L
A11L
A12L
A13L
A14L
A15L
A16L
VCC
NC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
[8]
[9]
[8]
[9]
CY7C09199V (128K x 9)
CY7C09189V (64K x 9)
CY7C09179V (32K x 9)
NC
NC
NC
NC
NC
NC
CE0L
CE1L
CE0R
CE1R
CNTRSTL
R/WL
CNTRSTR
R/WR
OEL
OER
FT/PIPEL
FT/PIPER
GND
NC
NC
24
25
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V
CY7C09179V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V
-6[1]
100
6.5
-7[1]
83
-9
67
9
-12
50
12
f
MAX2 (MHz) (Pipelined)
Max. Access Time (ns)
(Clock to Data,
Pipelined)
7.5
Typical Operating
Current ICC (mA)
175
25
155
25
135
20
115
20
TypicalStandbyCurrent
for ISB1 (mA) (Both
Ports TTL Level)
TypicalStandbyCurrent
for ISB3 (µA) (Both Ports
CMOS Level)
10 µA
10 µA
10 µA
10 µA
Notes:
8. This pin is NC for CY7C09179V.
9. This pin is NC for CY7C09179V and CY7C09189V.
Document #: 38-06043 Rev. *B
Page 3 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Pin Definitions
Left Port
A0L–A16L
ADSL
Right Port
Description
A0R–A16R
ADSR
Address Inputs (A0–A14 for 32K; A0–A15 for 64K; and A0–A16 for 128K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
CE0L,CE1L
CE0R,CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to
their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKL
CLKR
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O8L
OEL
I/O0R–I/O8R Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices).
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
FT/PIPEL
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
FT/PIPE
R
GND
NC
Ground Input.
No Connect.
Power Input.
VCC
Maximum Ratings[10]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................>2001V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.....................................................>200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +4.6V
Operating Range
Ambient
Range
Commercial
Industrial[11]
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to
Outputs in High Z State............................–0.5V to VCC+0.5V
3.3V ± 300 mV
3.3V ± 300 mV
DC Input Voltage......................................–0.5V to VCC+0.5V
Notes:
10. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
11. Industrial parts are available in CY7C09099V and CY7C09199V only.
Document #: 38-06043 Rev. *B
Page 4 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Electrical Characteristics Over the Operating Range
CY7C09079V/89V/99V
CY7C09179V/89V/99V
-6[1]
-7[1]
-9
-12
Parameter
Description
VOH
Output HIGH Voltage (VCC = Min. 2.4
2.4
2.0
2.4
2.4
2.0
V
V
I
OH = –4.0 mA)
Output LOW Voltage (VCC = Min.
OH = +4.0 mA)
VOL
0.4
0.8
0.4
0.8
0.4
0.8
0.4
0.8
I
VIH
VIL
IOZ
ICC
Input HIGH Voltage
Input LOW Voltage
2.0
2.0
V
V
Output Leakage Current
–10
10 –10
175 320
10 –10
10 –10
10 µA
Operating Current
(VCC=Max. IOUT =0 mA)
Outputs Disabled
Com’l.
Ind.[11]
155 275
275 390
135 225
185 295
115 205 mA
mA
ISB1
ISB2
ISB3
Standby Current (Both
Ports TTL Level)[12] CEL
& CER ≥ VIH, f = fMAX
Com’l.
Ind.[11]
25
95
25
85
20
35
65
75
20
50 mA
mA
85 120
Standby Current (One
Port TTL Level)[12] CEL |
CER ≥ VIH, f = fMAX
Com’l.
Ind.[11]
115 175
10 250
105 165
165 210
95 150
105 160
85 140 mA
mA
Standby Current (Both
Ports CMOS Level)[12]
CEL & CER ≥ VCC – 0.2V,
f = 0
Com’l.
Ind.[11]
10 250
10 250
10 250
10 250
10 250 µA
µA
ISB4
Standby Current (One
Port CMOS Level)[12]
CEL | CER ≥ VIH, f = fMAX
Com’l.
Ind.[11]
105 135
95 125
125 170
85 115
95 125
75 100 mA
mA
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
10
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
VCC = 3.3V
COUT
10
pF
Note:
12. CE and CE are internal signals. To select either the left or right port, both CE AND CE must be asserted to their active states (CE ≤ V and CE ≥ V ).
L
R
0
1
0
IL
1
IH
Document #: 38-06043 Rev. *B
Page 5 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
AC Test Loads
3.3V
3.3V
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
C = 30 pF
OUTPUT
R1 = 590Ω
OUTPUT
C = 5 pF
C = 30 pF
R2 = 435Ω
R2 = 435Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(b) Thévenin Equivalent (Load 1)
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
AC Test Loads (Applicable to -6 and -7 only)[13]
ALL INPUTPULSES
90%
Z = 50
Ω
R = 50Ω
0
OUTPUT
3.0V
GND
90%
10%
C
10%
3 ns
3 ns
≤
V
TH
= 1.4V
≤
(a) Load 1 (-6 and -7 only)
0.60
0.50
0.40
0.30
0.20
0.1 0
0.00
1 0
1 5
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Note:
13. Test Conditions: C = 10 pF.
Document #: 38-06043 Rev. *B
Page 6 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Characteristics Over the Operating Range
CY7C09079V/89V/99V
CY7C09179V/89V/99V
-6[1]
-7[1]
-9
-12
Parameter
fMAX1
fMAX2
tCYC1
tCYC2
tCH1
tCL1
tCH2
tCL2
tR
Description
fMax Flow-Through
Min. Max. Min. Max. Min. Max. Min. Max. Unit
53
45
83
40
67
33
50
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fMax Pipelined
100
Clock Cycle Time - Flow-Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow-Through
Clock LOW Time - Flow-Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
19
10
6.5
6.5
4
22
12
7.5
7.5
5
25
15
12
12
6
30
20
12
12
8
4
5
6
8
3
3
3
3
3
3
3
3
tF
Clock Fall Time
tSA
Address Set-Up Time
Address Hold Time
3.5
0
4
0
4
1
4
1
4
1
4
1
4
1
5
1
4
1
4
1
4
1
4
1
4
1
4
1
5
1
4
1
tHA
tSC
Chip Enable Set-Up Time
Chip Enable Hold Time
R/W Set-Up Time
3.5
0
4
tHC
0
tSW
3.5
0
4
tHW
R/W Hold Time
0
tSD
Input Data Set-Up Time
Input Data Hold Time
3.5
0
4
tHD
0
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
ADS Set-Up Time
3.5
0
4
ADS Hold Time
0
CNTEN Set-Up Time
3.5
0
4.5
0
CNTEN Hold Time
CNTRST Set-Up Time
CNTRST Hold Time
3.5
0
4
0
Output Enable to Data Valid
OE to Low Z
8
9
10
12
[14, 15]
tOLZ
2
1
2
1
2
1
2
1
[14, 15]
tOHZ
OE to High Z
7
7
7
20
9
7
tCD1
tCD2
tDC
Clock to Data Valid - Flow-Through
Clock to Data Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
15
6.5
18
7.5
25
12
2
2
2
2
2
2
2
2
2
2
2
2
[14, 15]
tCKHZ
9
9
9
9
[14, 15]
tCKLZ
Port to Port Delays
tCWDD Write Port Clock HIGH to Read Data Delay
tCCS Clock to Clock Set-Up Time
30
9
35
10
40
15
40
15
ns
ns
Notes:
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested.
Document #: 38-06043 Rev. *B
Page 7 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[16, 17, 18, 19]
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSC
tHC
CE1
R/W
tSW
tSA
tHW
tHA
An
An+1
An+2
An+3
ADDRESS
DATAOUT
tCKHZ
Qn+2
tDC
tDC
Qn
tCD1
Qn+1
tCKLZ
tOHZ
tOLZ
OE
tOE
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18, 19]
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
tSC
tHC
CE1
R/W
tSW
tSA
tHW
tHA
ADDRESS
DATAOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
tOHZ
Qn+2
tCKLZ
tOLZ
OE
t
OE
Notes:
16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
17. ADS = V , CNTEN and CNTRST = V
.
IH
IL
18. The output is disabled (high-impedance state) by CE =V or CE = V following the next rising edge of the clock.
0
IH
1
IL
19. Addresses do not have to be accessed sequentially since ADS = V constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
IL
Document #: 38-06043 Rev. *B
Page 8 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Bank Select Pipelined Read[20, 21]
-
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
A3
A4
ADDRESS(B1)
A5
A0
A1
A2
tHC
tSC
CE0(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
D0
D3
D1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE0(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
D4
D2
tCKLZ
tCKLZ
Left Port Write to Flow-Through Right Port Read[22, 23, 24, 25]
CLKL
tHW
tSW
R/WL
tHA
tSA
NO
MATCH
ADDRESSL
MATCH
tHD
tSD
VALID
tCCS
DATAINL
CLKR
R/WR
tCD1
tSW tHW
tSA tHA
NO
MATCH
MATCH
ADDRESSR
tCWDD
tCD1
DATAOUTR
VALID
VALID
tDC
tDC
Notes:
20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS
(B1)
= ADDRESS
.
(B2)
21. OE and ADS = V ; CE
, CE
, R/W, CNTEN, and CNTRST = V .
1(B2) IH
IL
1(B1)
22. The same waveforms apply for a right port write to flow-through left port read.
23. CE and ADS = V ; CE , CNTEN, and CNTRST = V
.
IH
0
IL
1
24. OE = V for the right port, which is being read from. OE = V for the left port, which is being written to.
IL
IH
25. It t
≤ maximum specified, then data from right port READ is not valid until the maximum specified for t
. If t >maximum specified, then data is not valid
CCS
CCS
CWDD
until t
+ t
. t
does not apply in this case.
CCS
CD1 CWDD
Document #: 38-06043 Rev. *B
Page 9 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[19, 26, 27, 28]
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD tHD
tSA
tHA
Dn+2
tCD2
tCD2
tCKHZ
tCKLZ
Qn
Qn+3
DATAOUT
READ
NO OPERATION
WRITE
READ
Pipelined Read-to-Write-to-Read (OE Controlled)[19, 26, 27, 28]
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tHW
tSW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSA
tHA
tSD tHD
Dn+2
Dn+3
tCD2
tCKLZ
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Notes:
26. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
27. CE and ADS = V ; CE , CNTEN, and CNTRST = V
.
IH
0
IL
1
28. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
Document #: 38-06043 Rev. *B
Page 10 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[17, 19, 26, 27, 28]
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
tCD1
tCD1
tCD1
tCD1
DATAOUT
Qn
tDC
Qn+1
tCKHZ
Qn+3
tCKLZ
tDC
NO
OPERATION
READ
WRITE
READ
Flow-Through Read-to-Write-to-Read (OE Controlled)[17, 20, 26, 27, 28]
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
Dn+3
tOE
tCD1
tDC
tCD1
tCD1
Qn
Qn+4
tDC
DATAOUT
OE
tOHZ
tCKLZ
READ
WRITE
READ
Document #: 38-06043 Rev. *B
Page 11 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[29]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
DATAOUT
Qx-1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Flow-Through Read with Address Counter Advance[29]
tCYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tCD1
tSCN
tHCN
DATAOUT
Qn+3
Qn+2
Qx
tDC
Qn
Qn+1
READ
WITH
READ
COUNTER HOLD
READ WITH COUNTER
EXTERNAL
ADDRESS
COUNTER
Note:
29. CE and OE = V ; CE , R/W and CNTRST = V .
IH
0
IL
1
Document #: 38-06043 Rev. *B
Page 12 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[30, 31]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Notes:
30. CE and R/W = V ; CE and CNTRST = V .
0
IL
1
IH
31. The “Internal Address” is equal to the “External Address” when ADS = V and equals the counter output when ADS = V
.
IL
IH
Document #: 38-06043 Rev. *B
Page 13 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[19, 26, 32, 33]
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
An+1
ADDRESS
INTERNAL
ADDRESS
AX
0
1
An
An+1
tSW tHW
R/W
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSRST
tHRST
CNTRST
DATAIN
tSD tHD
D0
DATAOUT
Q0
Q1
Qn
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Notes:
32. CE = V ; CE = V .
0
IL
1
IH
33. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Document #: 38-06043 Rev. *B
Page 14 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Read/Write and Enable Operation[34, 35, 36]
Inputs
Outputs
OE
CLK
CE0
CE1
R/W
I/O0–I/O9
Operation
X
H
X
X
High-Z
High-Z
DIN
Deselected[37]
X
X
L
X
L
L
L
L
X
L
Deselected[37]
Write
H
H
H
H
X
DOUT
High-Z
Read[37]
H
X
Outputs Disabled
Address Counter Control Operation[34, 38, 39, 40]
Previous
Address Address CLK ADS CNTEN CNTRST
I/O
Mode
Operation
X
An
X
X
X
X
X
H
L
Dout(0)
Reset
Counter Reset to Address 0
X
L
H
H
Dout(n)
Dout(n)
Load
Hold
Address Load into Counter
An
H
External Address Blocked—Counter
Disabled
X
An
H
L
H
Dout(n+1)
Increment Counter Enabled—Internal Address
Generation
Notes:
34. “X” = “Don’t Care”, “H” = V , “L” = V
.
IL
IH
35. ADS, CNTEN, CNTRST = “Don’t Care.”
36. OE is an asynchronous input signal.
37. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
38. CE and OE = V ; CE and R/W = V
.
IH
0
IL
1
39. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
40. Counter operation is independent of CE and CE .
0
1
Document #: 38-06043 Rev. *B
Page 15 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Ordering Information
32K x8 3.3V Synchronous Dual-Port SRAM
Speed (ns)
6.5[1]
Ordering Code
CY7C09079V-6AC
CY7C09079V-7AC
CY7C09079V-7AI
CY7C09079V-9AC
CY7C09079V-12AC
Package Name
A100
Package Type
Operating Range
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Industrial
7.5[1]
A100
A100
9
A100
Commercial
Commercial
12
A100
64K x8 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09089V-6AC
CY7C09089V-6AXC
CY7C09089V-7AC
CY7C09089V-9AC
CY7C09089V-12AC
CY7C09089V-12AXC
Package Name
A100
Package Type
Operating Range
Commercial
6.5[1]
100-Pin Thin Quad Flat Pack
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
7.5[1]
9
A100
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Commercial
A100
12
A100
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
128K x8 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09099V-6AC
CY7C09099V-6AXC
CY7C09099V-7AC
CY7C09099V-7AI
CY7C09099V-7AXI
CY7C09099V-9AC
CY7C09099V-9AI
CY7C09099V-12AC
CY7C09099V-12AXC
Package Name
A100
Package Type
Operating Range
6.5[1]
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
Commercial
Commercial
Industrial
A100
7.5[1]
A100
A100
A100
Industrial
9
A100
Commercial
Industrial
A100
12
A100
Commercial
Commercial
A100
32K x9 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09179V-6AC
CY7C09179V-6AXC
CY7C09179V-7AC
CY7C09179V-9C
Package Name
A100
Package Type
Operating Range
6.5[1]
100-Pin Thin Quad Flat Pack
Commercial
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
7.5[1]
9
A100
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Commercial
A100
12
CY7C09179V-12AC
CY7C09179V-12AXC
A100
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
64K x9 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09189V-6AC
CY7C09189V-6AXC
CY7C09189V-7AC
CY7C09189V-9AC
CY7C09189V-12AC
CY7C09189V-12AXC
Package Name
A100
Package Type
Operating Range
Commercial
6.5[1]
100-Pin Thin Quad Flat Pack
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
7.5[1]
9
A100
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Commercial
A100
12
A100
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
Document #: 38-06043 Rev. *B
Page 16 of 18
CY7C09079V/89V/99V
CY7C09179V/89V/99V
128K x9 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09199V-6AC
CY7C09199V-6AXC
CY7C09199V-7AC
CY7C09199V-7AXC
CY7C09199V-9AC
CY7C09199V-9AXC
CY7C09199V-9AI
Package Name
A100
Package Type
Operating Range
6.5[1]
100-Pin Thin Quad Flat Pack
Commercial
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
100-Pin Thin Quad Flat Pack Commercial
100-Pin Pb-Free Thin Quad Flat Pack Commercial
100-Pin Thin Quad Flat Pack Commercial
100-Pin Pb-Free Thin Quad Flat Pack Commercial
100-Pin Thin Quad Flat Pack Industrial
100-Pin Pb-Free Thin Quad Flat Pack Industrial
100-Pin Thin Quad Flat Pack Commercial
100-Pin Pb-Free Thin Quad Flat Pack Commercial
7.5[1]
9
A100
A100
A100
A100
A100
CY7C09199V-9AXI
CY7C09199V-12AC
CY7C09199V-12AXC
A100
12
A100
A100
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06043 Rev. *B
Page 17 of 18
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document History Page
Document Title: CY7C09079V/89V/99V, CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9Synchronous Dual Port Static
RAM
Document Number: 38-06043
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
110191
122293
365034
09/29/01
12/27/02
SZV
RBI
Change from Spec number: 38-00667 to 38-06043
Power up requirements added to Operating Conditions Information
*A
*B
See ECN PCX
Added Pb-Free Logo
Added Pb-Free Part Ordering Information:
CY7C09089V-6AXC, CY7C09089V-12AXC, CY7C09099V-6AXC,
CY7C09099V-7AI, CY7C09099V-7AXI, CY7C09099V-12AXC,
CY7C09179V-6AXC, CY7C09179V-12AXC, CY7C09189V-6AXC,
CY7C09189V-12AXC, CY7C09199V-6AXC, CY7C09199V-7AXC,
CY7C09199V-9AXC, CY7C09199V-9AXI, CY7C09199V-12AXC
Document #: 38-06043 Rev. *B
Page 18 of 18
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