CY7C1006D-12VXC [CYPRESS]
Standard SRAM, 256KX4, 12ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOJ-28;
| 型号： | CY7C1006D-12VXC |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX4, 12ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOJ-28 静态存储器 光电二极管 |
| 文件： | 总10页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C106D
CY7C1006D
PRELIMINARY
1-Mbit (256K x 4) Static RAM
Features
Functional Description[1]
The CY7C106D and CY7C1006D are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE), an active LOW Output Enable (OE), and tri-state
drivers. These devices have an automatic power-down feature
that reduces power consumption by more than 65% when the
devices are deselected.
• Pin- and function-compatible with
CY7C106B/CY7C1006B
• High speed
— tAA = 10 ns
• CMOS for optimum speed/power
• Low active power
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O0 through I/O3) is then written into the location
specified on the address pins (A0 through A17).
— ICC = 60 mA @ 10 ns
• Low CMOS standby power
— ISB2 = 3.0 mA
Reading from the devices is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the four I/O pins.
• Data Retention at 2.0V
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Available in Pb-Free packages
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
The CY7C106D is available in a standard 400-mil-wide
Pb-Free SOJ; the CY7C1006D is available in a standard
300-mil-wide Pb-Free SOJ.
Logic Block Diagram
Pin Configuration
SOJ
Top View
28
27
26
1
2
3
4
5
6
A
1
V
CC
0
A
A
17
A
A
2
16
A
25
24
A
3
15
A
A
4
14
23
22
A
A
5
13
A
A
7
8
6
12
INPUT BUFFER
21
20
19
18
17
A
A
7
11
A
9
NC
I/O
8
A1
10
11
12
13
A
9
10
3
2
1
A2
A3
A4
A5
A6
A7
A8
I/O3
I/O2
I/O1
I/O0
A
I/O
I/O
CE
16
15
OE
I/O
0
512 x 512 x 4
ARRAY
14
GND
WE
A9
POWER
DOWN
COLUMN
DECODER
CE
WE
OE
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05459 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 11, 2005
CY7C106D
CY7C1006D
PRELIMINARY
Selection Guide
CY7C106D-10
CY7C1006D-10
CY7C106D-12
CY7C1006D-12
Maximum Access Time (ns)
10
60
3
12
50
3
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Document #: 38-05459 Rev. *C
Page 2 of 10
CY7C106D
CY7C1006D
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage ..........................................> 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC Relative to GND[2] .... –0.5V to +7.0V
Operating Range
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–45°C to +85°C
VCC
DC Voltage Applied to Outputs
5V ± 10%
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C106D-10
7C1006D-10
7C106D-12
7C1006D-12
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Unit
VOH
VOL
VIH
VIL
IIX
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
Input HIGH Voltage
2.4
2.4
V
V
0.4
VCC + 0.3
0.8
0.4
VCC + 0.3
0.8
2.0
–0.5
–1
2.0
–0.5
–1
V
Input LOW Voltage[2]
V
Input Load Current
GND < VI < VCC
+1
+1
µA
µA
IOZ
Output Leakage
Current
GND < VI < VCC
Output Disabled
,
–1
+1
–1
+1
IOS
ICC
ISB1
Output Short
VCC = Max., VOUT = GND
–300
60
–300
50
mA
mA
mA
Circuit Current[3]
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
Automatic CE
Power-Down Current VIN > VIH or VIN < VIL,
Max. VCC, CE > VIH,
10
10
—TTL Inputs
f = fMAX
ISB2
Automatic CE
Power-Down Current VIN > VCC – 0.3V
—CMOS Inputs or VIN < 0.3V, f=0
Max. VCC, CE > VCC – 0.3V,
3
3
mA
Capacitance[4]
Parameter
CIN: Addresses
CIN: Controls
COUT
Description
Test Conditions
Max.
7
Unit
Input Capacitance
TA = 25°C, f = 1 MHz,
CC = 5.0V
pF
pF
pF
V
10
Output Capacitance
10
Thermal Resistance[4]
Parameter
Description
Test Conditions
All-Packages
Unit
ΘJA
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
TBD
°C/W
(Junction to Ambient)[4]
ΘJC
Thermal Resistance
(Junction to Case)[4]
TBD
°C/W
Notes:
2. V (min.) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IL
IH
CC
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05459 Rev. *C
Page 3 of 10
CY7C106D
CY7C1006D
PRELIMINARY
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
10%
10-ns Device
3.0V
Z = 50Ω
90%
10%
OUTPUT
GND
50Ω
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Rise Time < 1V/ns
Fall Time < 1V/ns
1.5V
(a)
High-Z Characteristics
12 -ns Devices
R1 480 Ω
R1 480 Ω
5V
5V
OUTPUT
R2
255 Ω
30 pF
R2
255Ω
INCLUDING
JIG AND
SCOPE
5 pF
INCLUDING
JIG AND
SCOPE
(b)
(c)
THÉ
Equivalent to:
OUTPUT
VENIN EQUIVALENT
167Ω
1.73V
Switching Characteristics Over the Operating Range[5]
7C106D-10
7C1006D-10
7C106D-12
7C1006D-12
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
[6]
tpower
VCC(typical) to the first access
Read Cycle Time
100
10
100
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[7, 8]
CE LOW to Low Z[8]
CE HIGH to High Z[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
10
12
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
10
5
12
6
0
3
0
0
3
0
5
5
6
6
tPD
10
12
Write Cycle[9, 10]
tWC
tSCE
tAW
Write Cycle Time
10
8
12
10
10
0
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
7
tHA
0
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
6. t
7. t
/I and 30-pF load capacitance.
OL OH
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
POWER
CC
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
HZOE HZCE
HZWE
8. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
9. The internal write time of the memory is defined by the overlap of CEand WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t .
SD
HZWE
Document #: 38-05459 Rev. *C
Page 4 of 10
CY7C106D
CY7C1006D
PRELIMINARY
Switching Characteristics Over the Operating Range[5]
7C106D-10
7C1006D-10
7C106D-12
7C1006D-12
Parameter
tSA
Description
Address Set-Up to Write Start
WE Pulse Width
Min.
Max.
Min.
Max.
Unit
ns
0
7
6
0
3
0
10
7
tPWE
ns
tSD
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[8]
ns
tHD
0
ns
tLZWE
tHZWE
2
ns
WE LOW to High Z[7, 8]
6
6
ns
Data Retention Characteristics Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min.
Max.
Unit
V
2.0
Non-L, Com’l / Ind’l VCC = VDR = 2.0V,
3
mA
mA
ns
ICCDR
Data Retention Current
CE > VCC – 0.3V,
L-Version Only
1.2
VIN > VCC – 0.3V or
[4]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
VIN < 0.3V
[11, 12]
tR
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
> 2V
4.5V
4.5V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No.1[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DA TA VALID
DATA VALID
Notes:
11. Full device operation requires linear V ramp from V to V
12. tr < 3 ns for all speeds.
> 50 µs or stable at V > 50 µs.
CC(min.)
CC
DR
CC(min.)
13. Device is continuously selected, OE and CE = V .
IL
14. WE is HIGH for read cycle.
Document #: 38-05459 Rev. *C
Page 5 of 10
CY7C106D
CY7C1006D
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
V
CC
ICC
t
PU
SUPPLY
CURRENT
50%
50%
ISB
Write Cycle No. 1 (CE Controlled)[16, 17]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
SD
t
HD
DATA I/O
DATA VALID
Notes:
15. Address valid prior to or coincident with CE transition LOW.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. Data I/O is high impedance if OE = V
.
IH
Document #: 38-05459 Rev. *C
Page 6 of 10
CY7C106D
CY7C1006D
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA I/O
DATA VALID
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[10, 17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
SD
t
HD
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
L
OE
X
WE
X
Input/Output
High Z
Mode
Power
Power-Down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
L
H
Data Out
Data In
High Z
)
L
X
L
Write
)
L
H
H
Selected, Outputs Disabled
)
Document #: 38-05459 Rev. *C
Page 7 of 10
CY7C106D
CY7C1006D
PRELIMINARY
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
10
CY7C106D-10VXC
CY7C1006D-10VXC
CY7C106D-10VXI
CY7C1006D-10VXI
CY7C106D-12VXC
CY7C1006D-12VXC
CY7C106D-12VXI
CY7C1006D-12VXI
V28
V21
V28
V21
V28
V21
V28
V21
28-Lead (400-Mil) Molded SOJ (Pb-Free) Commercial
28-Lead (300-Mil) Molded SOJ (Pb-Free)
28-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial
28-Lead (300-Mil) Molded SOJ (Pb-Free)
12
28-Lead (400-Mil) Molded SOJ (Pb-Free) Commercial
28-Lead (300-Mil) Molded SOJ (Pb-Free)
28-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial
28-Lead (300-Mil) Molded SOJ (Pb-Free)
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
MIN.
DIMENSIONS IN INCHES
MAX.
PIN 1 ID
DETAIL
A
EXTERNAL LEAD DESIGN
14
1
0.291
0.300
0.330
0.350
0.026
0.032
0.013
0.019
15
28
0.014
0.020
OPTION 1
OPTION 2
0.697
0.713
SEATING PLANE
0.120
0.140
0.007
0.013
0.004
A
0.262
0.272
0.050
TYP.
0.025 MIN.
51-85031-*B
Document #: 38-05459 Rev. *C
Page 8 of 10
CY7C106D
CY7C1006D
PRELIMINARY
Package Diagrams (continued)
28-Lead (400-Mil) Molded SOJ V28
PIN 1 I.D
1
14
MIN.
MAX.
DIMENSIONS IN INCHES
.435
.445
.395
.405
15
28
.720
.730
SEATING PLANE
.128
.148
.007
.013
0.004
.026
.032
.360
.380
51-85032-*B
.025 MIN.
.015
.020
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05459 Rev. *C
Page 9 of 10
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C106D
CY7C1006D
PRELIMINARY
Document History Page
Document Title: CY7C106D, CY7C1006D 1-Mbit (256K x 4) Static RAM (Preliminary)
Document Number: 38-05459
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Advance information data sheet for C9 IPP
CC,ISB1,ISB2 Specs are modified as per EROS (Spec # 01-2165)
201560
233693
See ECN
See ECN
SWI
RKF
*A
I
Pb-free offering in the ‘ordering information’
*B
*C
262950
307596
See ECN
See ECN
RKF
RKF
Added Tpower Spec in Switching Characteristics table
Shaded ‘Ordering Information’
Reduced Speed bins to -10 and -12 ns
Document #: 38-05459 Rev. *C
Page 10 of 10
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