CY7C1012AV33-12BGC [CYPRESS]
512K x 24 Static RAM; 512K ×24静态RAM
| 型号： | CY7C1012AV33-12BGC |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 24 Static RAM |
| 文件： | 总9页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1012AV33
512K x 24 Static RAM
Writing the data bytes into the SRAM is accomplished when
the chip select controlling that byte is LOW and the write
enable input (WE) input is LOW. Data on the respective
input/output (I/O) pins is then written into the location specified
on the address pins (A0–A18). Asserting all of the chip selects
LOW and write enable LOW will write all 24 bits of data into
the SRAM. Output enable (OE) is ignored while in WRITE
mode.
Features
• High speed
— tAA = 8, 10, 12 ns
• Low active power
— 1080 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE0, CE1 and CE2
features
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select
controlling that byte is LOW and write enable (WE) HIGH while
output enable (OE) remains LOW. Under these conditions, the
contents of the memory location specified on the address pins
will appear on the specified data input/output (I/O) pins.
Asserting all the chip selects LOW will read all 24 bits of data
from the SRAM.
Functional Description
The CY7C1012AV33 is a high-performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is
separately controlled by the individual chip selects (CE0, CE1,
CE2). CE0 controls the data on the I/O0–I/O7, while CE1
controls the data on I/O8–I/O15, and CE2 controls the data on
the data pins I/O16–I/O23. This device has an automatic
power-down feature that significantly reduces power
consumption when deselected.
The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
The CY7C1012AV33 is available in a standard 119-ball BGA.
Functional Block Diagram
INPUT BUFFER
A
0
A
1
A
2
I/O –I/O
0
7
A
3
4
512K x 24
ARRAY
A
I/O –I/O
8
15
A
5
6
4096 x 4096
A
I/O –I/O
16
23
A
7
A
8
A
9
CE , CE , CE
0
1
2
COLUMN
DECODER
WE
CONTROL LOGIC
OE
Selection Guide
–8
8
–10
10
–12
12
Unit
ns
Maximum Access Time
Maximum Operating Current
Commercial
300
300
50
275
275
50
260
260
50
mA
Industrial
Maximum CMOS Standby Current
Commercial/Industrial
mA
Cypress Semiconductor Corporation
Document #: 38-05254 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 12, 2002
CY7C1012AV33
Pin Configurations
119 BGA
Top View
1
2
3
4
5
6
7
A
NC
A
A
A
A
A
NC
B
C
D
E
F
NC
A
A
CE0
NC
A
A
NC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
DNU
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
NC
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
NC
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A
CE1
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
NC
A
CE2
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
NC
A
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
G
H
J
K
L
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
M
N
P
R
T
A
WE
OE
A
U
NC
A
A
A
A
NC
Document #: 38-05254 Rev. *D
Page 2 of 9
CY7C1012AV33
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 0.3V
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
–8
–10
–12
Parameter
Description
Test Conditions[2]
VCC = Min.,
Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage
2.4
2.4
2.4
V
V
V
IOH = –4.0 mA
VOL
VIH
Output LOW Voltage
Input HIGH Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
2.0
VCC
2.0
VCC
2.0
VCC
+ 0.3
+ 0.3
+ 0.3
[1]
VIL
Input LOW Voltage
Input Load Current
–0.3
–1
0.8
+1
–0.3
–1
0.8
+1
–0.3
–1
0.8
+1
V
IIX
GND < VI < VCC
µA
µA
mA
mA
mA
IOZ
ICC
Output Leakage Current GND < VOUT < VCC, Output Disabled
–1
+1
–1
+1
–1
+1
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Commercial
Industrial
300
300
100
275
275
100
260
260
100
ISB1
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC
CE > VCC – 0.3V, /Industrial
VIN > VCC – 0.3V,
,
Commercial
50
50
50
mA
or VIN < 0.3V, f = 0
Capacitance[3]
Parameter
CIN
Description
Input Capacitance
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
pF
8
COUT
10
pF
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. CE refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05254 Rev. *D
Page 3 of 9
CY7C1012AV33
AC Test Loads and Waveforms[4]
R1 317
Ω
50Ω
3.3V
= 1.5V
OUTPUT
VTH
OUTPUT
Z = 50Ω
30 pF*
0
R2
351Ω
5 pF
* Capacitive Load consists of all compo-
nents of the test environment.
(a)
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
(b)
3.3V
90%
90%
10%
10%
GND
Fall time:
> 1 V/ns
Rise time > 1 V/ns
(c)
[5]
AC Switching Characteristics Over the Operating Range
–8
–10
–12
Parameter
Read Cycle
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
[6]
tpower
VCC(typical) to the first access
Read Cycle Time
1
8
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
10
12
tAA
Address to Data Valid
8
10
12
tOHA
Data Hold from Address Change
CE1, CE2, and CE3 LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[7]
OE HIGH to High-Z[7]
CE1, CE2, and CE3 LOW to Low-Z[7]
CE1, CE2, or CE3 HIGH to High-Z[7]
CE1, CE2, and CE3 LOW to Power-up[8]
CE1, CE2, or CE3 HIGH to Power-down[8]
Byte Enable to Data Valid
3
3
3
tACE
8
5
10
5
12
6
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
1
3
0
1
3
0
1
3
0
5
5
5
5
6
6
tPD
8
5
10
5
12
6
tDBE
tLZBE
tHZBE
Write Cycle[9, 10]
tWC
Byte Enable to Low-Z[7]
Byte Disable to High-Z[7]
1
1
1
5
5
6
Write Cycle Time
8
6
10
7
12
8
ns
ns
tSCE
CE1, CE2, and CE3 LOW to Write End
Notes:
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching
the minimum operating VDD , normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise.
6. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a read/write operation
is started.
7. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±200 mV from steady-state voltage.
8. These parameters are guaranteed by design and are not tested.
9. The internal write time of the memory is defined by the overlap of CE1, CE2, and CE3 LOW and WE LOW. The chip enables must be active and WE must
be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to
the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05254 Rev. *D
Page 4 of 9
CY7C1012AV33
AC Switching Characteristics Over the Operating Range (continued)[5]
–8
–10
–12
Parameter
tAW
Description
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Min.
6
Max.
Min.
7
Max.
Min.
8
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHA
0
0
0
tSA
0
0
0
tPWE
tSD
6
7
8
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[7]
5
5.5
0
6
tHD
0
0
tLZWE
tHZWE
tBW
3
3
3
WE LOW to High-Z[7]
5
5
6
Byte Enable to End of Write
6
7
8
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[2, 12, 13]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
PU
CC
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05254 Rev. *D
Page 5 of 9
CY7C1012AV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[2, 14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 16
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[2, 15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Notes:
14. Data I/O is high impedance if OE = VIH
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05254 Rev. *D
Page 6 of 9
CY7C1012AV33
Truth Table
CE0
H
L
CE1
H
H
L
CE2
H
H
H
L
OE
X
L
WE
X
I/O0–I/O23
Mode
Power
High-Z
Power-down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
H
H
H
H
L
I/O0–I/O7 Data Out
I/O8–I/O15 Data Out
I/O16–I/O23 Data Out
Full Data Out
)
H
H
L
L
Read
)
H
L
L
Read
)
L
L
Read
)
L
H
L
H
H
L
X
X
X
X
H
I/O0–I/O7 Data In
I/O8–I/O15 Data In
I/O16–I/O23 Data In
Full Data In
Write
)
H
H
L
L
Write
)
H
L
L
Write
)
L
L
Write
)
L
L
L
H
High-Z
Selected, Outputs Disabled
)
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
8
CY7C1012AV33-8BGC
CY7C1012AV33-8BGI
CY7C1012AV33-10BGC
CY7C1012AV33-10BGI
CY7C1012AV33-12BGC
CY7C1012AV33-12BGI
BG119
14 × 22 mm 119-ball BGA
Commercial
Industrial
10
12
Commercial
Industrial
Commercial
Industrial
Document #: 38-05254 Rev. *D
Page 7 of 9
CY7C1012AV33
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05254 Rev. *D
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1012AV33
Document History Page
Document Title: CY7C1012AV33 512K x 24 Static RAM
Document Number: 38-05254
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
113711
117057
117988
118992
Description of Change
03/11/02
07/31/02
09/03/02
09/19/02
NSL
DFP
DFP
DFP
New Data Sheet
Removed 15-ns bin.
Added 8-ns bin.
*A
*B
*C
Change Cin - input capacitance -from 6 pF to 8 pF.
Change Cout -output capacitance from 8 pF to 10 pF.
*D
120382
11/15/02
DFP
Final data sheet. Added note 4 to “AC Test Loads and Waveforms.”
Document #: 38-05254 Rev. *D
Page 9 of 9
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