CY7C1019BV33-10VC [CYPRESS]
128K x 8 Static RAM; 128K ×8静态RAM
| 型号： | CY7C1019BV33-10VC |
| 厂家： | 
CYPRESS |
| 描述： | 128K x 8 Static RAM |
| 文件： | 总7页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3
CY7C1019BV33
128K x 8 Static RAM
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
Features
• High speed
pins (I/O through I/O ) is then written into the location speci-
0
7
fied on the address pins (A through A ).
0
16
— t = 10 ns
AA
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Functionally equivalent to CY7C1019V33
The eight input/output pins (I/O through I/O ) are placed in a
0
7
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description
The CY7C1019BV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
The CY7C1019BV33 is available in a standard 400-mil-wide
package.
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
A
1
A
16
32
31
30
1
2
3
4
5
6
0
A
15
A
A
14
2
I/O
0
A
A
13
29
28
3
INPUT BUFFER
CE
OE
I/O
I/O
1
2
27
26
I/O
0
1
A
0
7
A
1
I/O
V
I/O
V
7
8
9
10
11
12
13
6
I/O
A
2
25
24
23
22
21
CC
SS
A
3
4
V
V
SS
A
CC
I/O
3
I/O
4
I/O
5
512 x 256 x 8
ARRAY
A
6
I/O
I/O
I/O
5
2
3
5
4
A
I/O
A
A
7
8
WE
A
4
12
A
A
11
20
19
A
5
A
6
A
10
14
15
16
I/O
6
A
18
17
POWER
DOWN
9
COLUMN
DECODER
CE
A
8
A
7
I/O
7
WE
1019BV33–2
1019BV33–1
OE
Selection Guide
7C1019BV33-10
7C1019BV33-12
7C1019BV33-15
Maximum Access Time (ns)
10
175
5
12
160
5
15
145
5
Maximum Operating Current (mA)
Maximum Standby Current (mA)
L
−
0.5
0.5
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
January 19, 2001
CY7C1019BV33
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Ambient
Temperature
[1]
Supply Voltage on V to Relative GND .... –0.5V to +7.0V
[2]
CC
Range
V
CC
DC Voltage Applied to Outputs
in High Z State ....................................–0.5V to V + 0.5V
Commercial
0°C to +70°C
3.3V ± 10%
[1]
CC
[1]
DC Input Voltage .................................–0.5V to V + 0.5V
CC
Electrical Characteristics Over the Operating Range
7C1019BV33
-10
7C1019BV33
-12
7C1019BV33
-15
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
Output HIGH Voltage
V
= Min.,
CC
= – 4.0 mA
2.4
2.4
2.4
V
OH
OL
IH
I
OH
V
V
V
Output LOW Voltage
Input HIGH Voltage
V
= Min.,
0.4
0.4
0.4
V
V
CC
I
= 8.0 mA
OL
2.2
V
2.2
V
2.2
V
CC
CC
CC
+ 0.3
0.8
+1
+ 0.3
0.8
+1
+ 0.3
0.8
+1
[1]
Input LOW Voltage
–0.3
–1
–0.3
–1
–0.3
–1
V
IL
I
I
Input Load Current
GND < V < V
CC
µA
µA
IX
I
Output Leakage
Current
GND < V < V ,
CC
Output Disabled
–5
+5
–5
+5
–5
+5
OZ
I
I
I
I
V
Operating
V
= Max.,
= 0 mA,
175
20
160
20
145
20
mA
mA
mA
CC
CC
CC
Supply Current
I
OUT
f = f
= 1/t
MAX
RC
Automatic CE
Power-Down Current
—TTL Inputs
Max. V , CE > V
CC IH
V
V
SB1
SB2
> V or
IN
IN
IH
< V , f = f
IL
MAX
Automatic CE
Max. V
,
5
5
5
CC
Power-Down Current CE > V – 0.3V,
CC
L
−
0.5
0.5
—CMOS Inputs
V
> V – 0.3V,
IN CC
or V < 0.3V, f = 0
IN
Capacitance[3]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
Input Capacitance
Output Capacitance
6
8
pF
pF
IN
A
V
= 5.0V
CC
OUT
Notes:
1.
V
IL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
2
CY7C1019BV33
AC Test Loads and Waveforms
R1 480
ALL INPUT PULSES
90%
10%
Ω
R1 480
Ω
3.3V
3.3V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
R2
255
R2
255
30 pF
5 pF
Ω
Ω
3 ns
3 ns
≤
≤
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
1019BV33–3
(a)
1019BV33–4
THÉ
VENIN EQUIVALENT
Equivalent to:
167
Ω
1.73V
OUTPUT
Switching Characteristics[4] Over the Operating Range
7C1019BV33-10
7C1019BV33-12
7C1019BV33-15
Parameter
Description
Min.
10
3
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
10
12
15
AA
3
3
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
10
5
12
6
15
7
0
3
0
0
3
0
0
3
0
[5, 6]
OE HIGH to High Z
5
5
6
6
7
7
[6]
CE LOW to Low Z
[5, 6]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
10
12
15
PD
[7, 8]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
10
8
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
8
0
0
HA
0
0
0
SA
7
8
10
8
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
5
6
0
0
0
HD
[6]
WE HIGH to Low Z
3
3
3
LZWE
HZWE
[5, 6]
WE LOW to High Z
5
6
7
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CELOW and WE LOW. CE and WEmust be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
3
CY7C1019BV33
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter Description Conditions
for Data Retention No input may exceed V + 0.5V
Min.
Max.
Unit
V
V
V
2.0
DR
CC
CC
V
= V = 2.0V,
CC
DR
I
t
t
Data Retention Current
150
µA
ns
CCDR
CE > V – 0.3V,
V
CC
[3]
Chip Deselect to Data Retention Time
Operation Recovery Time
0
> V – 0.3V or V < 0.3V
CDR
R
IN
CC IN
200
µs
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
1019BV33–5
Switching Waveforms
[9, 10]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1019BV33–6
[10, 11]
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
1019BV33–7
Notes:
9. Device is continuously selected. OE, CE = VIL.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CEtransition LOW.
4
CY7C1019BV33
Switching Waveforms (continued)
[12, 13]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
1019BV33–8
[12, 13]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
t
WC
ADDRESS
t
SCE
CE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 14
t
HZOE
1019BV33–98
Notes:
12. Data I/O is high impedance if OE = VIH
.
13. If CEgoes HIGH simultaneously with WEgoing HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
5
CY7C1019BV33
Switching Waveforms (continued)
[13]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 14
DATA I/O
DATA VALID
t
t
LZWE
HZWE
1019BV33–10
Truth Table
CE
H
X
OE
WE
X
I/O –I/O
Mode
Power
0
7
X
X
L
High Z
High Z
Power-Down
Power-Down
Read
Standby (I )
SB
X
Standby (I
)
SB
L
H
Data Out
Data In
High Z
Active (I
Active (I
Active (I
)
CC
L
X
H
L
Write
)
CC
L
H
Selected, Outputs Disabled
)
CC
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY7C1019BV33-10VC
Package Type
10
V33
V33
V33
V33
V33
V33
32-Lead 400-Mil Molded SOJ
32-Lead 400-Mil Molded SOJ
32-Lead 400-Mil Molded SOJ
32-Lead 400-Mil Molded SOJ
32-Lead 400-Mil Molded SOJ
32-Lead 400-Mil Molded SOJ
Commercial
12
CY7C1019BV33-12VC
CY7C1019BV33L-12VC
CY7C1019BV33-15VC
CY7C1019BV33L-15VC
CY7C1019BV33-15VI
15
Industrial
Document #: 38-01053-*A
6
CY7C1019BV33
Package Diagram
32-Lead (400-Mil) Molded SOJ V33
51-85041-A
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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