首页 |元器件品牌

CY7C1019BV33-10ZC [CYPRESS]

128K x 8 Static RAM; 128K ×8静态RAM
CY7C1019BV33-10ZC
型号： CY7C1019BV33-10ZC
厂家： CYPRESS    CYPRESS
描述：

128K x 8 Static RAM
128K ×8静态RAM

存储 内存集成电路 静态存储器 光电二极管
文件： 总9页 (文件大小：259K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
019V33  
CY7C1019BV33  
CY7C1018BV33  
128K x 8 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location speci-  
fied on the address pins (A0 through A16).  
Features  
• High speed  
— tAA = 10 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• CMOS for optimum speed/power  
• Center power/ground pinout  
• Automatic power-down when deselected  
• Easy memory expansion with CE and OE options  
• Functionally equivalent to CY7C1019V33 and/or  
CY7C1018V33  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description  
The CY7C1019BV33/CY7C1018BV33 is a high-performance  
CMOS static RAM organized as 131,072 words by 8 bits. Easy  
memory expansion is provided by an active LOW Chip Enable  
(CE), an active LOW Output Enable (OE), and three-state driv-  
ers. This device has an automatic power-down feature that  
significantly reduces power consumption when deselected.  
The CY7C1019BV33 is available in standard 32-pin TSOP  
Type II and 400-mil-wide package. The CY7C1018BV33 is  
available in a standard 300-mil-wide package.  
Logic Block Diagram  
Pin Configurations  
SOJ / TSOPII  
Top View  
A
A
1
A
32  
1
2
3
4
5
6
0
16  
31  
30  
A
A
A
15  
A
2
14  
13  
I/O  
0
A
3
29  
28  
INPUT BUFFER  
CE  
OE  
I/O  
I/O  
6
I/O  
I/O  
1
27  
26  
I/O  
0
1
A
0
7
A
1
I/O  
V
7
8
9
2
A
2
25  
24  
23  
22  
21  
V
CC  
SS  
A
3
4
V
V
CC  
I/O  
I/O  
SS  
A
I/O  
3
I/O  
4
I/O  
5
512 x 256 x 8  
ARRAY  
A
6
I/O  
I/O  
5
10  
11  
12  
13  
2
3
5
A
4
A
7
8
A
A
WE  
A
4
12  
11  
A
20  
19  
A
5
A
10  
14  
15  
16  
I/O  
6
7
A
6
A
9
A
8
POWER  
DOWN  
18  
17  
COLUMN  
DECODER  
CE  
A
7
I/O  
WE  
OE  
Selection Guide  
7C1019BV33-10  
7C1018BV33-10  
7C1019BV33-12  
7C1018BV33-12  
7C1019BV33-15  
7C1018BV33-15  
Maximum Access Time (ns)  
10  
175  
5
12  
160  
5
15  
145  
5
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
L
−
0.5  
0.5  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
June 11, 2001  
CY7C1019BV33  
CY7C1018BV33  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
Static Discharge Voltage ........................................... >2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-Up Current..................................................... >200 mA  
Storage Temperature .................................–65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Operating Range  
Ambient  
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V  
Range  
Temperature[2]  
VCC  
DC Voltage Applied to Outputs  
Commercial  
0°C to +70°C  
3.3V ± 10%  
in High Z State[1]....................................–0.5V to VCC + 0.5V  
DC Input Voltage[1].................................–0.5V to VCC + 0.5V  
Electrical Characteristics Over the Operating Range  
7C1019BV33-10 7C1019BV33-12 7C1019BV33-15  
7C1018BV33-10 7C1018BV33-12 7C1018BV33-15  
Parameter  
Description  
Test Conditions  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
VOH  
Output HIGH Voltage VCC = Min.,  
2.4  
2.4  
2.4  
V
IOH = – 4.0 mA  
VOL  
VIH  
Output LOW Voltage VCC = Min.,  
IOL = 8.0 mA  
0.4  
0.4  
0.4  
V
V
Input HIGH Voltage  
2.2  
VCC  
+ 0.3  
2.2  
VCC  
+ 0.3  
2.2  
VCC  
+ 0.3  
VIL  
IIX  
Input LOW Voltage[1]  
–0.3  
–1  
0.8  
+1  
+5  
–0.3  
–1  
0.8  
+1  
+5  
–0.3  
–1  
0.8  
+1  
+5  
V
Input Load Current  
GND < VI < VCC  
µA  
µA  
IOZ  
Output Leakage  
Current  
GND < VI < VCC  
,
–5  
–5  
–5  
Output Disabled  
ICC  
VCC Operating  
Supply Current  
VCC = Max.,  
IOUT = 0 mA,  
f = fMAX = 1/tRC  
175  
20  
160  
20  
145  
20  
mA  
mA  
mA  
ISB1  
Automatic CE  
Power-Down Current VIN > VIH or  
—TTL Inputs  
Max. VCC, CE > VIH  
VIN < VIL, f = fMAX  
ISB2  
Automatic CE  
Max. VCC  
,
5
5
5
Power-Down Current CE > VCC – 0.3V,  
L
−
0.5  
0.5  
—CMOS Inputs  
VIN > VCC – 0.3V,  
or VIN < 0.3V, f = 0  
Capacitance[3]  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
CIN  
Input Capacitance  
Output Capacitance  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
6
8
pF  
pF  
COUT  
Notes:  
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.  
2. TA is the “Instant On” case temperature.  
3. Tested initially and after any design or process changes that may affect these parameters.  
2
CY7C1019BV33  
CY7C1018BV33  
AC Test Loads and Waveforms  
R1 480 Ω  
ALL INPUT PULSES  
90%  
10%  
R1 480 Ω  
3.3V  
3.3V  
OUTPUT  
3.0V  
GND  
90%  
10%  
OUTPUT  
R2  
R2  
255 Ω  
30 pF  
5 pF  
255 Ω  
≤ 3 ns  
≤ 3 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(b)  
(a)  
THÉ  
Equivalent to:  
VENIN EQUIVALENT  
167 Ω  
1.73V  
OUTPUT  
Switching Characteristics[4] Over the Operating Range  
7C1019BV33-10  
7C1018BV33-10  
7C1019BV33-12  
7C1018BV33-12  
7C1019BV33-15  
7C1018BV33-15  
Parameter  
READ CYCLE  
tRC  
Description  
Min.  
10  
3
Max.  
Min.  
Max.  
Min.  
15  
3
Max.  
Unit  
Read Cycle Time  
12  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
OE HIGH to High Z[5, 6]  
CE LOW to Low Z[6]  
CE HIGH to High Z[5, 6]  
CE LOW to Power-Up  
CE HIGH to Power-Down  
10  
12  
15  
tOHA  
3
tACE  
10  
5
12  
6
15  
7
tDOE  
tLZOE  
0
3
0
0
3
0
0
3
0
tHZOE  
tLZCE  
tHZCE  
tPU  
5
5
6
6
7
7
tPD  
10  
12  
15  
WRITE CYCLE[7, 8]  
tWC  
tSCE  
tAW  
Write Cycle Time  
10  
8
12  
9
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
7
8
tHA  
0
0
tSA  
0
0
0
tPWE  
tSD  
7
8
10  
8
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z[6]  
5
6
tHD  
0
0
0
tLZWE  
3
3
3
tHZWE  
WE LOW to High Z[5, 6]  
5
6
7
Notes:  
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
IOL/IOH and 30-pF load capacitance.  
5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.  
7. The internal write time of the memory is defined by the overlap of CELOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these  
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD  
.
3
CY7C1019BV33  
CY7C1018BV33  
Data Retention Characteristics Over the Operating Range (L Version Only)  
Parameter  
VDR  
Description  
VCC for Data Retention  
Conditions  
Min.  
Max.  
Unit  
V
No input may exceed VCC + 0.5V  
VCC = VDR = 2.0V,  
CE > VCC – 0.3V,  
2.0  
ICCDR  
Data Retention Current  
150  
µA  
ns  
[3]  
tCDR  
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
VIN > VCC – 0.3V or VIN < 0.3V  
tR  
200  
µs  
Data Retention Waveform  
DATA RETENTION MODE  
3.0V  
3.0V  
V
DR  
> 2V  
V
CC  
t
t
R
CDR  
CE  
Switching Waveforms  
Read Cycle No. 1[9, 10]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 (OE Controlled)[10, 11]  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
ICC  
ISB  
t
PU  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
Notes:  
9. Device is continuously selected. OE, CE = VIL.  
10. WE is HIGH for read cycle.  
11. Address valid prior to or coincident with CE transition LOW.  
4
CY7C1019BV33  
CY7C1018BV33  
Switching Waveforms (continued)  
Write Cycle No. 1 (CE Controlled)[12, 13]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
SCE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
DATA VALID  
DATA I/O  
IN  
NOTE 14  
t
HZOE  
Notes:  
12. Data I/O is high impedance if OE = VIH  
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
14. During this period the I/Os are in the output state and input signals should not be applied.  
5
CY7C1019BV33  
CY7C1018BV33  
Switching Waveforms (continued)  
Write Cycle No. 3 (WE Controlled, OE LOW)[13]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
NOTE 14  
DATA I/O  
DATA VALID  
t
t
LZWE  
HZWE  
Truth Table  
CE  
H
X
OE  
WE  
X
I/O0–I/O7  
Mode  
Power  
X
X
L
High Z  
High Z  
Power-Down  
Power-Down  
Read  
Standby (ISB  
Standby (ISB  
Active (ICC  
Active (ICC  
Active (ICC  
)
X
)
L
H
Data Out  
Data In  
High Z  
)
L
X
H
L
Write  
)
L
H
Selected, Outputs Disabled  
)
6
CY7C1019BV33  
CY7C1018BV33  
Ordering Information  
Speed  
(ns)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
32-Lead 300-Mil Molded SOJ  
10  
CY7C1018V33-10VC  
CY7C1019BV33-10VC  
CY7C1019BV33-10ZC  
CY7C1018BV33-12VC  
CY7C1018BV33L-12VC  
CY7C1019BV33-12VC  
CY7C1019BV33-12ZC  
CY7C1019BV33L-12VC  
CY7C1019BV33L-12ZC  
CY7C1018BV33-15VC  
CY7C1018BV33L-15VC  
CY7C1018BV33-15VI  
CY7C1019BV33-15VC  
CY7C1019BV33-15ZC  
CY7C1019BV33L-15VC  
CY7C1019BV33L-15ZC  
CY7C1019BV33-15VI  
CY7C1019BV33-15ZI  
V32  
V33  
Commercial  
32-Lead 400-Mil Molded SOJ  
32-Lead TSOP Type II  
ZS32  
V32  
12  
15  
32-Lead 300-Mil Molded SOJ  
32-Lead 300-Mil Molded SOJ  
32-Lead 400-Mil Molded SOJ  
32-Lead TSOP Type II  
V32  
V33  
ZS32  
V33  
32-Lead 400-Mil Molded SOJ  
32-Lead TSOP Type II  
ZS32  
V32  
32-Lead 300-Mil Molded SOJ  
32-Lead 300-Mil Molded SOJ  
32-Lead 300-Mil Molded SOJ  
32-Lead 400-Mil Molded SOJ  
32-Lead TSOP Type II  
V32  
V32  
V33  
ZS32  
V33  
32-Lead 400-Mil Molded SOJ  
32-Lead TSOP Type II  
ZS32  
V33  
32-Lead 400-Mil Molded SOJ  
32-Lead TSOP Type II  
ZS32  
Industrial  
Document #: 38-01053-*B  
7
CY7C1019BV33  
CY7C1018BV33  
Package Diagram  
32-Lead (400-Mil) Molded SOJ V33  
51-85041-A  
32-Lead (300-Mil) Molded SOJ V32  
51-85041  
8
CY7C1019BV33  
CY7C1018BV33  
Package Diagram  
32-Lead  
TSOP II ZS32  
51-85095  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明