CY7C1019D-12VXC [CYPRESS]
Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, LEAD FREE, SOJ-32;
| 型号： | CY7C1019D-12VXC |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, LEAD FREE, SOJ-32 静态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1019D
PRELIMINARY
1-Mbit (128K x 8) Static RAM
Features
Functional Description[1]
• Pin- and function-compatible with CY7C1019B
• High speed
The CY7C1019D is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
— tAA = 10 ns
• CMOS for optimum speed/power
• Low active power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight
I/O pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A16).
— ICC = 60 mA @ 10 ns
• Low CMOS standby power
— ISB2 = 1.2 mA (‘L’ Version only)
• Data Retention at 2.0V
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Functionally equivalent to CY7C1019B
• Available in Pb-Free Packages
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019D is available in standard 32-pin TSOP Type
II and 400-mil-wide SOJ Pb-Free packages.
Logic Block Diagram
Pin Configurations
/TSOPII
SOJ
Top View
A
A
1
A
A
32
1
0
16
31
30
2
3
4
5
6
15
A
2
A
14
A
13
A
29
28
3
I/O
0
CE
I/O
OE
I/O
I/O
6
INPUT BUFFER
27
26
0
7
I/O
I/O
1
2
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O
7
1
25
24
23
22
21
V
V
8
9
10
11
12
13
V
V
CC
I/O
5
I/O
CC
SS
SS
I/O
3
I/O
4
I/O
5
512 x 256 x 8
ARRAY
I/O
I/O
2
3
4
A
A
A
WE
12
11
A
4
20
19
A
5
10
I/O
14
15
16
6
7
POWER
DOWN
COLUMN
DECODER
CE
WE
A
6
A
9
A
8
18
17
I/O
A
7
OE
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05464 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 11, 2005
PRELIMINARY
CY7C1019D
Selection Guide
CY7C1019D-10
CY7C1019D-12
Unit
ns
Maximum Access Time
10
60
3
12
50
3
Maximum Operating Current
Maximum Standby Current
mA
mA
L
1.2
1.2
Document #: 38-05464 Rev. *C
Page 2 of 9
PRELIMINARY
CY7C1019D
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.....................................................> 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +7.0V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
5V ± 10%
5V ± 10%
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C1019D-10
7C1019D-12
Min. Max.
Parameter
VOH
Description
Test Conditions
Min.
Max.
Unit
V
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
Input HIGH Voltage
2.4
2.0
2.4
VOL
0.4
0.4
V
VIH
VCC
2.0
VCC
V
+ 0.3
+ 0.3
VIL
IIX
Input LOW Voltage[2]
–0.5
–1
0.8
+1
+1
–0.5
–1
0.8
+1
+1
V
Input Load Current
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VI < VCC
,
–1
–1
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
60
50
mA
mA
ISB1
Automatic CE
Power-Down Current VIN > VIH or
—TTL Inputs
Max. VCC, CE > VIH
10
10
10
10
L
L
V
IN < VIL, f = fMAX
ISB2
Automatic CE
Max. VCC
,
3.0
1.2
3.0
1.2
mA
Power-Down Current CE > VCC – 0.3V,
—CMOS Inputs IN > VCC – 0.3V,
or VIN < 0.3V, f = 0
V
Capacitance[3]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
6
8
pF
pF
COUT
Thermal Resistance[3]
Parameter
Description
Test Conditions
All - Packages
Unit
ΘJA
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
TBD
°C/W
(Junction to Ambient)[3]
ΘJC
Thermal Resistance
(Junction to Case)[3]
TBD
°C/W
Notes:
2. V (min.) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IL
IH
CC
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05464 Rev. *C
Page 3 of 9
PRELIMINARY
CY7C1019D
AC Test Loads and Waveforms
10-ns Devices
12 -ns Devices
Z = 50Ω
R1 480Ω
OUTPUT
5V
OUTPUT
50Ω
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R2
255Ω
30 pF
1.5V
INCLUDING
JIG AND
SCOPE
(a)
(b)
THÉ
Equivalent to:
OUTPUT
VENIN EQUIVALENT
167Ω
High-Z characteristics:
1.73V
R1 480Ω
5V
ALL INPUT PULSES
3.0V
GND
OUTPUT
90%
10%
90%
10%
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
≤ 3 ns
≤ 3ns
(c)
Switching Characteristics Over the Operating Range [5]
7C1019D-10
7C1019D-12
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
[4]
tpower
VCC(typical) to the first access
Read Cycle Time
100
10
100
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
10
12
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
10
5
12
6
0
3
0
0
3
0
5
5
6
6
tPD
10
12
Write Cycle[8, 9]
tWC
tSCE
tAW
tHA
Write Cycle Time
10
8
12
9
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
8
0
0
tSA
0
0
tPWE
7
8
tSD
Data Set-Up to Write End
5
6
Notes:
4. t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
CC
POWER
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
6. t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
HZOE HZCE
HZWE
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document #: 38-05464 Rev. *C
Page 4 of 9
PRELIMINARY
CY7C1019D
Switching Characteristics Over the Operating Range (continued)[5]
7C1019D-10
7C1019D-12
Parameter
tHD
tLZWE
tHZWE
Description
Data Hold from Write End
WE HIGH to Low Z[7]
Min.
Max.
Min.
Max.
Unit
ns
0
3
0
3
ns
WE LOW to High Z[6, 7]
5
6
ns
Data Retention Characteristics Over the Operating Range
Parameter
VDR
Description
Conditions
Min.
Max.
Unit
V
VCC for Data Retention
Data Retention Current
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
2.0
ICCDR
Non-L, Com’l/Ind’l
L-Version Only
3
mA
mA
ns
1.2
V
IN < 0.3V
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[10]
tR
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
> 2V
4.5V
4.5V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Notes:
10. Full device operation requires linear V ramp from V to V
> 50 µs or stable at V > 50 µs.
CC(min.)
CC
DR
CC(min.)
11. Device is continuously selected. OE, CE = V .
IL
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05464 Rev. *C
Page 5 of 9
PRELIMINARY
CY7C1019D
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 3 (WE Controlled, OE LOW)[15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Notes:
14. Data I/O is high impedance if OE = V
.
IH
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05464 Rev. *C
Page 6 of 9
PRELIMINARY
CY7C1019D
Truth Table
CE
H
X
OE
WE
X
I/O0–I/O7
Mode
Power
X
X
L
High Z
High Z
Power-Down
Power-Down
Read
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
X
)
L
H
Data Out
Data In
High Z
)
L
X
H
L
Write
)
L
H
Selected, Outputs Disabled
)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C1019D-10VXC
Package Type
10
V33
V33
32-Lead 400-Mil Molded SOJ (Pb-Free)
32-Lead 400-Mil Molded SOJ (Pb-Free)
32-Lead TSOP Type II (Pb-Free)
Commercial
Industrial
CY7C1019D-10VXI
CY7C1019D-10ZXC
CY7C1019D-10ZXI
CY7C1019D-12VXC
CY7C1019D-12VXI
CY7C1019D-12ZXC
CY7C1019D-12ZXI
ZS32
ZS32
V33
Commercial
Industrial
32-Lead TSOP Type II (Pb-Free)
12
32-Lead 400-Mil Molded SOJ (Pb-Free)
32-Lead 400-Mil Molded SOJ (Pb-Free)
32-Lead TSOP Type II (Pb-Free)
Commercial
Industrial
V33
ZS32
ZS32
Commercial
Industrial
32-Lead TSOP Type II (Pb-Free)
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Package Diagrams
32-Lead (400-Mil) Molded SOJ V33
51-85033-A
51-85033-*B
Document #: 38-05464 Rev. *C
Page 7 of 9
PRELIMINARY
CY7C1019D
Package Diagrams (continued)
32-Lead
TSOP II ZS32
51-85095-**
All product or company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05464 Rev. *C
Page 8 of 9
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY7C1019D
Document History Page
Document Title: CY7C1019D 1-Mbit (128K x 8) Static RAM (Preliminary)
Document Number: 38-05464
Orig. of
REV.
**
ECN NO.
201560
233715
Issue Date
See ECN
See ECN
Change
Description of Change
SWI
Advance Information data sheet for C9 IPP
*A
RKF
DC parameters are modified as per EROS (Spec # 01-2165)
Pb-free offering in the Ordering Information
*B
*C
262950
307598
See ECN
See ECN
RKF
RKF
Added Tpower Spec in Switching Characteristics table
Added Data Retention Characteristics table and waveforms
Shaded Ordering Information
Reduced Speed bins to -10 and -12 ns
Document #: 38-05464 Rev. *C
Page 9 of 9
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明