CY7C1021CV26_05 [CYPRESS]
1-Mbit (64K x 16) Static RAM; 1兆位（ 64K ×16 ）静态RAM
| 型号： | CY7C1021CV26_05 |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mbit (64K x 16) Static RAM |
| 文件： | 总9页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021CV26
1-Mbit (64K x 16) Static RAM
an automatic power-down feature that significantly reduces
power consumption when deselected.
Features
• Temperature Range
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
— Automotive: –40°C to 125°C
• High speed
— tAA = 15 ns
• Optimized voltage range: 2.5V–2.7V
• Low active power: 360 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
• Packages offered: 44-pin TSOP II and 44-Lead (400-Mil)
Molded SOJ
• Offered in both lead-free and non lead-free packages
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
Functional Description
The CY7C1021CV26 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
A4
A3
A2
A1
64K x 16
I/O1–I/O8
RAM Array
512 X 2048
I/O9–I/O16
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Selection Guide[1]
CY7C1021CV26-15
Unit
ns
Maximum Access Time
15
80
10
Maximum Operating Current
Maximum CMOS Standby Current
Note:
mA
mA
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ.)
Cypress Semiconductor Corporation
Document #: 38-05589 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 7, 2005
CY7C1021CV26
Pin Configuration[2]
TSOP II -Top View
44
1
A
4
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
2
7
OE
A
1
BHE
BLE
I/O
A
0
CE
I/O
7
1
16
37
36
35
34
33
I/O
I/O
8
I/O
I/O
2
3
15
14
13
9
10
11
12
13
I/O
V
SS
I/O
4
CC
V
SS
V
V
CC
32
I/O
I/O
I/O
5
6
7
8
12
11
31
30
29
28
I/O
I/O
I/O
14
15
16
I/O
10
9
I/O
WE 17
NC
18
27
26
25
A
A
8
15
19
A
A
14
9
A
13
20
21
22
A
11
10
A
A
12
24
23
NC
NC
Pin Definitions
Pin Name
A0–A15
Pin Number
I/O Type
Description
1–5, 18–21, Input
24–27,
42–44
Address Inputs used to select one of the address locations.
I/O1–I/O16
7–10,
Input/Output
Bidirectional Data I/O lines. Used as input or output lines depending on
operation.
13–16,
29–32,
35–38
NC
22, 23, 28
17
No Connect
Input/Control
No Connects. This pin is not connected to the die.
WE
Write Enable Input, active LOW. When selected LOW, a Write is conducted.
When selected HIGH, a Read is conducted.
CE
6
Input/Control
Input/Control
Input/Control
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH,
deselects the chip.
BHE, BLE
OE
39, 40
41
Byte Write Select Inputs, active LOW. BLE controls I/O8–I/O1, BHE controls
I/O16–I/O9.
Output Enable, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins.
VSS
12, 34
11, 33
Ground
Ground for the device. Should be connected to ground of the system.
VCC
Power Supply Power Supply inputs to the device.
Note:
2. NC pins are not connected on the die.
Document #: 38-05589 Rev. *A
Page 2 of 9
CY7C1021CV26
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current......................................................>200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V
Operating Range
Ambient
DC Voltage Applied to Outputs
Range
Automotive
Temperature
VCC
in High-Z State[3] ......................................–0.5V to VCC+0.5V
–40°C to +125°C
2.5V–2.7V
Electrical Characteristics Over the Operating Range
CY7C1021CV26-15
Parameter
VOH
VOL
VIH
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 1.0 mA
Min.
Max.
Unit
V
2.3
0.4
VCC + 0.3
0.8
V
Input HIGH Voltage
Input LOW Voltage[3]
2.0
–0.3
–3
V
VIL
V
IIX
Input Load Current
GND < VI < VCC
+3
µA
µA
mA
mA
IOZ
Output Leakage Current
Output Short Circuit Current[4]
VCC Operating Supply Current
GND < VI < VCC, Output Disabled
VCC = Max., VOUT = GND
–3
+3
IOS
–300
80
ICC
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
ISB2
Automatic CE Power-Down
Current —TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
15
10
mA
mA
Automatic CE Power-Down
Current —CMOS Inputs
Max. VCC,
CE > VCC – 0.3V, VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
CC = 2.6V
8
8
V
COUT
pF
Thermal Resistance[5]
44-lead
TSOP-II
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
76.92
°C/W
(Junction to Ambient)[5]
ΘJC
Thermal Resistance
(Junction to Case)[5]
15.86
°C/W
Notes:
3. V (min.) = –2.0V and V (max) = V + 0.5V for pulse durations of less than 20 ns.
IL
IH
CC
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05589 Rev. *A
Page 3 of 9
CY7C1021CV26
AC Test Loads and Waveforms[6]
R1
ALL INPUT PULSES
2.6V
GND
1830Ω
90%
10%
90%
10%
2.6 V
OUTPUT
R2
30 pF
1976Ω
Fall Time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
(b)
SCOPE
(a)
2.6V
OUTPUT
High-Z characteristics:
R 317Ω
5 pF
R2
351Ω
(c)
Switching Characteristics Over the Operating Range[7]
CY7C1021CV26-15
Parameter
Read Cycle
tRC
Description
Min.
Max.
Unit
Read Cycle Time
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8, 9]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
15
tOHA
tACE
15
7
tDOE
tLZOE
0
3
0
tHZOE
7
7
tLZCE
tHZCE
[10]
tPU
[10]
tPD
15
7
tDBE
tLZBE
0
tHZBE
7
Write Cycle[11]
tWC
tSCE
tAW
tHA
Write Cycle Time
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
tPWE
tSD
10
8
Data Set-Up to Write End
Data Hold from Write End
tHD
0
Notes:
6. AC characteristics (except High-Z) are tested using the Thevenin load shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
7. Test conditions assume signal transition time of 2.6 ns or less, timing reference levels of 1.3V, input pulse levels of 0 to 2.6V.
8. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
9. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZBE HZCE
HZWE
10. This parameter is guaranteed by design and is not tested.
11. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05589 Rev. *A
Page 4 of 9
CY7C1021CV26
Switching Characteristics Over the Operating Range[7] (continued)
CY7C1021CV26-15
Parameter
tLZWE
tHZWE
tBW
Description
WE HIGH to Low-Z[8]
WE LOW to High-Z[8, 9]
Min.
Max.
Unit
ns
3
7
ns
Byte Enable to End of Write
9
ns
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
I
SB
Notes:
12. Device is continuously selected. OE, CE, BHE and/or BLE = V .
IL
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05589 Rev. *A
Page 5 of 9
CY7C1021CV26
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes:
15. Data I/O is high-impedance if OE or BHE and/or BLE= V
.
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05589 Rev. *A
Page 6 of 9
CY7C1021CV26
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE OE WE BLE BHE
I/O1–I/O8
High-Z
I/O9–I/O16
Mode
Power
H
L
X
L
X
H
X
L
X
L
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
High-Z
Power-down
Read – All bits
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
Data Out
Data Out
High-Z
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
)
L
X
L
L
Data In
Data In
High-Z
High-Z
High-Z
)
L
H
L
Write – Lower bits only
Write – Upper bits only
)
H
X
H
)
L
L
H
X
H
X
X
H
Selected, Outputs Disabled
Selected, Outputs Disabled
)
)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C1021CV26-15ZSE
Package Type
15
Z44
V34
Z44
44-lead TSOP Type II
Automotive
CY7C1021CV26-15VXE
CY7C1021CV26-15ZSXE
44-pin (400-Mil) Molded SOJ (Pb-Free)
44-lead TSOP Type II (Pb-Free)
Document #: 38-05589 Rev. *A
Page 7 of 9
CY7C1021CV26
Package Diagrams
44-pin TSOP II Z44
51-85087-*A
44-Lead (400-Mil) Molded SOJ V34
51-85082-*B
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05589 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1021CV26
Document History Page
Document Title: CY7C1021CV26 1-Mbit (64K x 16) Static RAM
Document Number: 38-05589
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
New datasheet for Automotive
Added Lead-Free Product Information
Included the 44-Lead (400-Mil) Molded SOJ V34 Package
238454
335861
See ECN
See ECN
RKF
SYT
*A
Document #: 38-05589 Rev. *A
Page 9 of 9
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