CY7C1021D-10VXIT [CYPRESS]
1-Mbit (64 K Ã 16) Static RAM; 1兆位（ 64 K A ?? 16 ）静态RAM
| 型号： | CY7C1021D-10VXIT |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mbit (64 K Ã 16) Static RAM |
| 文件： | 总16页 (文件大小：521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021D
1-Mbit (64 K × 16) Static RAM
1-Mbit (64
K × 16) Static RAM
Features
Functional Description
■ Temperature Ranges:
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
The CY7C1021D is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected. The input and output pins (IO0
through IO15) are placed in a high impedance state when the
device is deselected (CE HIGH), outputs are disabled (OE
HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during
a write operation (CE LOW and WE LOW).
■ Pin and Function Compatible with CY7C1021B
■ High Speed
❐ tAA = 10 ns
■ Low Active Power
❐ ICC = 80 mA at 10 ns
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A15). If Byte High
■ Low CMOS Standby Power
❐ ISB2 = 3 mA
Enable (BHE) is LOW, then data from I/O pins (IO8 through IO15
)
is written into the location specified on the address pins (A0
through A15).
■ 2.0 V Data Retention
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Independent Control of Upper and Lower Bits
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the Truth Table on page 10 for a
complete description of read and write modes.
■ Available in Pb-free 44-pin 400-Mil Wide Molded SOJ and
44-pin TSOP II Packages
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
64K x 16
A4
IO0–IO7
RAM Array
A3
A2
A1
A0
IO8–IO15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05462 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 6, 2012
CY7C1021D
Contents
Pin Configuration .............................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Switching Characteristics ................................................6
Data Retention Characteristics .......................................7
Data Retention Waveform ................................................7
Switching Waveforms ......................................................7
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagrams ..........................................................12
Acronyms ........................................................................14
Document Conventions .................................................14
Units of Measure .......................................................14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................16
Worldwide Sales and Design Support .......................16
Products ....................................................................16
PSoC Solutions .........................................................16
Document Number: 38-05462 Rev. *K
Page 2 of 16
CY7C1021D
Pin Configuration
Figure 1. 44-pin SOJ / 44-pin TSOP II (Top View) [1]
A
A
A
A
A
A
A
A
7
OE
BHE
BLE
IO
15
IO
IO
13
IO
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
2
1
0
5
6
CE
IO
0
1
2
3
IO
IO
IO
V
14
9
10
11
12
13
14
15
16
12
V
SS
CC
V
SS
V
CC
IO
IO
IO
4
5
6
7
11
10
IO
IO
IO
IO
9
IO
8
NC
WE 17
A
15
A
14
A
13
A
12
18
19
20
21
22
A
8
A
9
A
10
A
11
NC
NC
Selection Guide
-10 (Industrial /
Automotive-A)
Description
Unit
Maximum Access Time
10
80
3
ns
Maximum Operating Current
Maximum CMOS Standby Current
mA
mA
Note
1. NC pins are not connected on the die.
Document Number: 38-05462 Rev. *K
Page 3 of 16
CY7C1021D
DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Storage Temperature ............................... –65 C to +150 C
Latch Up Current ...................................................> 200 mA
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Operating Range
Supply Voltage on
V
Ambient
Temperature
CC to Relative GND[2] ................................–0.5 V to +6.0 V
Range
VCC
Speed
DC Voltage Applied to Outputs
Industrial
–40 C to +85 C
5 V 10%
10 ns
in High Z State [2] ................................–0.5 V to VCC + 0.5 V
Automotive-A
Electrical Characteristics
Over the Operating Range
-10 (Industrial /
Automotive-A)
Parameter
Description
Test Conditions
Unit
Min
2.4
–
Max
–
VOH
VOL
VIH
VIL
IIX
Output HIGH Voltage
Output LOW Voltage
IOH = –4.0 mA
IOL = 8.0 mA
V
V
0.4
Input HIGH Voltage
2.2
0.5
1
1
–
VCC + 0.5 V
V
Input LOW Voltage [2]
Input Leakage Current
Output Leakage Current
VCC Operating Supply Current
0.8
+1
+1
80
72
58
37
10
V
GND < VI < VCC
A
A
mA
mA
mA
mA
mA
IOZ
ICC
GND < VI < VCC, Output Disabled
VCC = Max, IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz
83 MHz
66 MHz
40 MHz
–
–
–
ISB1
ISB2
Automatic CE Power Down
Current –TTL Inputs
Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax
–
Automatic CE Power Down
Current – CMOS Inputs
Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or
–
3
mA
VIN < 0.3 V, f = 0
Note
2.
V (min) = –2.0 V and V (max) = V + 1 V for pulse durations of less than 5 ns.
IL IH CC
Document Number: 38-05462 Rev. *K
Page 4 of 16
CY7C1021D
Capacitance
Parameter [3]
Description
Test Conditions
TA = 25C, f = 1 MHz, VCC = 5.0 V
Max
8
Unit
pF
CIN
Input capacitance
COUT
Output capacitance
8
pF
Thermal Resistance
Parameter [3]
Description
Test Conditions
44-pin SOJ 44-pin TSOP II Unit
JA
Thermal resistance
(junction to ambient)
Still Air, solderedona 3 × 4.5 inch, four-layer
printed circuit board
59.52
53.91
C/W
JC
Thermal resistance
(junction to case)
36.75
21.24
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
ALL INPUT PULSES
3.0 V
Z = 50
90%
10%
90%
10%
OUTPUT
50
1.5 V
GND
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Fall Time: 3 ns
Rise Time: 3 ns
(b)
(a)
High-Z characteristics:
R1 480
5 V
OUTPUT
R2
255
5 pF
INCLUDING
JIG AND
SCOPE
(c)
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load
shown in Figure 2 (c).
Document Number: 38-05462 Rev. *K
Page 5 of 16
CY7C1021D
Switching Characteristics
Over the Operating Range
-10 (Industrial /
Automotive-A)
Parameter [5]
Description
Unit
Min
Max
Read Cycle
[6]
tpower
tRC
VCC(typical) to the first access
100
10
–
–
–
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z [7]
OE HIGH to High Z [7, 8]
CE LOW to Low Z [7]
CE HIGH to High Z [7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
10
–
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
–
10
5
–
0
–
–
5
3
–
–
5
0
–
tPD
–
10
5
tDBE
tLZBE
tHZBE
Write Cycle [9]
tWC
–
0
–
–
5
Write Cycle Time
10
7
7
0
0
7
6
0
3
–
7
–
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tHA
tSA
tPWE
tSD
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z [7]
WE LOW to High Z [7, 8]
Byte Enable to End of Write
tHD
tLZWE
tHZWE
tBW
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I /I
OL OH
and 30-pF load capacitance.
t gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
POWER
6.
7. At any given temperature and voltage condition, t
CC
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8.
t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high impedance
HZOE HZBE HZCE
HZWE
state.
9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and
the transition of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates
the write.
Document Number: 38-05462 Rev. *K
Page 6 of 16
CY7C1021D
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Conditions
Min
2.0
–
Max
–
Unit
V
Data Retention Current
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
IN > VCC – 0.3 V or VIN < 0.3 V
3
mA
V
[10]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
–
–
ns
ns
[11]
tR
tRC
Data Retention Waveform
DATA RETENTION MODE
DR > 2 V
4.5 V
4.5 V
V
V
CC
t
t
R
CDR
CE
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [12, 13]
tRC
ADDRESS
DATA OUT
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
Notes
10. V (min) = –2.0 V and V (max) = V + 1 V for pulse durations of less than 5 ns.
IL
IH
CC
11. Full device operation requires linear V ramp from V to V
> 50 s or stable at V
> 50 s.
CC
DR
CC(min)
CC(min)
12. Device is continuously selected. OE, CE, BHE and/or BLE = V .
IL
13. WE is HIGH for read cycle.
Document Number: 38-05462 Rev. *K
Page 7 of 16
CY7C1021D
Switching Waveforms (continued)
Figure 4. Read Cycle No. 2 (OE Controlled) [14, 15]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE, BLE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
VCC
SUPPLY
CURRENT
50%
50%
ISB
Notes
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05462 Rev. *K
Page 8 of 16
CY7C1021D
Switching Waveforms (continued)
Figure 5. Write Cycle No. 1 (CE Controlled) [16, 17]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Figure 6. Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
BHE, BLE
t
SA
t
BW
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes
16. Data I/O is high impedance if OE or BHE and/or BLE = V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05462 Rev. *K
Page 9 of 16
CY7C1021D
Switching Waveforms (continued)
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE
H
OE
X
WE
X
BLE BHE
IO0–IO7
High Z
IO8–IO15
High Z
Mode
Power
X
L
X
L
Power Down
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
L
L
H
Data Out
Data Out
High Z
Data Out
High Z
Read – All bits
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
Data Out
Data In
High Z
)
L
X
L
L
Data In
Data In
High Z
)
L
H
L
Write – Lower bits only
Write – Upper bits only
)
H
X
H
Data In
High Z
)
L
L
H
X
H
X
X
H
High Z
Selected, Outputs Disabled Active (ICC
)
High Z
High Z
Selected, Outputs Disabled Active (ICC)
Document Number: 38-05462 Rev. *K
Page 10 of 16
CY7C1021D
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
10
CY7C1021D-10VXI
CY7C1021D-10ZSXI
CY7C1021D-10ZSXA
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
Industrial
Automotive-A
Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 7
C
1 02
1
D - 10 XX
X
X
Temperature Range: X = I or A
I = Industrial; A = Automotive-A
Pb-free
Package Type: XX = V or ZS
V = 44-pin Molded SOJ
ZS = 44-pin TSOP Type II
Speed: 10 ns
D = C9, 90 nm Technology
1 = Data width × 16-bits
02 = 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05462 Rev. *K
Page 11 of 16
CY7C1021D
Package Diagrams
Figure 8. 44-pin SOJ (400 Mils) V44.4 Package Outline, 51-85082
51-85082 *D
Document Number: 38-05462 Rev. *K
Page 12 of 16
CY7C1021D
Package Diagrams (continued)
Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *D
Document Number: 38-05462 Rev. *K
Page 13 of 16
CY7C1021D
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
chip enable
Symbol
°C
Unit of Measure
CMOS
I/O
complementary metal oxide semiconductor
input/output
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
nanosecond
ohm
MHz
µA
µs
OE
output enable
SOJ
SRAM
TSOP
TTL
small outline J-lead
static random access memory
thin small outline package
transistor-transistor logic
write enable
mA
mm
ms
ns
WE
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 38-05462 Rev. *K
Page 14 of 16
CY7C1021D
Document History Page
Document Title: CY7C1021D, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05462
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
201560
233695
SWI
RKF
See ECN Advance Information data sheet for C9 IPP
*A
See ECN DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in the Ordering Information
*B
263769
RKF
See ECN Added Data Retention Characteristics Table
Added Tpower Spec in Switching Characteristics Table
Shaded Ordering Information
*C
*D
307601
520647
RKF
VKN
See ECN Reduced Speed bins to –10 and –12 ns
See ECN Changed status from Preliminary to Final.
Removed Commercial Operating range
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Added Automotive Product Information
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4
*E
*F
802877
VKN
See ECN Changed Commercial operating range ICC spec from 60 mA to 80 mA for
100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to
37 mA for 40MHz
Changed Automotive operating range ICC spec from 100 mA to 120 mA for
83MHz, 90 mA to 100 mA for 66MHz, 60 mA to 63 mA for 40MHz
2751755
VKN /
PYRS
08/14/09
For 12 ns speed, changed ICC spec from 120 mA to 90 mA
For 12 ns speed, changed ISB1 spec from 50 mA to 10 mA and ISB2 spec from
15 mA to 10 mA
*G
*H
*I
2898399
3109897
3245199
AJU
AJU
03/24/2010 Updated Package Diagrams.
12/14/2010 Added Ordering Code Definitions.
PRAS
04/30/2011 Dislodged Automotive information to new datasheet (001-68372).
Removed the Note “Automotive Product Information is Preliminary.” in page 3.
Added Acronyms and Units of Measure.
Updated in new template.
*J
3086499
AJU
06/07/2011 Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
*K
3540685 TAVA / AJU 03/06/2012 Updated Features (Included Automotive-A Range information).
Updated Selection Guide (Included Automotive-A Range information).
Updated Operating Range (Included Automotive-A Range information).
Updated Electrical Characteristics (Included Automotive-A Range
information).
Updated Switching Characteristics (Included Automotive-A Range
information).
Updated Ordering Information (included the part number
CY7C1021D-10ZSXA).
Updated Package Diagrams.
Document Number: 38-05462 Rev. *K
Page 15 of 16
CY7C1021D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05462 Rev. *K
Revised March 6, 2012
Page 16 of 16
All products and company names mentioned in this document may be the trademarks of their respective holders.
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