CY7C1041B-25VI [CYPRESS]
256K x 16 Static RAM; 256K ×16静态RAM
| 型号： | CY7C1041B-25VI |
| 厂家： | 
CYPRESS |
| 描述： | 256K x 16 Static RAM |
| 文件： | 总10页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C1041B
CY7C1041B
256K x 16 Static RAM
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Features
• High speed
— tAA = 12 ns
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
• Low active power
— 1540 mW (max.)
• Low CMOS standby power (L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1041B is a high-performance CMOS static RAM or-
ganized as 262,144 words by 16 bits.
The CY7C1041B is available in
a
standard 44-pin
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
INPUT BUFFER
A
0
44
1
A
A
A
A
OE
BHE
BLE
I/O
I/O
I/O
0
17
16
15
A
43
42
41
40
39
38
1
A
2
3
4
5
6
1
A
2
A
2
I/O – I/O
256K x 16
ARRAY
0
7
A
3
4
A
3
A
A
4
1024 x 4096
A
I/O – I/O
5
6
8
15
CE
A
I/O
7
0
15
A
7
8
37
36
35
34
33
I/O
I/O
8
1
2
14
13
12
A
9
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
COLUMN
DECODER
V
V
CC
I/O
32
31
30
29
28
27
I/O
I/O
4
5
6
7
11
10
I/O
I/O
I/O
14
15
16
I/O
I/O
NC
9
8
WE 17
18
BHE
A
A
14
A
13
A
12
A
11
5
WE
CE
OE
19
20
21
22
26
25
A
6
A
7
BLE
A
24
23
8
9
A
A
10
1041B–1
1041B–2
Selection Guide
7C1041B-12 7C1041B-15 7C1041B-17 7C1041B-20 7C1041B-25
Maximum Access Time (ns)
Maximum Operating Current (mA) Com’l
Ind’l
12
200
220
3
15
190
210
3
17
180
200
3
20
170
190
3
25
160
180
3
Maximum CMOS Standby Current Com’l
(mA)
Com’l
L
-
0.5
6
0.5
6
0.5
6
0.5
6
Ind’l
-
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 23, 2001
CY7C1041B
DC Input Voltage[1]–0.5V to VCC + 0.5V
Current into Outputs (LOW)20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature –65°C to +150°C
Ambient Temperature with
Power Applied–55°C to +125°C
Supply Voltage on VCC to Relative GND[1]–0.5V to +7.0V
Ambient
Range
Commercial
Industrial
Temperature[2]
0°C to +70°C
VCC
5V ± 0.5
DC Voltage Applied to Outputs
–40°C to +85°C
in High Z State[1]–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C1041B-12
7C1041B-15
7C1041B-17
Parameter
VOH
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max. Unit
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
Input HIGH Voltage
2.4
2.4
2.4
V
VOL
0.4
0.4
0.4
V
V
VIH
2.2
VCC
2.2
VCC
2.2
VCC
+ 0.5
+ 0.5
+ 0.5
VIL
IIX
Input LOW Voltage[1]
–0.5
–1
0.8
+1
+1
–0.5
–1
0.8
+1
+1
–0.5
–1
0.8
+1
+1
V
Input Load Current
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Com’l
Ind’l
200
220
40
190
210
40
180
200
40
mA
mA
mA
ISB1
Automatic CE
Max. VCC, CE > VIH
Power-Down Current VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current CE > VCC – 0.3V,
—CMOS Inputs VIN > VCC – 0.3V,
Max. VCC
,
Com’l
Com’l
3
-
3
0.5
6
3
0.5
6
mA
mA
mA
L
or VIN < 0.3V, f = 0 Ind’l
-
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the case temperature.
2
CY7C1041B
Electrical Characteristics Over the Operating Range (continued)
Test Conditions
7C1041B-20
7C1041B-25
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Min.
Max.
Min.
Max.
Unit
V
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
2.4
2.4
VOL
VIH
0.4
0.4
V
2.2
VCC
2.2
VCC + 0.5
V
+ 0.5
VIL
IIX
Input LOW Voltage[1]
Input Load Current
–0.5
–1
0.8
+1
+1
–0.5
–1
0.8
+1
+1
V
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Com’l
Ind’l
170
190
40
160
180
40
mA
mA
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
,
Com’l
Com’l
Ind’l
3
0.5
6
3
0.5
6
mA
mA
mA
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
L
Capacitance[3]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
CIN
Input Capacitance
I/O Capacitance
8
8
pF
pF
COUT
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
3.0V
GND
90%
10%
OUTPUT
10%
R2
255Ω
R2
255Ω
30 pF
5 pF
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
1041B–3
(a)
1041B–4
THÉ
Equivalent to:
VENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
3
CY7C1041B
Switching Characteristics[4] Over the Operating Range
7C1041B-12
7C1041B-15
7C1041B-17
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tpower
tRC
VCC(typical) to the First Access[5]
1
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
12
15
17
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
12
15
17
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
3
12
6
15
7
17
7
0
3
0
0
3
0
0
3
0
6
6
7
7
7
7
tPD
12
6
15
7
17
7
tDBE
tLZBE
tHZBE
0
0
0
6
7
7
WRITE CYCLE[8, 9]
tWC
tSCE
tAW
Write Cycle Time
12
10
10
0
15
12
12
0
17
14
14
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
tPWE
tSD
10
7
12
8
14
8
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
0
0
tLZWE
tHZWE
3
3
3
WE LOW to High Z[6, 7]
6
7
7
tBW
Byte Enable to End of Write
10
12
12
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation
is started.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
4
CY7C1041B
Switching Characteristics[4] Over the Operating Range (continued)
7C1041B-20
7C1041B-25
Parameter
READ CYCLE
tpower
tRC
Description
Min.
Max.
Min.
Max.
Unit
VCC(typical) to the First Access[5]
Read Cycle Time
1
1
1
20
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
20
25
tOHA
3
5
tACE
20
8
25
10
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
5
0
8
8
10
10
tPD
20
8
25
10
tDBE
tLZBE
0
0
tHZBE
8
10
WRITE CYCLE[8, 9]
tWC
tSCE
tAW
Write Cycle Time
20
13
13
0
25
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
13
9
15
10
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
tLZWE
tHZWE
tBW
3
5
WE LOW to High Z[6, 7]
8
10
Byte Enable to End of Write
13
15
Data Retention Characteristics Over the Operating Range (L version only)
Parameter
VDR
Description
VCC for Data Retention
Data Retention Current
Conditions[11]
Min.
Max.
Unit
V
2.0
ICCDR
Com’l
L
VCC = VDR = 3.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
200
µA
ns
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[10]
tR
tRC
ns
Notes:
10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds.
11. No input may exceed VCC + 0.5V.
5
CY7C1041B
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
DR
CC
t
t
R
CDR
CE
1041B–5
Switching Waveforms
[12, 13]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1041B-6
Read Cycle No. 2 (OEControlled) [13, 14]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
1041B-7
Notes:
12. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
6
CY7C1041B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATAI/O
1041B-8
Write Cycle No. 2 (BLEor BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
1041B-9
Notes:
15. Data I/O is high impedance if OE or BHE and/or BLE= VIH
.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
7
CY7C1041B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOOEW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
1041B-10
Truth Table
CE
H
L
OE WE BLE
BHE
X
I/O0–I/O7
High Z
I/O8–I/O15
Mode
Power
X
L
X
H
H
H
L
X
L
High Z
Power Down
Read All bits
Standby (ISB)
L
Data Out
Data Out
High Z
Data Out
High Z
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
L
H
L
Read Lower bits only
Read Upper bits only
Write All bits
L
L
H
L
Data Out
Data In
High Z
L
X
X
X
H
L
Data In
Data In
High Z
L
L
L
H
L
Write Lower bits only
Write Upper bits only
Selected, Outputs Disabled
L
L
H
X
Data In
High Z
L
H
X
High Z
8
CY7C1041B
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
12
CY7C1041B-12VC
CY7C1041B-12ZC
CY7C1041B-15VC
CY7C1041BL-15VC
CY7C1041B-15ZC
CY7C1041BL-15ZC
CY7C1041B-17VC
CY7C1041BL-17VC
CY7C1041B-17ZC
CY7C1041BL-17ZC
CY7C1041B-20VC
CY7C1041BL-20VC
CY7C1041B-20ZC
CY7C1041BL-20ZC
CY7C1041B-25VC
CY7C1041BL-25VC
CY7C1041B-25ZC
CY7C1041BL-25ZC
CY7C1041B-15ZI
CY7C1041B-15VI
CY7C1041B-17ZI
CY7C1041B-17VI
CY7C1041B-20ZI
CY7C1041B-20VI
CY7C1041B-25ZI
CY7C1041B-25VI
V34
Z44
V34
V34
Z44
Z44
V34
V34
Z44
Z44
V34
V34
Z44
Z44
V34
V34
Z44
Z44
Z44
V34
V34
Z44
Z44
Z44
Z44
Z44
Commercial
15
17
20
25
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
15
17
20
25
44-Lead TSOP Type II
Industrial
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
Document #: 38-00938-*B
9
CY7C1041B
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
44-Pin TSOP II Z44
51-85087-A
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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