CY7C1041CV33-20BAI [CYPRESS]
256K x 16 Static RAM; 256K ×16静态RAM
| 型号： | CY7C1041CV33-20BAI |
| 厂家： | 
CYPRESS |
| 描述： | 256K x 16 Static RAM |
| 文件： | 总11页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1041CV33
256K x 16 Static RAM
HIGH Enable (BHE) is LOW, then data from I/O pins
(I/O8–I/O15) is written into the location specified on the
address pins (A0–A17).
Features
• Pin equivalent to CY7C1041BV33
• High speed
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of Read and Write modes.
— tAA = 10 ns
• Low active power
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The input/output pins (I/O0–I/O15
)
are placed in
a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
Functional Description[1]
The CY7C1041CV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
The CY7C1041CV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable
(BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written
into the location specified on the address pins (A0–A17). If Byte
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
INPUT BUFFER
44
1
A
A
A
A
OE
BHE
BLE
0
17
16
15
A
0
A
1
43
42
41
40
39
38
A
2
3
4
5
6
1
A
2
A
2
A
3
I/O –I/O
256K × 16
ARRAY
0
7
A
3
4
A
4
A
CE
1024 x 4096
A
I/O –I/O
8 15
5
6
I/O
I/O
7
0
15
A
37
36
35
34
33
I/O
I/O
8
I/O
I/O
1
2
14
13
12
A
8
7
9
A
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
V
V
CC
COLUMN
DECODER
32
I/O
I/O
I/O
4
5
6
7
11
10
I/O
I/O
I/O
31
30
29
28
14
15
16
I/O
9
8
I/O
WE 17
18
NC
27
26
25
BHE
WE
CE
OE
BLE
A
14
A
5
19
20
21
22
A
A
13
A
12
A
11
6
A
7
A
24
23
8
9
A
A
10
Selection Guide
-8
-10
10
-12
12
85
95
10
-15
15
80
90
10
-20
20
75
85
10
Unit
ns
Maximum Access Time
8
Maximum Operating Current
Commercial
Industrial
100
110
10
90
mA
mA
mA
100
10
Maximum CMOS Standby Current
Commercial/
Industrial
Shaded areas contain advance information.
Note:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05134 Rev. *D
Revised October 18, 2002
CY7C1041CV33
Pin Configurations
48-ball Mini FBGA
(Top View)
1
2
4
3
5
6
A
A
A
2
NC
OE
BLE
0
1
A
B
C
I/O
0
A
A
4
BHE
CE
I/O
I/O
8
3
I/O
2
A
A
6
I/O
1
I/O
9
5
10
I/O
11
A
I/O
3
V
V
A
CC
D
E
F
SS
7
17
A
V
CC
NC
V
I/O
4
I/O
12
SS
16
I/O
A
A
I/O
13
I/O
5
I/O
6
14
14
15
A
I/O
15
A
G
H
I/O
7
NC
WE
13
12
A
A
9
A
A
8
NC
NC
10
11
Document #: 38-05134 Rev. *D
Page 2 of 11
CY7C1041CV33
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 0.3V
DC Voltage Applied to Outputs
in High-Z State[2]....................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
-8
-10
-12
-15
-20
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage VCC = Min.,
2.4
2.4
2.4
2.4
2.4
V
V
V
V
IOH = –4.0 mA
VOL
VIH
Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
0.4
0.4
Input HIGH Voltage
2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC
+ 0.3 + 0.3 + 0.3 + 0.3 + 0.3
[2]
VIL
Input LOW Voltage
–0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8
IIX
Input Load Current
GND < VI < VCC
–1 +1 –1 +1 –1 +1 –1 +1 –1 +1 µA
–1 +1 –1 +1 –1 +1 –1 +1 –1 +1 µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX = Comm’l
100
110
40
90
100
40
85
95
40
80
90
40
75 mA
85 mA
40 mA
1/tRC
Indus.
ISB1
Automatic CE
Max. VCC, CE > VIH
Power-down Current VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current CE > VCC – 0.3V,
Max. VCC
,
Comm’l
Indus.
10
10
10
10
10 mA
—CMOS Inputs
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Shaded areas contain advance information.
Capacitance[3]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
CIN
Input Capacitance
I/O Capacitance
8
8
pF
pF
COUT
Notes:
2. Minimum voltage is–2.0V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05134 Rev. *D
Page 3 of 11
CY7C1041CV33
AC Switching Characteristics[4] Over the Operating Range
-8
-10
-12
-15
-20
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
[5]
tpower
VCC(typical) to the first access
Read Cycle Time
1
8
1
1
1
1
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
10
12
15
20
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z[6, 7]
CE LOW to Low-Z[7]
CE HIGH to High-Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
8
10
12
15
20
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
3
3
3
8
4
10
5
12
6
15
7
20
8
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
4
4
5
5
6
6
7
7
8
8
tPD
8
4
10
5
12
6
15
7
20
8
tDBE
tLZBE
tHZBE
0
0
0
0
0
6
6
6
7
8
Write Cycle[8, 9]
tWC
tSCE
tAW
Write Cycle Time
8
6
6
0
0
6
4
0
3
10
7
12
8
15
10
10
0
20
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
8
tHA
0
0
tSA
0
0
0
0
tPWE
tSD
7
8
10
7
10
8
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low-Z[7]
5
6
tHD
0
0
0
0
tLZWE
tHZWE
tBW
3
3
3
3
WE LOW to High-Z[6, 7]
4
5
6
7
8
Byte Enable to End of Write
6
7
8
10
10
Shaded areas contain advance information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. POWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
t
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05134 Rev. *D
Page 4 of 11
CY7C1041CV33
AC Test Loads and Waveforms[10]
12-, 15-, 20-ns Devices
8-, 10-ns Devices
R 317Ω
Z = 50Ω
3.3V
OUTPUT
OUTPUT
30 pF
50Ω
30 pF*
R2
351Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(b)
(a)
High-Z Characteristics
R 317Ω
3.3V
OUTPUT
5 pF
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
R2
GND
351Ω
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(d)
Switching Waveforms
[11, 12]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2(OEControlled) [12, 13]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
CC
PU
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
10. AC characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the
Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL
.
12. WE is HIGH for Read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05134 Rev. *D
Page 5 of 11
CY7C1041CV33
Switching Waveforms (continued)
[14, 15]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATAI/O
Write Cycle No. 2 (BLEor BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
Notes:
14. Data I/O is high-impedance if OE or BHE and/or BLE = VIH
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05134 Rev. *D
Page 6 of 11
CY7C1041CV33
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE
H
L
OE WE BLE
BHE
X
I/O0–I/O7
High-Z
I/O8–I/O15
Mode
Power
X
L
X
H
H
H
L
X
L
High-Z
Power-down
Read All Bits
Standby (ISB)
L
Data Out
Data Out
High-Z
Data Out
High-Z
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
L
H
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
L
H
L
Data Out
Data In
High-Z
L
X
X
X
H
L
Data In
Data In
High-Z
L
L
L
H
L
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
L
H
X
Data In
High-Z
L
H
X
High-Z
Document #: 38-05134 Rev. *D
Page 7 of 11
CY7C1041CV33
Ordering Information
CY7C1041CV33
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
48-ball Fine Pitch BGA
10
CY7C1041CV33-10BAC
CY7C1041CV33-10VC
CY7C1041CV33-10ZC
CY7C1041CV33-10BAI
CY7C1041CV33-10VI
CY7C1041CV33-10ZI
CY7C1041CV33-12BAC
CY7C1041CV33-12VC
CY7C1041CV33-12ZC
CY7C1041CV33-12BAI
CY7C1041CV33-12VI
CY7C1041CV33-12ZI
CY7C1041CV33-15BAC
CY7C1041CV33-15VC
CY7C1041CV33-15ZC
CY7C1041CV33-15BAI
CY7C1041CV33-15VI
CY7C1041CV33-15ZI
CY7C1041CV33-20BAC
CY7C1041CV33-20VC
CY7C1041CV33-20ZC
CY7C1041CV33-20BAI
CY7C1041CV33-20VI
CY7C1041CV33-20ZI
BA48B
V34
Commercial
44-lead (400-mil) Molded SOJ
44-pin TSOP II Z44
Z44
BA48B
V34
48-ball Fine Pitch BGA
44-lead (400-mil) Molded SOJ
44-pin TSOP II Z44
Industrial
Z44
12
15
20
BA48B
V34
48-ball Fine Pitch BGA
44-lead (400-mil) Molded SOJ
44-pin TSOP II Z44
Commercial
Industrial
Z44
BA48B
V34
48-ball Fine Pitch BGA
44-lead (400-mil) Molded SOJ
44-pin TSOP II Z44
Z44
BA48B
V34
48-ball Fine Pitch BGA
44-lead (400-mil) Molded SOJ
44-pin TSOP II Z44
Commercial
Industrial
Z44
BA48B
V34
48-ball Fine Pitch BGA
44-lead (400-mil) Molded SOJ
44-pin TSOP II Z44
Z44
BA48B
V34
48-ball Fine Pitch BGA
44-lead (400-mil) Molded SOJ
44-pin TSOP II Z44
Commercial
Industrial
Z44
BA48B
V34
48-ball Fine Pitch BGA
44-lead (400-mil) Molded SOJ
44-pin TSOP II Z44
Z44
Document #: 38-05134 Rev. *D
Page 8 of 11
CY7C1041CV33
Package Diagrams
48-ball (7.00 mm x 8.5 mm x 1.2 mm) FBGA BA48B
51-85106-*D
44-lead (400-mil) Molded SOJ V34
51-85082-*B
Document #: 38-05134 Rev. *D
Page 9 of 11
CY7C1041CV33
Package Diagrams (continued)
44-pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05134 Rev. *D
Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1041CV33
Document History Page
Document Title: CY7C1041CV33 256K x 16 Static RAM
Document Number: 38-05134
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109513
112440
112859
Description of Change
12/13/01
12/20/01
03/25/02
HGK
BSS
DFP
New Data Sheet
*A
Updated 51-85106 from revision *A to *C
Added CY7C1042CV33 in BGA package
*B
Removed 1042 BGA option pin ACC Final Data Sheet
Add applications foot note to data sheet
Added 20-ns speed bin
*C
*D
116477
119797
09/16/02
10/21/02
CEA
DFP
Document #: 38-05134 Rev. *D
Page 11 of 11
相关型号：
©2020 ICPDF网 联系我们和版权申明