CY7C1041CV33-20VXET [CYPRESS]
Standard SRAM, 256KX16, CMOS, PDSO44;
| 型号： | CY7C1041CV33-20VXET |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX16, CMOS, PDSO44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1041CV33
4-Mbit (256K x 16) Static RAM
Features
Functional Description
■ Temperature ranges
The CY7C1041CV33 is a high performance CMOS static RAM
organized as 262,144 words by 16 bits.
❐ Commercial: 0°C to 70°C
❐ Industrial: –40°C to 85°C
❐ Automotive-A: –40°C to 85°C
❐ Automotive-E: –40°C to 125°C
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A17). If Byte High
■ Pin and function compatible with CY7C1041BV33
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15
)
is written into the location specified on the address pins (A0
through A17).
■ High speed
❐ tAA = 10 ns (Commercial, Industrial and Automotive-A)
❐ tAA = 12 ns (Automotive-E)
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. For more information, see the Truth
Table on page 9 for a complete description of Read and Write
modes.
■ Low active power
❐ 324 mW (max)
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
The input and output pins (IO0 through IO15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
■ AvailableinPb-freeandnonPb-free44-pin400MilSOJ, 44-pin
TSOP II and 48-Ball FBGA packages
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
INPUT BUFFER
A
A
0
1
A
A
A
A
2
3
4
5
256K x 16
RAM Array
IO –IO
0
7
A
A
A
6
7
8
IO –IO
8
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05134 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 14, 2008
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CY7C1041CV33
Selection Guide
Description
-10
10
-12
12
85
95
-15
15
80
90
-20
20
75
85
85
90
10
Unit
ns
Maximum Access Time
Maximum Operating Current
Commercial
Industrial
90
mA
mA
mA
mA
mA
100
100
Automotive-A
Automotive-E
120
10
Maximum CMOS Standby Current
Commercial/
Industrial
10
10
10
Automotive-A
Automotive-E
10
15
mA
mA
15
Pin Configuration
Figure 1. 44-Pin SOJ/TSOP II (Top View) [1]
Figure 2. 48-Ball FBGA Pinout (Top View) [1]
A
A
A
A
A
A
A
A
1
2
3
4
5
6
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
0
1
2
3
4
17
16
15
A0
A1
A2
NC
A
B
C
OE
BHE
IO2
IO3
IO4
IO5
NC
A8
BLE
IO0
OE
BHE
BLE
IO
15
IO
14
IO
A4
A6
A7
A3
A5
IO8
CE
CE
IO
0
IO
1
IO1
VSS
VCC
IO10 IO9
IO
9
2
13
IO
3
IO
V
10
11
12
13
14
15
16
12
VCC
IO11
D
E
F
A17
NC
A14
V
CC
SS
V
SS
V
CC
IO
IO
A16 IO12 VSS
A15
IO
4
5
6
7
11
10
IO
IO
IO
IO
IO
IO13 IO14
9
IO6
IO7
NC
8
NC
WE 17
A12 A13
IO15
NC
WE
G
H
A
5
A
6
A
7
A
8
18
19
20
21
22
A
14
A
13
A
12
A9 A10 A11
A
11
A
A
10
9
Note
1. NC pins are not connected on the die.
Document Number: 38-05134 Rev. *I
Page 2 of 14
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CY7C1041CV33
Pin Definitions
SOJ, TSOP
Pin Number
BGA
Pin Name
IO Type
Description
Address Inputs. Used to select one of the address locations.
Pin Number
A0–A17
1–5, 18–27, A3, A4, A5, B3,
Input
42–44
B4, C3, C4,
D4, H2, H3, H4,
H5, G3, G4, F3,
F4, E4, D3
IO0–IO15
7–10,13–16, B1, C1, C2, D2, Input or Output Bidirectional DataIOlines. Usedas input or output lines depending
29–32, 35–38 E2, F2, F1, G1,
B6, C6, C5, D5,
on operation.
E5, F5, F6, G6
NC
WE
28
17
A6, E3, G2, H1, No Connect No Connects. Not connected to the die.
H6
G5
Input or
Control
Write Enable Input, Active LOW. When selected LOW, a write is
conducted. When deselected HIGH, a read is conducted.
CE
6
B5
Input or
Control
Chip Enable Input, Active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
BHE, BLE
OE
40, 39
41
B2, A1
A2
Input or
Control
Byte Write Select Inputs, Active LOW. BHE controls IO16 – IO9,
BLE controls IO8 – IO1.
Input or
Control
Output Enable, Active LOW. Controls the direction of the IO pins.
When LOW, the IO pins are allowed to behave as outputs. When
deasserted HIGH, the IO pins are tri-stated and act as input data
pins.
VSS
VCC
12, 34
11, 33
D1, E6
D6, E1
Ground
Ground for the Device. Connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Document Number: 38-05134 Rev. *I
Page 3 of 14
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CY7C1041CV33
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch Up Current..................................................... >200 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient
Temperature (TA)
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Range
VCC
Supply Voltage on VCC Relative to GND[2].....–0.5V to +4.6V
Commercial
0°C to +70°C
3.3V ± 10%
Industrial
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
DC Voltage Applied to Outputs
in High Z State[2]...................................... –0.5V to VCC+0.5V
Automotive-A
Automotive -E
DC Input Voltage[2] .................................. –0.5V to VCC+0.5V
Current into Outputs (LOW)......................................... 20 mA
Electrical Characteristics
Over the Operating Range
-10
-12
-15
-20
Parameter
Description
Test Conditions
Unit
Min Max Min Max Min Max Min Max
2.4 2.4 2.4 2.4
VOH
VOL
VIH
Output HIGH Voltage VCC = Min, IOH = –4.0 mA
Output LOW Voltage VCC = Min, IOL = 8.0 mA
Input HIGH Voltage
V
V
V
0.4
2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC
+ 0.3 + 0.3 + 0.3 + 0.3
–0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8
0.4
0.4
0.4
[2]
VIL
Input LOW Voltage
V
IIX
Input Leakage
Current
GND < VI < VCC
Com’l/Ind’l
Auto-A
–1
–1
+1
+1
–1
+1
–1
+1
–1
–1
+1
+1
μA
Auto-E
–20 +20
–1 +1
–20 +20
IOZ
Output Leakage
Current
GND < VOUT < VCC, Com’l/Ind’l
–1
–1
+1
+1
–1
+1
–1
–1
+1
+1
μA
Output disabled
Auto-A
Auto-E
–20 +20
–20 +20
ICC
VCC Operating
Supply Current
VCC = Max,
f = fMAX = 1/tRC
Com’l
90
85
95
80
90
75
85
85
90
40
40
45
mA
Ind’l
100
100
Auto-A
Auto-E
Com’l/Ind’l
Auto-A
Auto-E
120
40
ISB1
Automatic CE Power Max VCC
Down Current —TTL CE > VIH
Inputs
,
40
40
40
10
mA
mA
VIN > VIH or
IN < VIL, f = fMAX
45
10
V
ISB2
Automatic CE Power Max VCC
Down Current —
CMOS Inputs
,
Com’l/Ind’l
Auto-A
10
10
10
10
15
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Auto-E
15
Note
2.
V (min) = –2.0V and V (max) = V + 0.5V for pulse durations of less than 20 ns.
IL IH CC
Document Number: 38-05134 Rev. *I
Page 4 of 14
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CY7C1041CV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max
8
Unit
pF
COUT
8
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
SOJ
TSOP II
FBGA
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
25.99
42.96
38.15
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
18.8
10.75
9.15
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [3]
12-, 15-, 20-ns devices:
10-ns devices:
R 317Ω
Z = 50Ω
3.3V
OUTPUT
OUTPUT
50Ω
30 pF*
R2
351Ω
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(b)
(a)
High-Z characteristics:
R 317Ω
ALL INPUT PULSES
90%
3.3V
OUTPUT
5 pF
3.0V
90%
10%
10%
R2
351Ω
GND
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(d)
Note
3. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown
in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document Number: 38-05134 Rev. *I
Page 5 of 14
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CY7C1041CV33
Switching Characteristics
Over the Operating Range [4]
-10
-12
-15
-20
Parameter
Description
Unit
Min Max Min Max Min Max Min Max
Read Cycle
[5]
tpower
VCC(Typical) to the First Access
Read Cycle Time
100
10
100
12
100
15
100
20
μs
ns
ns
ns
ns
ns
tRC
tAA
Address to Data Valid
10
12
15
20
tOHA
tACE
tDOE
Data Hold from Address Change
CE LOW to Data Valid
3
3
3
3
10
5
12
6
15
7
20
8
OE LOW to Data Valid
Comm’l/Ind’l/Auto-A
Auto-E
7
8
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power Up
CE HIGH to Power Down
0
3
0
0
3
0
0
3
0
0
3
0
ns
ns
ns
ns
ns
ns
ns
5
5
6
6
7
7
8
8
tPD
10
5
12
6
15
7
20
8
tDBE
Byte Enable to Data Valid Comm’l/Ind’l/Auto-A
Auto-E
7
8
tLZBE
Byte Enable to Low Z
0
0
0
0
ns
ns
tHZBE
Byte Disable to High Z
6
6
7
8
Write Cycle[8, 9]
tWC
tSCE
tAW
Write Cycle Time
10
7
12
8
15
10
10
0
20
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
7
8
tHA
0
0
tSA
0
0
0
0
tPWE
tSD
7
8
10
7
10
8
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
5
6
tHD
0
0
0
0
tLZWE
tHZWE
tBW
3
3
3
3
WE LOW to High Z[6, 7]
5
6
7
8
Byte Enable to End of Write
7
8
10
10
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
5. gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
6. At any temperature and voltage condition, t
t
POWER
CC
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
7.
t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads and Waveforms on page 5. Transition is measured ±500
HZOE HZCE HZBE
HZWE
mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document Number: 38-05134 Rev. *I
Page 6 of 14
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CY7C1041CV33
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[10, 11]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE, BLE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
ICC
ISB
PU
VCC
SUPPLY
CURRENT
50%
50%
Notes
10. Device is continuously selected. OE, CE, BHE, and/or BLE = V .
IL
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05134 Rev. *I
Page 7 of 14
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CY7C1041CV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (CE Controlled)[13, 14]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA IO
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
BHE, BLE
t
SA
t
BW
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA IO
Notes
13. Data IO is high impedance if OE, BHE, and/or BLE = V
.
IH
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05134 Rev. *I
Page 8 of 14
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CY7C1041CV33
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA IO
t
LZWE
Truth Table
CE
H
OE
X
WE
X
BLE
X
BHE
X
IO0 – IO7 IO8 – IO15
High Z High Z
Data Out Data Out Read – All Bits
Data Out High Z Read – Lower Bits Only
Data Out Read – Upper Bits Only
Mode
Power
Power Down
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
L
L
H
L
L
)
L
H
L
)
H
L
High Z
Data In
Data In
High Z
High Z
High Z
)
L
X
L
L
Data In
High Z
Data In
High Z
High Z
Write – All Bits
)
L
H
L
Write – Lower Bits Only
Write – Upper Bits Only
)
H
X
)
L
L
H
X
H
X
X
Selected, Outputs Disabled
Selected, Outputs Disabled
)
H
H
)
Document Number: 38-05134 Rev. *I
Page 9 of 14
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CY7C1041CV33
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
10
CY7C1041CV33-10BAXC
CY7C1041CV33-10VC
CY7C1041CV33-10VXC
CY7C1041CV33-10ZXC
CY7C1041CV33-10BAI
CY7C1041CV33-10BAXI
CY7C1041CV33-10ZI
CY7C1041CV33-10ZXI
CY7C1041CV33-10BAXA
CY7C1041CV33-10ZSXA
CY7C1041CV33-12VXC
CY7C1041CV33-12ZXC
CY7C1041CV33-12ZI
CY7C1041CV33-12ZXI
CY7C1041CV33-12BAXE
CY7C1041CV33-12ZSXE
CY7C1041CV33-15ZXC
CY7C1041CV33-15VI
CY7C1041CV33-15VXI
CY7C1041CV33-15ZI
CY7C1041CV33-15ZXI
CY7C1041CV33-20ZC
CY7C1041CV33-20ZSXA
CY7C1041CV33-20VE
CY7C1041CV33-20VXE
CY7C1041CV33-20ZE
CY7C1041CV33-20ZSXE
51-85106 48-ball Fine Pitch BGA (Pb-Free)
51-85082 44-pin (400-mil) Molded SOJ
44-pin (400-mil) Molded SOJ (Pb-Free)
51-85087 44-pin TSOP II (Pb-Free)
51-85106 48-ball Fine Pitch BGA
48-ball Fine Pitch BGA (Pb-Free)
51-85087 44-pin TSOP II
Commercial
Industrial
44-pin TSOP II (Pb-Free)
51-85106 48-ball Fine Pitch BGA (Pb-Free)
51-85087 44-pin TSOP II (Pb-Free)
51-85082 44-pin (400-mil) Molded SOJ (Pb-Free)
51-85087 44-pin TSOP II (Pb-Free)
51-85087 44-pin TSOP II
Automotive-A
Commercial
Industrial
12
44-pin TSOP II (Pb-Free)
51-85106 48-ball Fine Pitch BGA (Pb-Free)
51-85087 44-pin TSOP II (Pb-Free)
51-85087 44-pin TSOP II (Pb-Free)
51-85082 44-pin (400-mil) Molded SOJ
44-pin (400-mil) Molded SOJ (Pb-Free)
51-85087 44-pin TSOP II
Automotive-E
15
20
Commercial
Industrial
44-pin TSOP II (Pb-Free)
51-85087 44-pin TSOP II
Commercial
Automotive-A
Automotive-E
51-85087 44-pin TSOP II (Pb-Free)
51-85082 44-pin (400-mil) Molded SOJ
44-pin (400-mil) Molded SOJ (Pb-Free)
51-85087 44-pin TSOP II
44-pin TSOP II (Pb-Free)
Please contact your local Cypress sales representative for availability of these parts
Document Number: 38-05134 Rev. *I
Page 10 of 14
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CY7C1041CV33
Package Diagrams
Figure 9. 44-Pin (400 Mil) Molded SOJ, 51-85082
51-85082-*B
Document Number: 38-05134 Rev. *I
Page 11 of 14
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CY7C1041CV33
Package Diagrams (continued)
Figure 10. 44-Pin Thin Small Outline Package Type II, 51-85087
51-85087-*A
Document Number: 38-05134 Rev. *I
Page 12 of 14
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CY7C1041CV33
Package Diagrams (continued)
Figure 11. 48-Ball FBGA (7 x 8.5 x 1.2 mm), 51-85106
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05ꢀ(48X
A1 CORNER
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
7.00 0.10
3.75
B
7.00 0.10
0.15ꢀ(8X
SEATING PLANE
C
51-85106-*E
Document Number: 38-05134 Rev. *I
Page 13 of 14
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CY7C1041CV33
Document History Page
Document Title: CY7C1041CV33, 4-Mbit (256K x 16) Static RAM
Document Number: 38-05134
Issue
Date
Orig. of
Change
REV. ECN NO.
Description of Change
**
109513 12/13/01
112440 12/20/01
112859 03/25/02
HGK
BSS
DFP
New Data Sheet
*A
*B
Updated 51-85106 from revision *A to *C
Added CY7C1042CV33 in BGA package
Removed 1042 BGA option pin ACC Final Data Sheet
*C
*D
*E
116477 09/16/02
119797 10/21/02
262949 See ECN
CEA
DFP
RKF
Add applications foot note to data sheet
Added 20-ns speed bin
1) Added Lead (Pb)-Free parts in the Ordering info (Page #9)
2) Added Automotive Specs to Datasheet
*F
361795 See ECN
435387 See ECN
SYT
NXR
Added Pb-Free offerings in the Ordering Information
*G
Removed -8 Speed bin from Product offering.
Corrected typo in description for BHE/BLE in pin definitions table on Page# 3
corrected their Pin name from OE2 to OE.
Included the Maximum Ratings for Static Discharge Voltage and Latch up Current.
Changed the description of IIX current from Input Load Current to
Input Leakage Current
Added note# 4 on page# 4
Updated the Ordering Information table
*H
*I
499153 See ECN
NXR
Added Automotive-A Operating Range
Changed tpower value from 1 μs to 100 μs
Updated Ordering Information table
2104110 See ECN VKN/AESA Added Automotive-E specs for 12 ns speed
Updated Ordering Information table
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Document Number: 38-05134 Rev. *I
Revised February 14, 2008
Page 14 of 14
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