CY7C1049L-17VC [CYPRESS]
512K x 8 Static RAM; 512K ×8静态RAM
| 型号： | CY7C1049L-17VC |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 8 Static RAM |
| 文件： | 总10页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
049
PRELIMINARY
CY7C1049
512K x 8 Static RAM
is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. Writing to the de-
vice is accomplished by taking chip enable (CE) and write en-
able (WE) inputs LOW. Data on the eight I/O pins (I/O0 through
I/O7) is then written into the location specified on the address
pins (A0 through A18).
Features
• High speed
— tAA = 15 ns
• Low active power
— 1210 mW (max.)
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write en-
able (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
• Low CMOS standby power (Commercial L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description
The CY7C1049 is available in a standard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.
The CY7C1049 is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configuration
SOJ
Top View
A0
A1
36
35
34
33
32
1
2
3
4
5
6
7
8
9
NC
A18
A17
A16
A15
A2
A3
A4
CE
I/O0
I/O1
VCC
31
30
29
28
OE
I/O7
I/O6
I/O
0
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
INPUT BUFFER
27
26
25
GND 10
A
1
0
I/O
I/O
I/O2
I/O3
WE
11
12
13
1
A
A
2
24
23
22
21
20
19
2
A
A5
A6
A7
A8
A9
3
4
14
15
16
17
18
A
A
6
5
I/O
I/O
I/O
3
4
5
512K x 8
ARRAY
A
A
7
A
8
A
9
1049–2
A
10
I/O
6
7
POWER
DOWN
COLUMN
DECODER
CE
I/O
WE
1049–1
OE
Selection Guide
7C1049-12
7C1049-15
7C1049-17
7C1049-20
7C1049-25
Maximum Access Time (ns)
12
240
8
15
220
8
17
195
8
20
185
8
25
180
8
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Com’l
Com’l
Ind’l
L
0.5
9
0.5
9
0.5
9
0.5
9
0.5
9
Military
10
10
Shaded areas contain advance information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05063 Rev. **
Revised August 31, 2001
PRELIMINARY
CY7C1049
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
Ambient
Range
Commercial
Industrial
Military
Temperature[2]
0°C to +70°C
VCC
4.5V–5.5V
DC Voltage Applied to Outputs
–40°C to +85°C
–55°C to +125°C
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
7C1049-12
7C1049-15
7C1049-17
Min.
Max.
Min.
Max.
Min.
Max. Unit
VOH
VOL
VIH
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
Input HIGH Voltage
2.4
2.4
2.4
V
0.4
0.4
0.4
V
V
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
VIL
IIX
Input LOW Voltage[1]
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
–0.3
–1
0.3
+1
+1
V
Input Load Current
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
240
40
220
40
195
40
mA
mA
ISB1
Automatic CE
Max. VCC, CE > VIH
Power-Down Current VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current CE > VCC – 0.3V,
—CMOS Inputs
Max. VCC
,
Com’l
Com’l
Ind’l
8
0.5
9
8
0.5
9
8
0.5
9
mA
mA
mA
mA
L
VIN > VCC – 0.3V,
or VIN < 0.3V, f=0
Military
10
10
10
Shaded areas contain advance information.
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. A is the “instant on” case temperature.
T
Document #: 38-05063 Rev. **
Page 2 of 10
PRELIMINARY
CY7C1049
Electrical Characteristics Over the Operating Range (continued)
Test Conditions
7C1049-20
7C1049-25
Parameter
VOH
Description
Min.
Max.
Min.
Max.
Unit
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
2.2
2.4
2.2
VOL
VIH
VCC = Min., IOL = 8.0 mA
0.4
0.4
V
VCC
+ 0.3
VCC
0.3
+
V
VIL
IIX
Input LOW Voltage[1]
Input Load Current
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
V
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
185
40
180
40
mA
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
,
Com’l
Com’l
Ind’l
8
0.5
9
8
0.5
9
mA
mA
mA
mA
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f=0
L
Military
10
10
Capacitance[3]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
pF
CIN
Input Capacitance
I/O Capacitance
8
8
COUT
pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
Ω
R1 481
R1 481Ω
5V
5V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
10%
R2
255Ω
R2
255Ω
30 pF
5 pF
≤ 3ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
1049–3
(a)
1049–4
THÉ
Equivalent to:
VENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Document #: 38-05063 Rev. **
Page 3 of 10
PRELIMINARY
CY7C1049
Switching Characteristics[4] Over the Operating Range
7C1049-12
Min. Max.
7C1049-15
Min. Max.
7C1049-17
Min. Max.
Parameter
Description
Unit
READ CYCLE
tRC
Read Cycle Time
Address to Data Valid
12
3
15
3
17
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
12
15
17
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
CE HIGH to High Z[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
12
6
15
7
17
8
0
3
0
0
3
0
0
3
0
6
6
7
7
7
7
tPD
12
15
17
WRITE CYCLE[7,8]
tWC
tSCE
tAW
Write Cycle Time
12
10
10
0
15
12
12
0
17
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
tPWE
tSD
10
7
12
8
12
8
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
tHD
0
0
0
tLZWE
tHZWE
3
3
3
WE LOW to High Z[5, 6]
6
7
8
Shaded areas contain advance information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05063 Rev. **
Page 4 of 10
PRELIMINARY
CY7C1049
Switching Characteristics[4] Over the Operating Range (continued)
7C1049-20
7C1049-25
Parameter
READ CYCLE
tRC
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
20
3
25
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
20
25
tOHA
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
CE HIGH to High Z[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
tACE
20
8
25
10
tDOE
tLZOE
tHZOE
tLZCE
0
3
0
0
5
0
8
8
10
10
25
tHZCE
tPU
tPD
20
WRITE CYCLE[7]
tWC
tSCE
tAW
Write Cycle Time
20
13
13
0
25
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
13
9
15
10
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
tHD
0
tLZWE
tHZWE
3
5
WE LOW to High Z[5, 6]
8
10
Data Retention Characteristics Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Conditions[10]
Min.
Max Unit
2.0
V
ICCDR
Data Retention Current
Com’l
Ind’l
L
VCC = VDR = 3.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
200
1
µA
mA
mA
ns
Military
2
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[9]
tR
tRC
ns
Notes:
9. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
10. No input may exceed VCC + 0.5V.
Document #: 38-05063 Rev. **
Page 5 of 10
PRELIMINARY
CY7C1049
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
1049–5
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1049–6
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
1049–7
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05063 Rev. **
Page 6 of 10
PRELIMINARY
CY7C1049
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
1049–8
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 16
t
HZOE
1049–9
Notes:
14. Data I/O is high impedance if OE = VIH
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05063 Rev. **
Page 7 of 10
PRELIMINARY
CY7C1049
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATA I/O
DATA VALID
t
t
LZWE
HZWE
1049–10
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C1049-15VC
Package Type
15
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
Commercial
CY7C1049L-15VC
CY7C1049-17VC
CY7C1049L-17VC
CY7C1049-20VC
CY7C1049L-20VC
CY7C1049-20VI
CY7C1049L-20VI
CY7C1049-20VM
CY7C1049L-20VM
CY7C1049-25VC
CY7C1049L-25VC
CY7C1049-25VI
CY7C1049L-25VI
CY7C1049-25VM
CY7C1049L-25VM
17
20
Industrial
Military
25
Commercial
Industrial
Military
Shaded areas contain advance information.
Document #: 38-05063 Rev. **
Page 8 of 10
PRELIMINARY
CY7C1049
Package Diagram
36-Lead (400-Mil) Molded SOJ V36
Document #: 38-05063 Rev. **
Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C1049
Document Title: CY7C1049 512K x 8 Static RAM
Document Number: 38-05063
Issue
Orig. of
Change
REV.
ECN NO.
Date
Description of Change
Change from Spec number: 38-00563 to 38-05063
**
107256
09/10/01
SZV
Document #: 38-05063 Rev. **
Page 10 of 10
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