CY7C10612GN30-10ZSXI [CYPRESS]
16-Mbit (1M words à 16 bit) Static RAM;
| 型号： | CY7C10612GN30-10ZSXI |
| 厂家： | 
CYPRESS |
| 描述： | 16-Mbit (1M words à 16 bit) Static RAM |
| 文件： | 总21页 (文件大小：1933K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1061GN/CY7C10612GN
16-Mbit (1M words × 16 bit) Static RAM
16-Mbit (1M words
× 16 bit) Static RAM
Features
Functional Description
■ High speed
❐ tAA = 10 ns/15 ns
The CY7C1061GN/CY7C10612GN is a high performance
CMOS Static RAM organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
■ Low active power
❐ ICC = 90 mA at 100 MHz
■ Low CMOS standby current
❐ ISB2 = 20 mA (typ)
A
19). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A19).
■ Operating voltages of 2.2 V to 3.6 V
■ 1.0 V data retention
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 13
for a complete description of Read and Write modes.
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2 features
■ Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball
VFBGA packages
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH/CE2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH, and WE LOW).
■ Offered in dual Chip Enable options
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
4
3
I/O0 – I/O7
I/O8 – I/O15
1M x 16
ARRAY
A
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
BHE
WE
CE2
CE1
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-93680 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 29, 2016
CY7C1061GN/CY7C10612GN
Contents
Selection Guide ................................................................3
Pin Configurations ...........................................................3
Maximum Ratings .............................................................6
Operating Range ...............................................................6
DC Electrical Characteristics ..........................................6
Capacitance ......................................................................7
Thermal Resistance ..........................................................7
AC Test Loads and Waveforms .......................................7
Data Retention Characteristics .......................................8
Over the Operating Range ...............................................8
Data Retention Waveform ................................................8
AC Switching Characteristics .........................................9
Switching Waveforms ....................................................10
Truth Table ......................................................................13
Ordering Information ......................................................14
Ordering Code Definitions .........................................14
Package Diagrams ..........................................................15
Acronyms ........................................................................18
Document Conventions .................................................18
Units of Measure .......................................................18
Document History Page .................................................19
Sales, Solutions, and Legal Information ......................21
Worldwide Sales and Design Support .......................21
Products ....................................................................21
PSoC®Solutions .......................................................21
Cypress Developer Community .................................21
Technical Support .....................................................21
Document Number: 001-93680 Rev. *C
Page 2 of 21
CY7C1061GN/CY7C10612GN
Selection Guide
Description
-10
10
-15
15
80
30
Unit
ns
Maximum access time
Maximum operating current
Maximum CMOS standby current
110
30
mA
mA
Pin Configurations
Figure 1. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable pinout, Package/Grade ID: BVXI [1]
1
2
3
4
6
5
A0
A1
A2
CE2
A
B
C
OE
BLE
A4
A6
A3
A5
CE1
I/O8 BHE
I/O9 I/O10
I/O0
I/O1 I/O2
VCC
I/O11
VSS
A7 I/O3
D
E
F
A17
VCC
A16
A15
A13
A10
I/O4 VSS
I/O5 I/O6
I/O12 NC
A14
I/O14 I/O13
A12
A9
I/O15 NC
I/O7
A19
WE
A11
G
H
A8
A18
Note
1. NC pins are not connected internally to the die.
Document Number: 001-93680 Rev. *C
Page 3 of 21
CY7C1061GN/CY7C10612GN
Pin Configurations (continued)
Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm)
Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm)
Dual Chip Enable pinout, Package/Grade ID: BVJXI [2]
Single Chip Enable pinout, Package/Grade ID: BV1XI [2]
1
2
3
4
5
6
1
2
3
4
5
6
A0
A2
A1
NC
A
B
C
A0
A1
A2
CE2
OE
A
B
C
BLE
OE
BLE
A3
A5
A4
A6
A3
A5
A4
A6
CE1
I/O8 BHE
I/O9 I/O10
CE
I/O8 BHE
I/O9 I/O10
I/O0
I/O0
I/O1 I/O2
I/O1 I/O2
VCC
I/O11
VSS
VCC
A7 I/O3
D
E
F
A17
I/O11
VSS
A7 I/O3
D
E
F
A17
VCC
A16 I/O4 VSS
I/O12 ERR
A14
I/O4 VSS
I/O5 I/O6
VCC
A16
A15
A13
A10
I/O12 NC
A14
A15
I/O5 I/O6
I/O14 I/O13
I/O15 A19
I/O14 I/O13
A12 A13
I/O7
NC
WE
G
H
A12
A9
I/O15 A19
I/O7
NC
WE
A11
G
H
A9 A10 A11
A8
A18
A8
A18
Figure 4. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm)
Dual Chip Enable pinout (Top View) [2]
Figure 5. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm)
Single Chip Enable pinout (Top View) [2]
I/O
V
I/O
V
I/O
V
I/O
V
12
1
2
3
4
5
6
54
53
52
51
50
49
48
47
46
12
1
2
3
4
5
6
54
53
52
51
50
49
48
47
46
11
11
CC
CC
SS
SS
I/O
I/O
V
I/O
I/O
V
I/O
I/O
V
I/O
I/O
V
13
14
13
14
10
9
10
9
SS
SS
CC
CC
I/O
I/O
I/O
A
5
I/O
A
5
15
15
8
8
A
A
7
8
9
7
8
9
4
3
2
1
0
4
3
2
1
0
A
A
A
A
BHE
CE
A
6
A
7
A
8
A
9
A
A
A
A
A
6
A
7
A
8
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
45
44
45
44
NC
NC
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
BHE
CE
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
OE
V
OE
V
1
CC
V
V
CC
SS
SS
WE
NC
A
A
A
A
A
I/O
0
NC
BLE
WE
CE
A
A
A
A
A
I/O
0
NC
BLE
2
A
A
19
10
19
10
A
A
18
11
18
11
A
A
17
12
17
12
A
A
16
13
16
13
A
I/O
7
A
I/O
7
15
14
15
14
V
I/O
1
V
I/O
6
V
I/O
1
V
I/O
6
CC
SS
CC
SS
I/O
5
I/O
2
I/O
5
I/O
2
V
I/O
3
V
I/O
4
V
I/O
3
V
I/O
4
SS
CC
SS
CC
Note
2. NC pins are not connected internally to the die.
Document Number: 001-93680 Rev. *C
Page 4 of 21
CY7C1061GN/CY7C10612GN
Pin Configurations (continued)
Figure 6. 48-pin TSOP I (12 × 18.4 × 1 mm) pinout (Top View) [3]
A
A
A
A
A
NC
CE
I/O
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
A
A
A
OE
BHE
BLE
I/O
I/O
14
I/O
I/O
12
4
3
2
1
0
5
6
7
8
0
15
I/O
1
I/O
I/O
3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
13
V
GND
DD
GND
I/O
I/O
5
I/O
I/O
7
WE
NC
V
DD
I/O
I/O
I/O
I/O
4
11
10
9
6
8
NC
A
A
A
A
A
A
9
A
19
10
11
12
13
14
A
18
A
17
A
16
A
15
Note
3. NC pins are not connected internally to the die.
Document Number: 001-93680 Rev. *C
Page 5 of 21
CY7C1061GN/CY7C10612GN
DC Input Voltage [4] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(MIL-STD-883, Method 3015) ..................................>2001V
Storage Temperature ............................... –65 C to +150 C
Latch Up Current ....................................................>200 mA
Ambient Temperature
with Power Applied .................................. –55 C to +125 C
Operating Range
Supply Voltage
on VCC relative to GND [4] ..................–0.5 V to VCC + 0.5 V
Range
Ambient Temperature
VCC
Industrial
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V
DC Voltage Applied to Outputs
in High Z State [4] ................................–0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the Operating Range
10 ns/15 ns
Parameter
Description
Test Conditions
Unit
Max
Min
1.4
2.0
2.2
2.4
–
Typ [5]
VOH
Output HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA
3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
2.2 V to 2.7 V VCC = Min, IOL = 2 mA
2.7 V to 3.6 V VCC = Min, IOL = 8 mA
1.65 V to 2.2 V –
–
–
–
V
–
–
–
–
–
VOL
VIH
VIL
Output LOW
voltage
–
0.2
V
V
V
–
–
0.4
–
–
0.4
Input HIGH
voltage [4]
1.4
2.0
2.0
–0.2
–0.3
–0.3
–1
–
VCC + 0.2
VCC + 0.3
VCC + 0.3
0.4
2.2 V to 2.7 V –
–
2.7 V to 3.6 V –
–
Input LOW
voltage [4]
1.65 V to 2.2 V –
–
2.2 V to 2.7 V –
–
0.6
2.7 V to 3.6 V –
–
0.8
IIX
Input leakage current
GND < VI < VCC
–
+1
A
A
IOZ
ICC
Output leakage current
VCC operating supply current
GND < VOUT < VCC, Output disabled
–1
–
+1
VCC = Max,
IOUT = 0 mA,
f = 100 MHz
f = 66.7 MHz
–
90
70
110
mA
–
80
CMOS levels
ISB1
Automatic CE power down
current – TTL inputs[6]
Max VCC
,
–
–
–
40
30
mA
mA
CE1 > VIH, CE2 < VIL,
VIN > VIH or VIN < VIL, f = fMAX
ISB2
Automatic CE power down
current – CMOS inputs[6]
Max VCC
,
20
CE1 > VCC – 0.3 V, CE2 < 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0
Notes
4.
V
= –2.0 V and V
= V + 2 V for pulse durations of less than 20 ns.
IH(max) CC
IL(min)
5. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),
CC
CC
V
= 3 V (for a V range of 2.2 V–3.6 V) at T = 25 °C.
CC A
CC
6. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
Document Number: 001-93680 Rev. *C
Page 6 of 21
CY7C1061GN/CY7C10612GN
Capacitance
Parameter [7]
Description
Input capacitance
I/O capacitance
Test Conditions
48-pin TSOP I 54-pin TSOP II 48-ball VFBGA Unit
CIN
TA = 25 C, f = 1 MHz,
VCC = 3.3 V
10
10
10
10
10
10
pF
pF
COUT
Thermal Resistance
Parameter [7]
Description
Test Conditions
48-pin TSOP I 54-pin TSOP II 48-ball VFBGA Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a
3 × 4.5 inch, four layer
printed circuit board
57.99
93.63
31.50
C/W
JC
Thermal resistance
(junction to case)
13.42
21.58
15.75
C/W
AC Test Loads and Waveforms
Figure 7. AC Test Loads and Waveforms [8]
High-Z Characteristics:
R1
50
VCC
Output
VTH
Output
Z = 50
R2
30 pF*
0
5 pF*
Including
JIG and
Scope
(a)
(b)
* Capacitive Load Consists
of all Components of the
Test Environment
All Input Pulses
V
HIGH
90%
10%
90%
10%
GND
Fall Time:
> 1 V/ns
Rise Time:
> 1 V/ns
(c)
Parameters
R1
1.8 V
1667
1538
0.9
3.0 V
Unit
317
351
1.5
3
V
V
R2
VTH
VHIGH
1.8
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full-device AC operation assumes a 100-µs ramp time from 0 to V (min) and 100-µs wait time after V stabilizes to its operational value.
CC
CC
Document Number: 001-93680 Rev. *C
Page 7 of 21
CY7C1061GN/CY7C10612GN
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
VCC for data retention
Data retention current
Conditions
Min
1
Max
–
Unit
V
–
VCC = 1.2 V,
–
30
mA
CE1 > VCC – 0.2 V, CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
[9]
tCDR
Chip deselect to data retention
time
–
0
–
ns
ns
[10]
tR
Operation recovery time
VCC > 2.2 V
VCC < 2.2 V
10
15
–
–
Data Retention Waveform
Figure 8. Data Retention Waveform [11]
Data Retention Mode
VCC (min)
VCC (min)
VCC
CE
VDR > 1 V
t
t
R
CDR
Notes
9. Tested initially and after any design or process changes that may affect these parameters.
10. Full device operation requires linear V ramp from V to V > 100 s or stable at V > 100 s.
CC(min.)
CC
DR
CC(min.)
11. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
Document Number: 001-93680 Rev. *C
Page 8 of 21
CY7C1061GN/CY7C10612GN
AC Switching Characteristics
Over the Operating Range
-10
-15
Parameter [12]
Description
Unit
Min
Max
Min
Max
Read Cycle
tpower
tRC
VCC(typical) to the first access [13]
Read cycle time
100
10
–
–
–
100
15
–
–
–
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
10
–
15
–
tOHA
Data hold from address change
CE1 LOW/CE2 HIGH to data valid
OE LOW to data valid
3
3
tACE
–
10
5
–
15
8
tDOE
–
–
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to low Z [14]
0
–
1
–
OE HIGH to high Z [14, 15]
CE1 LOW/CE2 HIGH to low Z [14]
CE1 HIGH/CE2 LOW to high Z [14, 15]
CE1 LOW/CE2 HIGH to power-up [16]
CE1 HIGH/CE2 LOW to power-down [16]
Byte enable to data valid
–
5
–
8
3
–
3
–
–
5
–
8
0
–
0
–
tPD
–
10
5
–
15
8
tDBE
–
–
tLZBE
Byte enable to low Z
0
–
1
–
tHZBE
Byte disable to high Z
–
6
–
8
Write Cycle [17, 18]
tWC
tSCE
tAW
Write cycle time
10
7
7
0
0
7
5
0
3
–
7
–
–
–
–
–
–
–
–
–
5
–
15
12
12
0
–
–
–
–
–
–
–
–
–
8
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW/CE2 HIGH to write end[19]
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
tHA
tSA
0
tPWE
tSD
12
8
Data setup to write end
tHD
Data hold from write end
WE HIGH to low Z [14]
WE LOW to high Z [14, 15]
0
tLZWE
tHZWE
tBW
3
–
Byte Enable to End of Write
12
Notes
12. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for V > 3 V) and V /2 (for V < 3 V), and input pulse levels
CC
CC
CC
of 0 to 3 V (for V > 3 V) and 0 to V (for V < 3V). Test conditions for the read cycle use the output loading, shown in part (a) of Figure 7 on page 7, unless specified otherwise.
CC
CC
CC
13. t
gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
POWER
CC
14. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
15. t
, t
, t
, and t
are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 7 on page 7. Hi-Z, Lo-Z transition is measured 200 mV from steady state
HZOE HZCE HZWE
HZBE
voltage.
16. These parameters are guaranteed by design and are not tested.
17. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . Chip enables must be active and WE and byte enables must be
1
IL
2
IH
LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal
that terminates the write.
18. The minimum write cycle time for Write Cycle No. 2 (WE Controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
19. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
Document Number: 001-93680 Rev. *C
Page 9 of 21
CY7C1061GN/CY7C10612GN
Switching Waveforms
Figure 9. Read Cycle No. 1 (Address Transition Controlled) [20, 21]
tRC
Address
t
AA
t
OHA
Data Out
Previous Data Valid
Data Valid
Figure 10. Read Cycle No. 2 (OE Controlled) [21, 22, 23]
Address
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
High
Impedance
High Impedance
Data Out
VCC
Supply
Current
Data Valid
t
LZCE
t
PD
I
CC
t
PU
50%
50%
I
SB
Notes
20. The device is continuously selected. OE, CE = V , BHE, BLE or both = V
.
IL
IL
21. WE is HIGH for read cycle.
22. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
23. Address valid before or similar to CE transition LOW.
Document Number: 001-93680 Rev. *C
Page 10 of 21
CY7C1061GN/CY7C10612GN
Switching Waveforms (continued)
Figure 11. Write Cycle No. 1 (CE Controlled) [24, 25, 26]
t
WC
Address
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
Data I/O
Figure 12. Write Cycle No. 2 (WE Controlled, OE LOW) [24, 25, 26]
t
WC
Address
t
SCE
CE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
Data I/O
t
LZWE
Notes
24. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
25. Data I/O is high impedance if OE, BHE, and/or BLE = V
.
IH
26. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document Number: 001-93680 Rev. *C
Page 11 of 21
CY7C1061GN/CY7C10612GN
Switching Waveforms (continued)
Figure 13. Write Cycle No. 3 (BLE or BHE Controlled) [27]
t
WC
Address
t
t
BW
SA
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
Data I/O
Note
27. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
Document Number: 001-93680 Rev. *C
Page 12 of 21
CY7C1061GN/CY7C10612GN
Truth Table
CE1 CE2 OE WE BLE BHE I/O0–I/O7 I/O8–I/O15
Mode
Power
H
X
L
L
L
L
L
L
L
X
L
X
X
L
X
X
H
H
H
L
X
X
L
X
X
L
High Z
High Z
Data out
Data out
High Z
Data in
Data in
High Z
High Z
High Z
High Z
Data out
High Z
Data out
Data in
High Z
Data in
High Z
Power down
Standby (ISB
)
)
Power down
Standby (ISB
H
H
H
H
H
H
H
Read all bits
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
H
L
Read lower bits only
Read upper bits only
Write all bits
L
H
L
X
X
X
H
L
L
L
H
L
Write lower bits only
Write upper bits only
Selected, outputs disabled
L
H
X
H
X
Document Number: 001-93680 Rev. *C
Page 13 of 21
CY7C1061GN/CY7C10612GN
Ordering Information
Speed
Package
Diagram
Package Type
(Pb-free)
Operating
Range
Ordering Code
(ns)
10
CY7C1061GN30-10ZSXI
CY7C1061GN30-10ZSXIT
CY7C10612GN30-10ZSXI
51-85160 54-pin TSOP II, Dual Chip Enable
Industrial
51-85160 54-pin TSOP II, Dual Chip Enable, Tape and Reel
51-85160 54-pin TSOP II, Single Chip Enable
CY7C10612GN30-10ZSXIT 51-85160 54-pin TSOP II, Single Chip Enable, Tape and Reel
CY7C1061GN30-10ZXI
CY7C1061GN30-10ZXIT
CY7C1061GN30-10BV1XI
51-85183 48-pin TSOP I, Single Chip Enable
51-85183 48-pin TSOP I, Single Chip Enable, Tape and Reel
51-85150 48-ball VFBGA, Single Chip Enable, Address MSB A19 at ball G2
CY7C1061GN30-10BV1XIT 51-85150 48-ball VFBGA, Single Chip Enable, Address MSB A19 at ball G2,
Tape and Reel
CY7C1061GN30-10BVJXI
51-85150 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball G2
CY7C1061GN30-10BVJXIT 51-85150 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball G2,
Tape and Reel
CY7C1061GN30-10BVXI
CY7C1061GN30-10BVXIT
51-85150 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball H6
51-85150 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball H6,
Tape and Reel
15
CY7C1061GN18-15ZSXI
CY7C1061GN18-15ZSXIT
51-85160 54-pin TSOP II
51-85160 54-pin TSOP II, Tape and Reel
Ordering Code Definitions
CY 7 1 06 1 X G N XX - X XX X
C
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = ZS or ZX or BV1 or BVJ or BV
ZS = 54-pin TSOP II;
ZX = 48-pin TSOP I;
BV1 = 48-ball VFBGA, Single Chip Enable, Address MSB A19 at ball G2;
BVJ = 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball G2;
BV = 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball H6
Speed: X = 10 or 15
10 = 10 ns; 15 = 15 ns
Voltage Range: XX = 30 or 18
30 = 2.2 V to 3.6 V; 18 = 1.65 V to 2.2 V
N = No ECC
Process Technology: G = 65 nm Technology
Chip Enable: X = blank or 2
Data Width: 1 = × 16-bits
Density: 06 = 16-Mbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-93680 Rev. *C
Page 14 of 21
CY7C1061GN/CY7C10612GN
Package Diagrams
Figure 14. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
51-85160 *E
Document Number: 001-93680 Rev. *C
Page 15 of 21
CY7C1061GN/CY7C10612GN
Package Diagrams (continued)
Figure 15. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A Package Outline, 51-85183
51-85183 *D
Document Number: 001-93680 Rev. *C
Page 16 of 21
CY7C1061GN/CY7C10612GN
Package Diagrams (continued)
Figure 16. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-93680 Rev. *C
Page 17 of 21
CY7C1061GN/CY7C10612GN
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
BHE
BLE
Byte High Enable
Unit of Measure
Byte Low Enable
Chip Enable
°C
MHz
A
s
mA
mm
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
CE
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
OE
Output Enable
SRAM
TSOP
TTL
Static Random Access Memory
Thin Small Outline Package
Transistor-Transistor Logic
Very Fine-Pitch Ball Grid Array
Write Enable
%
percent
VFBGA
WE
pF
V
picofarad
volt
W
watt
Document Number: 001-93680 Rev. *C
Page 18 of 21
CY7C1061GN/CY7C10612GN
Document History Page
Document Title: CY7C1061GN/CY7C10612GN, 16-Mbit (1M words × 16 bit) Static RAM
Document Number: 001-93680
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
4505531
4900408
VINI
01/02/2015 New data sheet.
*A
NILE
09/11/2015 Updated DC Electrical Characteristics:
Updated details in “Test Conditions” column of VOH and VOL parameters.
Updated Ordering Information:
No change in part numbers.
Replaced “51-85178” with “51-85150” in “Package Diagram” column.
Replaced “8 × 9.5 × 1 mm” with “6 × 8 × 1.0 mm” in “Package Type” column.
Updated Package Diagrams:
Removed spec 51-85178 *C.
Added spec 51-85150 *H.
Updated to new template.
*B
5415385
NILE
09/07/2016 Updated Document Title to read as “CY7C1061GN/CY7C10612GN, 16-Mbit
(1M words × 16 bit) Static RAM”.
Added CY7C10612GN part related information in all instances across the
document.
Added “1.65 V to 2.2 V” voltage range related information in all instances
across the document.
Added 48-pin TSOP I package related information in all instances across the
document.
Added 15 ns speed bin related information in all instances across the
document.
Updated Pin Configurations:
Added Figure 2.
Added Figure 3.
Added Figure 4.
Added Figure 5.
Added Figure 6.
Removed figure “54-pin TSOP II (22.4 × 11.84 × 1.0 mm) pinout (Top View)”.
Updated DC Electrical Characteristics:
Updated details in “Test Conditions” column of ICC parameter (Added condition
“f = 66.7 MHz” and added corresponding values).
Added Note 6 and referred the same note in description of ISB1 and ISB2
parameters.
Updated AC Test Loads and Waveforms:
Updated Note 8 referred in Figure 7.
Updated AC Switching Characteristics:
Updated Note 12.
Added Note 14 and referred the same note in description of tLZOE, tHZOE, tLZCE
,
t
HZCE parameters.
Updated Note 15.
Added Note 19 and referred the same note in description of tSCE parameter.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
Added spec 51-85183 *D.
Updated to new template.
Document Number: 001-93680 Rev. *C
Page 19 of 21
CY7C1061GN/CY7C10612GN
Document History Page (continued)
Document Title: CY7C1061GN/CY7C10612GN, 16-Mbit (1M words × 16 bit) Static RAM
Document Number: 001-93680
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*C
5454555
NILE
09/29/2016 Updated Maximum Ratings:
Updated Note 4 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Removed Operating Range “2.7 V to 3.6 V” and all values corresponding to
VOH parameter.
Included Operating Ranges “2.7 V to 3.0 V” and “3.0 V to 3.6 V” and all values
corresponding to VOH parameter.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Document Number: 001-93680 Rev. *C
Page 20 of 21
CY7C1061GN/CY7C10612GN
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
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Forums | Projects | Video | Blogs | Training | Components
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Touch Sensing
USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015–2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-93680 Rev. *C
Revised September 29, 2016
Page 21 of 21
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