CY7C1061DV33-10BVJXIT [CYPRESS]
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48;
| 型号： | CY7C1061DV33-10BVJXIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 存储 内存集成电路 静态存储器 |
| 文件： | 总10页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1061DV33
PRELIMINARY
16-Mbit (1M x 16) Static RAM
Features
Functional Description
• High speed
The CY7C1061DV33 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
— tAA = 10 ns
Writing to the device is accomplished by enabling the chip
(CE1 LOW and CE2 HIGH) while forcing the Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
• Low active power
— ICC = 125 mA @ 10 ns
• Low CMOS standby power
— ISB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
Reading from the device is accomplished by enabling the chip
by taking CE1 LOW and CE2 HIGH while forcing the Output
Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table at the back of this data
sheet for a complete description of Read and Write modes.
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 54-pin TSOP II package and 48-ball
VFBGA packages
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE1
HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the
BHE and BLE are disabled (BHE, BLE HIGH), or during a
Write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C1061DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball Very fine-pitch ball grid array (VFBGA) package
Logic Block Diagram
Pin Configuration
54-pin TSOP II (Top View)
I/O
V
I/O
I/O
1
54
53
I/O
V
11
12
CC
INPUT BUFFER
2
3
4
5
6
SS
I/O
52
51
50
13
14
10
A
0
I/O
V
9
A
1
V
SS
CC
A
2
I/O
49 I/O
15
8
A
4
3
A
A
3
48
47
A
5
I/O0–I/O7
7
1M x 16
ARRAY
4
A
A
8
6
A
5
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A
A
7
9
I/O8–I/O15
2
A
6
A
10
11
12
A
1
8
A
7
A
A
9
0
A
8
NC
BHE
CE1 13
CC
14
A
9
OE
V
V
SS
WE
NC
15
COLUMN
DECODER
CE2
BLE
16
A
19
A
17
18
19
20
21
22
23
24
25
26
27
10
A
18
A
11
A
A
13
17
12
A
A
16
A
A
14
15
BHE
WE
I/O
I/O
0
7
CE2
CE1
V
V
CC
SS
I/O
I/O
6
5
1
2
OE
BLE
I/O
V
I/O
V
SS
CC
28 I/O
I/O
3
4
Cypress Semiconductor Corporation
Document #: 38-05476 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 14, 2006
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PRELIMINARY
CY7C1061DV33
Selection Guide
–10
10
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
125
25
mA
mA
Pin Configuration[1]
48-ball VFBGA
(Top View)
1
4
2
5
3
6
A
A
A
2
CE2
OE
BLE
0
1
A
B
C
I/O
A
A
BHE
CE1 I/O
8
4
3
0
I/O
10
A
A
6
I/O
I/O
I/O
2
5
9
1
I/O
I/O
A
I/O
V
CC
V
A17
NC
D
E
F
SS
3
7
11
A
V
CC
V
SS
I/O
16
12
4
I/O
A
A
I/O
5
I/O
I/O
6
14
15
13
14
A
A
I/O
7
G
H
I/O
NC
WE
13
12
15
A
A
A
A
19
A
A
10
9
11
18
8
Note:
1. NC pins are not connected on the die
Document #: 38-05476 Rev. *C
Page 2 of 10
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PRELIMINARY
CY7C1061DV33
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Latch-up Current......................................................>200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC Relative to GND[2] .... –0.5V to +4.6V
Operating Range
Ambient
DC Voltage Applied to Outputs
Range
Industrial
Temperature
VCC
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
–40°C to +85°C
3.3V ± 0.3V
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
–10
Parameter
VOH
VOL
VIH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Leakage Current
Output Leakage Current
Test Conditions[7]
VCC = Min., IOH = –4.0 mA
Min.
Max.
Unit
V
2.4
VCC = Min., IOL = 8.0 mA
0.4
V
2.0
–0.3
–1
VCC + 0.3
0.8
V
VIL
V
IIX
GND < VI < VCC
+1
µA
µA
mA
mA
IOZ
GND < VOUT < VCC, Output Disabled
–1
+1
ICC
VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC, OUT
I
= 0 mA CMOS levels
125
30
ISB1
Automatic CE Power-down
Current —TTL Inputs
CE2 <= VIL, Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
ISB2
Automatic CE Power-down
Current —CMOS Inputs
CE2 <= 0.3V, Max. VCC, CE > VCC – 0.3V,
25
mA
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
Capacitance[3]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
TSOP II
VFBGA
Unit
CIN
TA = 25°C, f = 1 MHz, VCC = 3.3V
6
8
8
pF
pF
COUT
10
Thermal Resistance[3]
Parameter
Description
Test Conditions
All-Packages
TBD
Unit
°C/W
°C/W
ΘJA
ΘJC
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
Thermal Resistance (Junction to Case)
TBD
AC Test Loads and Waveforms[4]
High-Z characteristics:
50Ω
R1 317Ω
3.3V
= 1.5V
OUTPUT
VTH
OUTPUT
Z = 50Ω
30 pF*
0
R2
351Ω
5 pF*
(a)
ALL INPUT PULSES
90%
INCLUDING
JIG AND
SCOPE
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
3.0V
90%
10%
(d)
10%
GND
Rise time > 1 V/ns
Fall time:
> 1 V/ns
(c)
Notes:
2. V (min.) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IL
IH
CC
3. Tested initially and after any design or process changes that may affect these parameters.
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). 100µs (t
) after reaching the minimum
power
DD
operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0V) voltage.
CCDR
DD
DD
Document #: 38-05476 Rev. *C
Page 3 of 10
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PRELIMINARY
CY7C1061DV33
AC Switching Characteristics Over the Operating Range [5]
–10
Parameter
Read Cycle
tpower
tRC
Description
VCC(typical) to the first access[6]
Min.
Max.
Unit
100
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tAA
Address to Data Valid
10
tOHA
tACE
Data Hold from Address Change
CE1 LOW/CE2 HIGH to Data Valid
OE LOW to Data Valid
3
10
5
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Low-Z
OE HIGH to High-Z[7]
1
3
0
5
5
CE1 LOW/CE2 HIGH to Low-Z[7]
CE1 HIGH/CE2 LOW to High-Z[7]
CE1 LOW/CE2 HIGH to Power-Up[8]
CE1 HIGH/CE2 LOW to Power-Down[8]
Byte Enable to Data Valid
Byte Enable to Low-Z
tPD
10
5
tDBE
tLZBE
tHZBE
Write Cycle[9, 10]
tWC
1
Byte Disable to High-Z
5
Write Cycle Time
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
7
tHA
0
tSA
0
tPWE
tSD
7
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[7]
5.5
0
tHD
tLZWE
tHZWE
3
WE LOW to High-Z[7]
5
tBW
Byte Enable to End of Write
7
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the Read cycle use
output loading shown in part a) of the AC test loads, unless specified otherwise.
6. t
7. t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
CC
POWER
, t
,t
, t
andt
, t
, t
, t
arespecifiedwithaloadcapacitanceof5pFasin(b)ofACTestLoads. Transitionismeasured ±200mVfromsteady-state
HZOE HZCE HZWE HZBE
LZOE LZCE \LZWE LZBE
voltage.
8. These parameters are guaranteed by design and are not tested.
9. The internal Write time of the memory is defined by the overlap of CE LOW (CE HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
1
2
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the
leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05476 Rev. *C
Page 4 of 10
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PRELIMINARY
CY7C1061DV33
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min.
Typ.
Max.
Unit
V
2
ICCDR
Data Retention Current
VCC = 2V , CE1 > VCC – 0.2V,
CE2 < 0.2V, VIN > VCC – 0.2V or
VIN < 0.2V
25
mA
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
[11]
tR
tRC
Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
V
DR
> 2V
V
CC
t
t
R
CDR
CE
]
Switching Waveforms
Read Cycle No. 1[12,13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
11. Full device operation requires linear V ramp from V to V
12. Device is continuously selected. OE, CE, BHE and/or BHE = V . CE = V .
> 50 µs or stable at V > 50 µs
CC(min.)
IH
CC
DR
CC(min.)
IL
2
13. WE is HIGH for Read cycle.
Document #: 38-05476 Rev. *C
Page 5 of 10
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PRELIMINARY
CY7C1061DV33
Switching Waveforms (continued)
Read Cycle No. 2(OE Controlled)[13,14]
ADDRESS
t
RC
CE1
CE2
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
ISB
Write Cycle No. 1(CE Controlled)[15,16,17]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATAI/O
Notes:
14. Address valid prior to or coincident with CE transition LOW and CE transition HIGH.
1
2
15. Data I/O is high-impedance if OE or BHE and/or BLE = V
.
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
1
17. CE is a shorthand combination of both CE and CE combined. It is active LOW.
1
2
Document #: 38-05476 Rev. *C
Page 6 of 10
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PRELIMINARY
CY7C1061DV33
Switching Waveforms (continued)
Write Cycle No. 2(BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
Write Cycle No. 3(WE Controlled, OE LOW)[15,16,17]
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Document #: 38-05476 Rev. *C
Page 7 of 10
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PRELIMINARY
CY7C1061DV33
Truth Table
CE1 CE2 OE WE BLE
BHE
X
I/O0–I/O7
I/O8–I/O15
High-Z
Mode
Power
H
X
L
L
L
L
L
L
L
X
L
X
X
L
X
X
H
H
H
L
X
X
L
High-Z
High-Z
Data Out
Data Out
High-Z
Data In
Data In
High-Z
High-Z
Power-down
Power-down
Read All Bits
Standby (ISB
)
)
X
High-Z
Standby (ISB
H
H
H
H
H
H
H
L
Data Out
High-Z
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
H
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
H
L
Data Out
Data In
High-Z
X
X
X
H
L
L
L
H
L
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
H
X
Data In
High-Z
H
X
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
CY7C1061DV33-10ZXI
CY7C1061DV33-10BVXI 51-85178 48-ball Very Fine Pitch Ball Grid Array (8 × 9.5 × 1 mm) (Pb-Free)
Package Type
10
51-85160 54-pin TSOP II (Pb-Free)
Industrial
Package Diagrams
54-pin TSOP Type II (51-85160)
51-85160-**
Document #: 38-05476 Rev. *C
Page 8 of 10
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PRELIMINARY
CY7C1061DV33
Package Diagrams (continued)
48-ball FBGA (8 x 9.5 x 1 mm) (51-85178)
BOTTOM VIEW
A1 CORNER
TOP VIEW
C
Ø0.05 M
Ø0.25 M
Ø0.30 0.05ꢀ(48X
A
C
B
A1 CORNER
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
0.75
3.75
4.00 0.10
A
A
B
4.00 0.10
B
0.15ꢀ(8X
51-85178. **
SEATING PLANE
C
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05476 Rev. *C
Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
CY7C1061DV33
Document History Page
Document Title: CY7C1061DV33 16-Mbit (1M x 16) Static RAM
Document Number: 38-05476
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Advance Data sheet for C9 IPP
201560
233748
See ECN
See ECN
SWI
RKF
*A
1.AC, DC parameters are modified as per EROS (Spec # 01-2165)
2.Pb-free offering in the ‘ordering information’
*B
469420
See ECN
NXR
Converted from Advance Information to Preliminary
Corrected typo in the Document Title
Removed –8 and –12 speed bins from product offering
Removed Commercial Operating Range
Changed 2G ball of FBGA and pin #40 of TSOPII from DNU to NC
Included the Maximum ratings for Static Discharge Voltage and Latch Up
Current on page #3
Changed ICC(Max) from 220 mA to 125 mA
Changed ISB1(Max) from 70 mA to 30 mA
Changed ISB2(Max) from 40 mA to 25 mA
Specified the Overshoot spec in footnote # 1.
Updated the Ordering Information Table
*C
499604
See ECN
NXR
Added note# 1 for NC pins
Updated Test Condition for ICC in DC Electrical Characteristics table
Updated the 48-ball FBGA Package
Document #: 38-05476 Rev. *C
Page 10 of 10
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