CY7C1069DV33-10BVXI [CYPRESS]
16-Mbit (2M x 8) Static RAM; 16兆位（ 2M ×8 ）静态RAM
| 型号： | CY7C1069DV33-10BVXI |
| 厂家： | 
CYPRESS |
| 描述： | 16-Mbit (2M x 8) Static RAM |
| 文件： | 总9页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1069DV33
PRELIMINARY
16-Mbit (2M x 8) Static RAM
Features
Functional Description
• High speed
The CY7C1069DV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE1
LOW and CE2 HIGH) and Write Enable (WE) inputs LOW.
— tAA = 10 ns
• Low active power
— ICC = 125 mA @ 10 ns
Reading from the device is accomplished by enabling the chip
(CE1 LOW and CE2 HIGH) as well as forcing the Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
See the truth table at the back of this data sheet for a complete
description of Read and Write modes.
• Low CMOS standby power
— ISB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
The input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a Write operation (CE1 LOW, CE2 HIGH, and WE
LOW).
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
The CY7C1069DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball very fine-pitch ball grid array (VFBGA) package.
• Available in Pb-free 54-pin TSOP II package and 48-ball
VFBGA packages
Logic Block Diagram
Pin Configuration
TSOP II
Top View
INPUT BUFFER
NC
1
2
3
4
5
6
54
53
NC
CC
V
V
SS
NC
52
51
50
NC
A
0
I/O
I/O
6
5
A
1
V
V
CC
SS
A
I/O
49 I/O
7
4
2
48
47
A
5
A
7
4
A
3
I/O0–I/O7
2M x 8
A
A
8
3
6
A
4
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A
A
7
ARRAY
9
2
A
A
5
10
11
12
A
8
1
A
A
A
9
6
0
NC
NC
CE1 13
CC
14
WE
CE2
A
7
OE
A
8
V
V
SS
A
9
NC
15
A
20
16
A
19
A
10
17
18
19
20
21
22
23
24
25
26
27
A
18
A
11
WE
CE2
OE
A
17
A
13
COLUMN
DECODER
12
A
A
15
16
A
A
14
I/O
I/O
0
3
V
V
CC
SS
I/O
NC
V
CE1
I/O
2
1
NC
V
CC
SS
NC
NC
Selection Guide
–10
10
Unit
ns
Maximum Access Time
Maximum Operating Current
125
25
mA
mA
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document #: 38-05478 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 14, 2006
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PRELIMINARY
CY7C1069DV33
Pin Configurations[1]
48-ball VFBGA
(Top View)
1
4
2
5
3
6
A
A
A
2
NC
NC
OE
NC
0
1
CE2
NC
A
B
C
A
A
CE1
4
3
A
A
6
I/O NC
0
NC I/O
4
5
I/O
A
I/O
A17
A
D
E
F
5
7
VSS
VCC
VSS
1
A
V
CC
I/O
I/O
6
18
16
2
I/O
7
A
A
15
NC
NC
I/O
3
14
A
A
NC
G
H
NC NC
WE
13
12
A
A
A
A
A
A
19
9
10
11
20
8
Note:
1. NC pins are not connected on the die
Document #: 38-05478 Rev. *C
Page 2 of 9
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PRELIMINARY
CY7C1069DV33
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Latch-up Current......................................................>200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V
Operating Range
Ambient
Range
Industrial
Temperature
VCC
DC Voltage Applied to Outputs
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
–40°C to +85°C
3.3V ± 0.3V
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
–10
Parameter
VOH
VOL
VIH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Leakage Current
Output Leakage Current
Test Conditions
VCC = Min., IOH = –4.0 mA
Min.
Max.
Unit
2.4
V
V
VCC = Min., IOL = 8.0 mA
0.4
2.0
–0.3
–1
VCC + 0.3
V
VIL
0.8
+1
V
IIX
GND < VI < VCC
µA
µA
mA
mA
IOZ
GND < VOUT < VCC, Output Disabled
–1
+1
ICC
VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC, OUT
I
= 0 mA CMOS levels
125
30
ISB1
Automatic CE Power-down
Current —TTL Inputs
CE2 < VIL, Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
ISB2
Automatic CE Power-down
Current —CMOS Inputs
CE2 < 0.3V, Max. VCC, CE > VCC – 0.3V,
25
mA
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
Capacitance[3]
Parameter
CIN
Description
Input Capacitance
I/O Capacitance
Test Conditions
TSOP II
VFBGA
Unit
TA = 25°C, f = 1 MHz, VCC = 3.3V
6
8
8
pF
pF
COUT
10
Thermal Resistance[3]
Parameter Description
Test Conditions
All-Packages
TBD
Unit
°C/W
°C/W
ΘJA
ΘJC
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
TBD
AC Test Loads and Waveforms[4]
50Ω
R1 317 Ω
= 1.5V
OUTPUT
VTH
3.3V
Z = 50Ω
0
OUTPUT
30 pF*
*Capacitive Load consists of all
R2
351Ω
components of the test environment
5 pF*
(a)
*Including
jig and
scope
All input pulses
3.0V
GND
90%
10%
90%
10%
(b)
Fall time:
> 1V/ns
Rise time > 1V/ns
(c)
Notes:
2. V (min.) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IL
IH
CC
3. Tested initially and after any design or process changes that may affect these parameters.
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). 100µs (t
) after reaching the minimum
power
DD
operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0V) voltage.
CCDR
DD
DD
Document #: 38-05478 Rev. *C
Page 3 of 9
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PRELIMINARY
CY7C1069DV33
[5]
AC Switching Characteristics Over the Operating Range
–10
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Unit
VCC(typical) to the First Access[6]
Read Cycle Time
100
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
10
tOHA
tACE
Data Hold from Address Change
CE1 LOW/CE2 HIGH to Data Valid
OE LOW to Data Valid
3
10
5
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Low-Z[7]
OE HIGH to High-Z[7]
1
3
0
5
5
CE1 LOW/CE2 HIGH to Low-Z[7]
CE1 HIGH/CE2 LOW to High-Z[7]
CE1 LOW/CE2 HIGH to Power-up[8]
CE1 HIGH/CE2 LOW to Power-down[8]
tPD
10
Write Cycle[9, 10]
tWC
Write Cycle Time
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
7
tHA
0
tSA
0
tPWE
tSD
7
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[7]
5.5
0
tHD
tLZWE
tHZWE
3
WE LOW to High-Z[7]
5
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the Read cycle use
output loading shown in part a) of the AC test loads, unless specified otherwise.
6. t
7. t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
CC
POWER
, t
, t
and t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from
HZOE HZSCE HZWE
steady-state voltage.
LZOE LZCE
LZWE
8. These parameters are guaranteed by design and are not tested.
9. The internal Write time of the memory is defined by the overlap of CE LOW/CE HIGH, and WE LOW. CE and WE must be LOW along with CE HIGH to initiate a
1
2
1
2
Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document #: 38-05478 Rev. *C
Page 4 of 9
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PRELIMINARY
CY7C1069DV33
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min.
Typ.
Max.
Unit
V
2
ICCDR
Data Retention Current
VCC = 2V , CE1 > VCC – 0.2V,
CE2 < 0.2V, VIN > VCC – 0.2V or
VIN < 0.2V
25
mA
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
[11]
tR
tRC
Data Retention Waveform
DATA RETENTION MODE
3V
3V
V
DR
> 2V
VCC
CE
t
t
R
CDR
Switching Waveforms
Read Cycle No. 1[12,13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2(OE Controlled)[13,14]
ADDRESS
CE1
t
RC
CE2
t
ASCE
OE
t
HZOE
t
DOE
t
t
HZSCE
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZSCE
t
PD
t
ICC
PU
50%
50%
ISB
Notes:
11. Full device operation requires linear V ramp from V to V
> 50 µs or stable at V > 50 µs
CC(min.)
CC
DR
.
CC(min.)
12. Device is continuously selected. CE = V , CE = V
1
IL
2
IH
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW and CE transition HIGH.
1
2
Document #: 38-05478 Rev. *C
Page 5 of 9
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PRELIMINARY
CY7C1069DV33
Switching Waveforms (continued)
Write Cycle No. 1(CE1 Controlled)[15,16,17]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
t
t
SD
HD
DATAI/O
Write Cycle No.2(WE Controlled, OE LOW)[15,16,17]
OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE1
H
CE2
X
OE
X
WE
X
I/O0–I/O7
High-Z
Mode
Power
Power-down
Power-down
Read All Bits
Write All Bits
Standby (ISB
)
)
X
L
X
X
High-Z
Data Out
Data In
High-Z
Standby (ISB
L
H
L
H
Active (ICC
)
)
)
L
H
X
L
Active (ICC
Active (ICC
L
H
H
H
Selected, Outputs Disabled
Notes:
15. Data I/O is high-impedance if OE = V
.
IH
16. If CE goes HIGH/CE LOW simultaneously with WE going HIGH, the output remains in a high–impedance state.
1
2
17. CE above is defined as a combination of CE and CE . It is active low.
1
2
Document #: 38-05478 Rev. *C
Page 6 of 9
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PRELIMINARY
CY7C1069DV33
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
10
CY7C1069DV33-10ZXI
51-85160 54-pin TSOP II (Pb-Free)
Industrial
CY7C1069DV33-10BVXI 51-85178 48-ball Very Fine Pitch Ball Grid Array (8 × 9.5 × 1 mm) (Pb-Free)
Package Diagrams
54-pin TSOP Type II (51-85160)
51-85160-**
Document #: 38-05478 Rev. *C
Page 7 of 9
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PRELIMINARY
CY7C1069DV33
Package Diagrams
48-ball FBGA (8 x 9.5 x 1 mm) (51-85178)
BOTTOM VIEW
A1 CORNER
TOP VIEW
C
Ø0.05 M
Ø0.25 M
Ø0.30 0.05ꢀ(48X
A
C
B
A1 CORNER
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
0.75
3.75
4.00 0.10
A
A
B
4.00 0.10
B
0.15ꢀ(8X
51-85178. **
SEATING PLANE
C
Document #: 38-05478 Rev. *C
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
CY7C1069DV33
Document History Page
Document Title: CY7C1069DV33 16-Mbit (2M x 8) Static RAM
Document Number: 38-05478
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Advance Data sheet for C9 IPP
201560
233748
See ECN
See ECN
SWI
RKF
*A
1.AC, DC parameters are modified as per EROS (Spec # 01-2165)
2.Pb-free Offering in the ‘Ordering Information
*B
469420
See ECN
NXR
Converted from Advance Information to Preliminary
Removed –8 and –12 speed bins from product offering
Removed Commercial Operating Range
Changed 2G ball of FBGA and pin #40 of TSOPII from DNU to NC
Included the Maximum ratings for Static Discharge Voltage and Latch Up
Current on page #3
Changed ICC(Max) from 220 mA to 100 mA
Changed ISB1(Max) from 70 mA to 30 mA
Changed ISB2(Max) from 40 mA to 25 mA
Specified the Overshoot spec in footnote # 1
Added Data Retention Characteristics table on page #5
Updated the 48-pin FBGA package
Updated the ordering Information table.
*C
499604
See ECN
NXR
Added note# 1 for NC pins
Updated Test Condition for ICC in DC Electrical Characteristics table
Updated the 48-ball FBGA Package
Document #: 38-05478 Rev. *C
Page 9 of 9
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