CY7C1219F-133AXC [CYPRESS]
Cache SRAM, 32KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | CY7C1219F-133AXC |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 32KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 存储 内存集成电路 静态存储器 CD |
| 文件： | 总15页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1219F
1-Mbit (32K x 36) Pipelined DCD Sync
SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
The CY7C1219F SRAM integrates 32,768 x 36 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
Control inputs (ADSC, ADSP, and ADV2), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
• 32K × 36-bit common I/O architecture
• 3.3V –5% and +10% core power supply (VDD
)
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
• 3.3V I/O supply (VDDQ
)
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100-pin TQFP package and pinout
• “ZZ” Sleep Mode option
The CY7C1219F operates from a +3.3V core power supply
while all outputs operate with a +3.3V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
166 MHz
3.5
133 MHz
4.0
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
240
40
225
40
mA
mA
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of this part.
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05416 Rev. *A
Revised April 10, 2004
CY7C1219F
Functional Block Diagram—32Kx36
ADDRESS
REGISTER
A0,A1,A
2
A[1:0]
MODE
Q1
ADV
CLK
BINARY
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQD,DQP
D
DQD, DQP
D
BYTE
BYTE
BW
D
WRITE REGISTER
WRITE DRIVER
DQC, DQP
BYTE
WRITE DRIVER
c
DQ
BYTE
WRITE REGISTER
c
,DQP
C
MEMORY
ARRAY
BW
C
DQs
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQP
DQP
DQP
DQP
A
B
C
DQ
BYTE
WRITE DRIVER
B
,DQP
B
E
DQ
BYTE
WRITE REGISTER
B
,DQP
B
BW
BW
B
A
D
DQ
BYTE
WRITE DRIVER
A
,
DQP
A
DQA , DQP
A
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
ZZ
CONTROL
Document #: 38-05416 Rev. *A
Page 2 of 15
CY7C1219F
Pin Configurations
100-pin TQFP
Top View
DQPc
DQc
1
2
3
4
5
80
79
78
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
DQc
VDDQ
77
76
75
74
73
72
71
70
69
68
67
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
6
7
8
9
10
11
12
13
14
15
16
17
VDD
66
65
64
63
62
61
60
CY7C1219F
(32K x 36)
NC
NC
VDD
VSS
ZZ
18
19
20
21
22
23
24
25
26
27
28
29
30
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
59
58
57
56
55
54
53
52
51
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
Document #: 38-05416 Rev. *A
Page 3 of 15
CY7C1219F
Pin Descriptions
Pin
A0, A1, A
TQFP
37,36,32,33
Type
Input-
Description
Address Inputs used to select one of the 32K address locations. Sampled at
34,35,44,45, Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
46,47,48,81,
are sampled active. A[1:0] are fed to the two-bit counter.
82,99,100
BWA, BWB, 93,94,95,96
BWC, BWD
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
Synchronous
.
to the SRAM. Sampled on the rising edge of CLK
88
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
GW
Synchronous of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW[A:D] and BWE).
87
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
BWE
Synchronous signal must be asserted LOW to conduct a byte write.
CLK
89
98
Input-
Clock
Input-
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
CE1
Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH.
97
92
86
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
CE2
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
CE3
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the
Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
83
84
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW. When
ADV
Synchronous asserted, it automatically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active
ADSP
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
85
64
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active
ADSC
ZZ
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal opera-
tion, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs
52,53,56,57,
58,59,62,63
68,69,72,73,
74,75,78,79
2,3,6,7,8,9,
12,13
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
DQP[A:D]
Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are
placed in a three-state condition.
18,19,22,23,
24,25,28,29,
1,30,51,80
VDD
VSS
15,41,65,
Power Supply Power supply inputs to the core of the device.
91
17,40,67,
90
Ground
Ground for the core of the device.
VDDQ
4,11,20,27,
54,61,70,
77
I/O Power Power supply for the I/O circuitry.
Supply
Document #: 38-05416 Rev. *A
Page 4 of 15
CY7C1219F
Pin Descriptions (continued)
Pin
TQFP
Type
Description
VSSQ
5,10,21,26,
55,60,71,
76
I/O Ground Ground for the I/O circuitry.
MODE
NC
31
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to VDD or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
No Connects. Not internally connected to the die.
14,16,38,39,
42,43,49,50,
66
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1219F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and BW[A:D]) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
then the write operation is controlled by BWE and BW[A:D]
signals. The CY7C1219F provides byte write capability that is
described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.
Because the CY7C1219F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQ are automatically three-stated
whenever a write cycle is detected, regardless of the state of
OE.
Accesses can
Strobe (ADSP)
be initiated with either the Processor Address
or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
self-timed write circuitry.
synchronous
Synchronous Chip Selects CE1, CE2, CE3 and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSC
Single Read Accesses
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BW[A:D]) are asserted active to conduct a write to the
desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQX is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the Write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tCO if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive
single read cycles are supported.
Because the CY7C1219F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQX inputs. Doing so will three-state the output drivers.
As a safety precaution, DQX are automatically three-stated
The CY7C1219F is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will three-state immediately
after the next clock rise.
Document #: 38-05416 Rev. *A
Page 5 of 15
CY7C1219F
whenever a write cycle is detected, regardless of the state of
OE.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
Burst Sequences
First
Second
Address
A1, A0
Third
Fourth
Address
A1, A0
Address
A1, A0
Address
A1, A0
The CY7C1219F provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Both read and write burst operations
are supported.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Address
A1, A0
Sleep Mode
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Truth Table [2, 3, 4, 5, 6]
Address
Operation
Used CE1 CE3 CE2 ZZ
ADSP ADSC ADV WRITE OE
CLK
DQ
Deselected Cycle,
None
None
None
None
None
None
H
L
L
L
L
X
X
H
X
H
X
L
L
L
L
L
X
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H
three-state
Power-down
Deselected Cycle,
Power-down
L
L
L-H
L-H
L-H
L-H
three-state
three-state
three-state
three-state
Deselected Cycle,
X
L
L
Power-down
Deselected Cycle,
Power-down
H
H
Deselected Cycle,
X
Power-down
ZZ Mode, Power-Down
X
L
L
L
L
L
X
X
L
L
L
L
L
X
X
H
H
H
H
H
X
H
L
L
L
L
L
L
X
L
L
H
H
H
H
X
X
X
L
L
L
X
X
X
X
X
X
L
X
X
X
L
H
H
H
X
L
H
X
L
X
three-state
Read Cycle, Begin Burst External
Read Cycle, Begin Burst External
Write Cycle, Begin Burst External
Read Cycle, Begin Burst External
Read Cycle, Begin Burst External
L-H
L-H
L-H
L-H
L-H
L-H
Q
three-state
D
Q
three-state
Q
H
L
Read Cycle, Continue
Next
H
Burst
Read Cycle, Continue
Burst
Next
X
X
X
L
H
H
L
H
H
L-H
three-state
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW and BWE = L or GW = L. WRITE = H when all Byte write enable signals
)
D
A
B
C
(BW , BW , BW , BW BWE, GW = H.
),
A
B
C
D
4. The DQ pins are controlled by the current cycle and the
signal.
is asynchronous and is not sampled with the clock.
OE
OE
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A:D]
after the
or with the assertion of
. As a result,
must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. is
OE
ADSC
a don't care for the remainder of the write cycle.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
OE
ADSP
6.
OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05416 Rev. *A
Page 6 of 15
CY7C1219F
Truth Table (continued)[2, 3, 4, 5, 6]
Address
Operation
Used CE1 CE3 CE2 ZZ
ADSP ADSC ADV WRITE OE
CLK
DQ
Read Cycle, Continue
Next
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
X
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
X
X
L
L-H
Q
Burst
Read Cycle, Continue
Burst
Next
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
three-state
Write Cycle, Continue
Next
L
D
Burst
Write Cycle, Continue
Burst
Next
L
L
D
Read Cycle, Suspend
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
Burst
Read Cycle, Suspend
Burst
H
L
three-state
Read Cycle, Suspend
Q
Burst
Read Cycle, Suspend
Burst
H
X
X
three-state
Write Cycle, Suspend
D
D
Burst
Write Cycle, Suspend
Burst
L
Truth Table for Read/Write[2, 3]
Function
Read
Read
Write byte A- (DQA and DQPA)
Write byte B- (DQBand DQPB)
Write byte C- (DQCand DQPC)
Write byte D- (DQDand DQPD)
Write all bytes
GW
BWE
BWA
X
H
L
H
H
H
L
X
BWB
X
H
H
L
H
H
L
X
BWC
BWD
X
H
H
H
H
L
L
X
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
X
X
H
H
H
L
H
L
X
Write all bytes
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
Description
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
40
2tCYC
Unit
mA
ns
ns
ns
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ inactive to exit snooze current
2tCYC
0
2tCYC
tRZZI
ns
Document #: 38-05416 Rev. *A
Page 7 of 15
CY7C1219F
Current into Outputs (LOW)......................................... 20mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883,Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch -up Current....................................................> 200 mA
Storage Temperature .................................... –65°C to +150°
Ambient Temperature with
Operating Range
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range Temperature (TA)
VDD
VDDQ
DC Voltage Applied to Outputs
Com’l
0°C to +70°C
3.3V −5%/+10% 3.3V −5%
in three-state........................................ –0.5V to VDDQ +0.5V
to VDD
DC Input Voltage......................................–0.5V to VDD+0.5V
Electrical Characteristics Over the Operating Range[7, 8]
Parameter
VDD
VDDQ
VOH
VOL
VIH
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[7]
Test Conditions
Min.
3.135
3.135
2.4
Max.
3.6
VDD
Unit
V
V
V
V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 3.3V
0.4
2.0
VDD
+
V
0.3V
VIL
IX
Input LOW Voltage[7]
VDDQ = 3.3V
–0.3
–5
0.8
5
V
µA
Input Load Current except ZZ GND ≤ VI ≤ VDDQ
and MODE
Input Current of MODE
Input = VSS
Input = VDD
Input = VSS
–30
–5
µA
µA
µA
5
Input Current of ZZ
Input = VDD
GND ≤ VI ≤ VDDQ, Output Disabled
30
5
µA
µA
IOZ
IDD
Output Leakage Current
VDD Operating Supply Current VDD = Max., IOUT = 0 mA,
–5
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
240
225
100
90
mA
mA
mA
mA
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
ISB4
Automatic CE
VDD = Max., Device Deselected, 6-ns cycle, 166 MHz
IN ≥ VIH or VIN ≤ VIL, f = fMAX
1/tCYC
Power-down
V
=
7.5-ns cycle, 133 MHz
Current—TTL Inputs
Automatic CE
VDD = Max., Device Deselected, All speeds
IN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
40
mA
Power-down
V
Current—CMOS Inputs
Automatic CE
V
DD = Max., Device Deselected, 6-ns cycle, 166 MHz
85
75
mA
mA
Power-down
or VIN ≤ 0.3V or VIN > VDDQ
–
7.5-ns cycle, 133 MHz
Current—CMOS Inputs
0.3V, f = fMAX = 1/tCYC
Automatic CE Power-down
VDD = Max., Device Deselected, All speeds
45
mA
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL, f = 0
Thermal Characteristics[9]
TQFP
Parameter
Description
Test Conditions
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard test methods and procedures
41.83
°C/W
(Junction to Ambient) for measuring thermal impedance, per EIA/JESD51
ΘJC
Thermal Resistance
9.99
°C/W
(Junction to case)
Notes:
7. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
.
8. Power-up: Assumes a linear ramp from 0v to V (min.) within 200 ms. During this time V < V and V
< V
DD
DD
IH
DD
DDQ
Document #: 38-05416 Rev. *A
Page 8 of 15
CY7C1219F
Capacitance[9]
Parameter
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
Max.
Unit
pF
pF
CIN
CCLK
CI/O
TA = 25°C, f = 1 MHz,
5
5
5
V
DD = 3.3V
VDDQ = 3.3V
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
R = 351Ω
≤1ns
≤ 1ns
INCLUDING
JIG AND
SCOPE
V = 1.5V
T
(a)
(c)
(b)
[14, 15]
Switching Characteristics Over the Operating Range
166 MHz
Min. Max.
1
133 MHz
Parameter
tPOWER
Description
Min.
Max.
Unit
ms
VDD(Typical) to the first Access[10]
1
Clock
tCYC
tCH
Clock Cycle Time
Clock HIGH
Clock LOW
6.0
2.5
2.5
7.5
3.0
3.0
ns
ns
ns
tCL
Output Times
tCO
tDOH
tCLZ
tCHZ
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[11, 12, 13]
3.5
4.0
ns
ns
ns
ns
ns
ns
ns
2.0
0
2.0
0
Clock to High-Z[11, 12, 13]
3.5
3.5
4.0
4.5
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
tADS
tADVS
LOW to Output Low-Z[11, 12, 13]
OE
0
0
OE HIGH to Output High-Z[11, 12, 13]
3.5
4.0
Address Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
,
ADSC ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
tWES
Notes:
Set-up Before CLK Rise
GW, BWE, BW[A : D]
9. Tested initially and after any design or process change that may affect these parameters.
10. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above V minimum initially before a read or write operation
DD
can be initiated.
11. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
12. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing reference level is 1.5V when V
= 3.3V.
DDQ
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05416 Rev. *A
Page 9 of 15
CY7C1219F
Switching Characteristics Over the Operating Range (continued)[14, 15]
166 MHz
Min. Max.
133 MHz
Min. Max.
Parameter
Description
Data Input Set-up Before CLK Rise
Chip Enable Set-up Before CLK Rise
Unit
ns
ns
tDS
tCES
1.5
1.5
1.5
1.5
Hold Times
tAH
tADH
tADVH
tWEH
tDH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
,
Hold After CLK Rise
ADSP ADSC
ADV Hold After CLK Rise
,
,
GW BWE BW[A:D] Hold After CLK Rise
Data Input Hold After CLK Rise
tCEH
Chip Enable Hold After CLK Rise
Switching Waveforms
Read Timing[16]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,BW[A:D]
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
OEV
CO
t
t
CHZ
t
t
t
OELZ
OEHZ
DOH
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A1)
Data IOut (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
16. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05416 Rev. *A
Page 10 of 15
CY7C1219F
Switching Waveforms (continued)
Write Timing[16, 17]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A:D]
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
Data in (D)
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
17.
[A:D]
Document #: 38-05416 Rev. *A
Page 11 of 15
CY7C1219F
Switching Waveforms (continued)
Read/Write Timing[16, 18]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW[A:D]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Single WRITE
DON’T CARE
BURST READ
Back-to-Back
WRITEs
UNDEFINED
Note:
18.
ADSP or ADSP .GW is HIGH.
The data bus (Q) remains in High-Z following a WRITE cycle, unless a new read access initiated by
Document #: 38-05416 Rev. *A
Page 12 of 15
CY7C1219F
Switching Waveforms (continued)
ZZ Mode Timing [19, 20]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
Package
Name
A101
Operating
Range
Commercial
(MHz)
Ordering Code
CY7C1219F-133AC
Package Type
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
133
Please contact your local Cypress sales representative for availability of 166MHz speed grade option.
Notes:
19. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
20. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05416 Rev. *A
Page 13 of 15
CY7C1219F
Package Diagram
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. PowerPC is a registered trademark
of IBM. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05416 Rev. *A
Page 14 of 15
CY7C1219F
Document History Page
Document Title: CY7C1219F 32K x 36 Pipelined DCD Sync SRAM
Document Number: 38-05416
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
130279
01/19/04
NJY
New Data Sheet
*A
213321
See ECN
VBL
Shade selection guide and characteristics table for non-active part number
Document #: 38-05416 Rev. *A
Page 15 of 15
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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