CY7C1302BV25-133BZC [CYPRESS]
QDR SRAM, 512KX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165;
| 型号： | CY7C1302BV25-133BZC |
| 厂家： | 
CYPRESS |
| 描述： | QDR SRAM, 512KX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165 静态存储器 |
| 文件： | 总26页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CY7C1302BV25
Preliminary
9 Mb Burst of 2 Pipelined SRAM with QDR Architecture
Features
Functional Description
• Separate Independent Read and Write Data Ports
—Supports concurrent transactions
• 167 MHz Clock for High Bandwidth
—2.5 ns Clock-to-Valid access time
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read &
Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
—SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mis-matches
• Single multiplexed address input bus latches address
inputs for both READ and WRITE ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
The CY7C1302BV25 is a 2.5V Synchronous Pipelined
SRAMs equipped with QDR architecture. QDR architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data inputs to
support Write operations. Access to each port is accomplished
through a common address bus. The Read address is latched
on the rising edge of the K clock and the Write address is
latched on the rising edge of K clock. QDR has separate data
inputs and data outputs to completely eliminate the need to
“turn-around” the data bus required with common I/O devices.
Accesses to the CY7C1302BV25 Read and Write ports are
completely independent of one another. All accesses are initi-
ated synchronously on the rising edge of the positive input
clock (K). In order to maximize data throughput, both Read
and Write ports are equipped with Double Data Rate (DDR)
interfaces. Therefore, data can be transferred into the device
on every rising edge of both input clocks (K and K) and out of
the device on every rising edge of the output clock (C and C)
thereby maximizing performance while simplifying system de-
sign. Each address location is associated with two 18-bit
words that burst sequentially into or out of the device.
• 13x15 mm 1.0 mm pitch fBGA package, 165 ball
(11x15 matrix) Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
Depth expansion is accomplished with a Port Select input for
each port. Each Port Selects allow each port to operate inde-
pendently.
• Variable Impedance HSTL
Configurations
CY7C1302BV25 – 512 Kb x 18
All synchronous inputs pass through input registers controlled
by the K orK input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1302BV25)
D[17:0]
18
Write
Write
Data Reg
Data Reg
Address
Register
A
(17:0)
Address
Register
A(17:0)
18
18
256Kx18 256Kx18
Memory Memory
Array
Array
K
CLK
Gen.
RPS
Control
Logic
K
C
C
Read Data Reg.
36
18
Vref
18
Reg.
Reg.
Reg.
18
18
Control
Logic
WPS
BWS0
18
Q[17:0]
BWS1
CypressSemiconductorCorporation
Document #: 38-05XXX Rev. **
•
3901NorthFirstStreet
•
SanJose
•
CA 95134
•
408-943-2600
Revised April 14, 2003
CY7C1302BV25
Preliminary
Selection Guide[1]
CY7C1302BV25
-200
CY7C1302BV25
-167
CY7C1302BV25
CY7C1302BV25
-100
-133
Maximum Operating Frequency
(MHz)
200 MHz
167 MHz
133 MHz
100 MHz
Maximum Operating Current (mA)
TBD
TBD
TBD
TBD
Note:
1. Sheaded cells indicate advanced information.
Document #: 38-05XXX Rev. **
Page 2 of 27
CY7C1302BV25
Preliminary
Pin Configuration - CY7C1302BV25 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
Gnd/
NC/
36M
NC/
Gnd/
72M
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
144M
WPS
A
BWS1
NC
K
NC
BWS0
A
RPS
A
18M
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Q9
NC
D9
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
Q7
D10
Q10
Q11
D12
Q13
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
D11
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
VDDQ
VDDQ
VDDQ
D6
Q12
D13
VREF
NC
NC
G
H
J
NC
VDDQ VDDQ
VREF
Q4
D14
Q14
D15
D16
Q16
Q17
A
VDDQ
VDDQ
VDDQ
VSS
VSS
A
K
L
NC
D3
Q15
NC
NC
M
N
P
R
Q1
D17
NC
NC
A
C
A
D0
TCK
A
A
C
A
A
TMS
Document #: 38-05XXX Rev. **
Page 3 of 27
CY7C1302BV25
Preliminary
Pin Definitions
Name
I/O
Description
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1302BV25 – D[17:0]
D[x:0]
WPS
Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When assert-
ed active, a write operation is initiated. Deasserting will deselect the Write port. Dese-
lecting the Write port will cause D[x:0] to be ignored.
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3 - active LOW. Sampled on the rising edge of the K and
K clocks during write operations. Used to select which byte is written into the device
during the current portion of the write operations.
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous
CY7C1302BV25 - BWS0 controls D[8:0] and BWS1 controls D[17:9].
Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the cor-
responding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active Read operations
and on the rising edge of K for Write operations. These address inputs are multiplexed
for both Read and Write operations. Internally, the device is organized as 512 Kbx 18
(2 arrays each of 256 Kb x 18) for CY7C1302BV25. These inputs are ignored when the
appropriate port is deselected.
A
Input-
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K. when in single clock mode. When the Read port is deselected,
Q[x:0] are automatically three-stated.
Q[x:0]
Outputs-
Synchronous
CY7C1302BV25 - Q[17:0]
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the K clock. Each
read access consists of a burst of two sequential 18-bit or 36-bit transfers.
RPS
Input-
Synchronous
Positive Output Clock, input. C is used in conjunction withC to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
C
C
K
Input-Clock
Input-Clock
Input-Clock
Negative Output Clock, input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board cack to the controller. See application example for further details.
Positive Input Clock, input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[x:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented
K
Input-Clock
Input
to the device and to drive out data through Q
when in single clock mode.
[x:0]
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. Q[x:0]output impedance are set to 0.2 x RQ, where RQ is
a resistor connected between ZQ and ground. Alternately, this pin can be connected
directly to VDD, which enables the minimum impedance mode. This pin cannot be con-
nected directly to GND or left unconnected.
ZQ
Document #: 38-05XXX Rev. **
Page 4 of 27
CY7C1302BV25
Preliminary
Pin Definitions
TDO
TCK
TDI
Output
Input
Input
Input
Input
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
TMS
Address expansion for 18M. This pin is not connected to the die. Can be tied to any
voltage level.
NC/18M
Input
Address expansion for 36M. This pin is not connected to the die. Can be tied to any
voltage level .
NC/36M
GND/72M
NC/72M
GND/144M
GND/288M
NC
Input
Input
Input
Input
Address expansion for 72M. This pin has to be tied to GND.
Address expansion for 72M. This pin can be tied to any voltage level.
Address expansion for 144M. This pin has to be tied to GND.
Address expansion for 288M. This pin has to be tied to GND.
No Connect Pins. These are not connected to the die.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as A/C measurement points.
VDD
Power supply inputs to the core of the device. Should be connected to 2.5V power
supply.
Power Supply
Ground
VSS
Ground for the device. Should be connected to ground of the system.
VDDQ
Power supply inputs for the outputs of the device. Should be connected to 1.5V power
supply.
Power Supply
device, triggered by the C clock. On the following C clock rise
the corresponding lower order word of data is driven onto the
Q[17:0]. On the subsequent rising edge of C the higher order
data word is driven onto the Q[17:0]. The requested data will be
valid 2.5ns from the rising edge of the output clock (C or C,
167 MHz device). With the separate Input and Output ports
and the internal logic determining when the device should
drive the data bus, the QDR architecture has eliminated the
need for an output enable input to control the state of the out-
put drivers.
Introduction
Functional Overview
The CY7C1302BV25 is a synchronous pipelined Burst SRAM
equipped with both a Read Port and a Write Port. The Read
port is dedicated to Read operations and the Write Port is ded-
icated to Write operations. Data flows into the SRAM through
the Write port and out through the Read Port. These devices
multiplex the address inputs in order to minimize the number
of address pins required. The device latches the Read address
on the rising edge of the positive input clock (K) and latches
the Write address on the rising edge of the negative input clock
(K). By having separate Read and Write ports, this architecture
completely eliminates the need to “turn-around” the data bus
and avoids any possible data contention, thereby simplifying
system design.
Read accesses can be initiated on every rising edge of the
positive input clock (K). Doing so will pipeline the data flow
such that data is transferred out of the device on every rising
edge of the output clocks (C and C). The CY7C1302BV25 will
deliver the most recent data for the address location being
accessed. This includes forwarding data when a Read and
Write transactions to the same address location are initiated
on the same clock rise.
Accesses for both ports are initiated by the positive input clock
(K). All synchronous input timing is referenced from the rising
edge of the input clocks (K and K) and all output timing is
referenced to the output clocks (C and C) or K and K when in
single clock mode.
When the read port is deselected, the CY7C1302BV25 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the positive output clock (C). This will allow
for a seamless transition between devices without the inser-
tion of wait states.
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All synchro-
nous data outputs (Q[x:0]) pass through output registers con-
trolled by the rising edge of the output clocks (C and C).
The CY7C1302BV25 is equipped with internal logic that syn-
chronously controls the state of the output drivers. The logic
inside the device determines when the output drivers need to
be active or inactive. This advanced logic eliminates the need
for an asynchronous output enable (OE) since the device will
automatically enable/disable the output drivers during the
proper cycles. The CY7C1302BV25 will automatically pow-
er-up in a deselected state with the outputs in a three state
condition.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers. RPS and WPS are controlled by the
rising edge of the input clock (K). BWS[0:x] are controlled by
the rising edges of input clocks (K and K).
Read Operations
Read operations are initiated by asserting RPS active at the
rising edge of the positive input clock (K). The address pre-
Write Operations
sented to A
is stored in the Read address register. Be-
[17:0]
cause the CY7C1302BV25 is a 36-bit memory, it will access
two 18-bit data words with each read operation. Following the
next K clock rise the data is available to be latched out of the
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same clock
rise (K) the data presented to D
is stored into the lower
[17:0]
Document #: 38-05XXX Rev. **
Page 5 of 27
CY7C1302BV25
Preliminary
18-bit Write Data register providedBWS[1:0] are both asserted
active. On the subsequent rising edge of the negative input
clock or double clock mode. The clock mode should not be
changed during device operation.
clock (K), the information presented to A
stored in the Write Address Register and the information pre-
is latched and
[17:0]
Concurrent Transactions
The Read and Write ports on the CY7C1302BV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the transac-
tion on the other port. Should the Read and Write ports access
the same location on the rising edge of the positive input clock,
the information presented to the D [17:0] will be forwarded to the
Q[17:0] such that no latency is required to access valid data.
Coherency is conducted on cycle boundaries. Once the sec-
ond word of data is latched into the device, the write operation
is considered completed. At this point, any access to that ad-
dress location will receive that data until altered by a subse-
quent Write operation. Coherency is not maintained for Write
operations initiated in the cycle after a Read.
sented to D[17:0] is also stored into the upper 18-bit Write Data
Register provided BWS
are both asserted active. The 36
[1:0]
bits of data are then written into the memory array at the spec-
ified location.
Write accesses can be initiated on every rising edge of the
positive clock. Doing so will pipeline the data flow such that
18-bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
Byte Write operations are supported by the CY7C1302BV25.
A write operation is initiated by selecting the write port using
WPS. The bytes that are written are determined by BWS0 and
BWS1 which are sampled with each set of 18-bit data word.
Asserting the appropriate Byte Write Select input during the
data portion of a write will allow the data being presented to be
latched and written into the device. De-asserting the Byte
Write Select input during the data portion of a write will allow
the data stored in the device for that byte to remain unaltered.
This feature can be used to simplify READ/MODIFY/WRITE
operations to a Byte Write operation.
Depth Expansion
The CY7C1302BV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the positive input clock only (K).
Each port select input can deselect the specified port. Dese-
lecting a port will not affect the other port. All pending transac-
tions (Read and Write) will be completed prior to the device
being deselected.
When deselected, the write port will ignore all inputs.
Single Clock Mode
The CY7C1302BV25 can be used with a single clock mode. In
this mode the device will recognize only the pair of input clocks
(K and K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C to VDD. During power-up, the device
will sense the single clock input and operating in either single
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V to allow the SRAM to adjust its
SS
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±10% is between 175Ohms and 350Ohms, with
VDDQ=1.5V. The output impedance is adjusted every 1024 cy-
cles to adjust for drifts in supply voltage and temperature.
Document #: 38-05XXX Rev. **
Page 6 of 27
CY7C1302BV25
Preliminary
Application Example
CY7C1302BV25 in an Application
VT=VDDQ/2
SRAM #4
SRAM #1
Q
D
Q
D
18
18
18
R=50Ohms
18
Memory
Controller
72
18
18
Q
Din
Add.
Cntr.
72
2
2
CLK/CLK (input)
CLK/CLK (output)
R=50Ohms
VT=VDDQ/2
Document #: 38-05XXX Rev. **
Page 7 of 27
CY7C1302BV25
Preliminary
Truth Table [
2,3,4,5,6]
Operation
K
RPS
H
WPS
L
DQ
DQ
Write Cycle:
L-H
D(A+0)at
K(t+1) ¦
D(A+1) at
K(t+1) ¦
Load address, input write data on 2 consecutive K and
K rising edges.
Read Cycle:
L-H
L
H
Q(A+0) at
C(t+1)¦
Q(A+1) at
C(t+1) ¦
Load address, wait one cycle, read data on 2 consec-
utive C and C rising edges.
NOP: No Operation
L-H
H
X
H
X
High-Z
High-Z
Standby: Clock Stopped
Stopped
Previous
State
Previous
State
Note:
2. X=Don't Care, H=Logic HIGH, L=Logic LOW.
3. Device will power-up deselected and the outputs in a three-state condition.
4. A represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.
5. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
6. It is recommended that K =K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
Document #: 38-05XXX Rev. **
Page 8 of 27
CY7C1302BV25
Preliminary
[7]
Write Descriptions (CY7C1302BV25)
Operation
BWS0
BWS1
K
K
Comments
Write Initiated
L
L
L-H
-
Both bytes (D[17:0]) are written into the lower order 18-bit
write buffer device during this portion of a write operation.
Write Completed
- Write initiated
on previous K
clock rise
L
L
-
L-H
Both bytes (D[17:0]) are written into the higher order 18-bit
write buffer device during this portion of a write operation.
The contents of the entire 36-bits write buffer are written
into the memory array.
Write Initiated
L
L
H
H
L-H
-
-
Only Byte 0 (D[8:0]) is written into the lower order 18-bit write
buffer of the device during this portion of a write operation.
Byte 1 (D
) remains unaltered
[17:9]
Write Completed
- Write initiated
on previous K
clock rise
L-H
Only Byte 0 (D[8:0]) is written into the higher order 18-bit
write buffer of the device during this portion of a write op-
eration. Byte 1 (D[17:9]) remains unaltered. Byte 0 is then
written into the memory array.
Write Initiated
H
H
L
L
L-H
-
-
Only Byte 1 (D[17:9]) is written into the lower order 18-bit
write buffer of the device during this portion of a write op-
eration. Byte 0 (D[8:0]) remains unaltered
Write Complet-
ed - Write initiat-
ed on previous K
clock rise
L-H
Only Byte 1 (D[17:9]) is written into the higher order 18-bit
write buffer of the device during this portion of a write op-
eration. Byte 0(D[8:0]) remains unaltered. Byte 1 is then
written into the memory array.
Write - NO-OP
H
H
H
H
L-H
-
-
No data is written into the device during this portion of a
write operation.
Write - NO-OP
L-H
No data is written into the device during this portion of a
write operation.
Note:
7. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table.BWS0, BWS1 (CY7C1302BV25) ) can be altered on different
portions of a write cycle, as long as the set-up and hold requirements are achieved.
Document #: 38-05XXX Rev. **
Page 9 of 27
CY7C1302BV25
Preliminary
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Ambient
Supply Voltage on VDD Relative to GND ....... –0.5V to +3.6V
Range
Temperature[9]
VDD
VDDQ
DC Voltage Applied to Outputs
in High Z State[8] ................................. –0.5V to VDDQ + 0.5V
Com’l
0°C to +70°C
2.5 ±100 mV 1.4V to 1.9V
DC Input Voltage[8] .............................–0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range[10]
Parameter
VDD
Description
Test Conditions
Min.
2.4
Max.
2.6
Unit
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[8]
Input Load Current
VDDQ
VOH
VOL
1.4
1.9
V
IOH = -2.0 mA, nominal impedance
IOL = 2.0 mA, nominal impedance
VDDQ/2+0.3
VSS
VDDQ
VDDQ/2–0.3
VDDQ+0.3
VREF–0.1
5
V
V
VIH
VREF+0.1
–0.3
V
VIL
V
IX
GND < VI < VDDQ
-5
mA
mA
IOZ
Output Leakage
Current
GND < VI < VDDQ, Output Disabled
-5
5
VREF
IDD
Input Reference Volt-
age
Typical value = 0.75V
0.68
0.95
V
VDD Operating Supply VDD = Max.,
IOUT = 0 mA,
5.0nscycle, 200MHz
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
6.0nscycle, 167MHz
7.5nscycle, 133MHz
10 ns cycle, 100 MHz
5.0nscycle, 200MHz
6.0nscycle, 167MHz
7.5nscycle, 133MHz
10 ns cycle, 100 MHz
f = fMAX = 1/tCYC
ISB1
Automatic
Power-Down
Current
Max. VDD, Both
Ports Deselected,
VIN Š VIH or
VIN < VIL f =
fMAX = 1/tCYC,
Inputs Static
AC Input Requirements Over the Operating Range
Test Conditions Min.
VREF + 0.2
Parameter
Description
Typ.
Max.
VIH
Input High (Logic 1)
Voltage
–
–
VIL
Input Low (Logic 0)
Voltage
–
–
VREF - 0.2
Notes:
8. Minimum voltage equals -2.0V for pulse duration less than 20 ns.
9. TA is the “instant on” case temperature.
10. All voltages referenced to ground.
Document #: 38-05XXX Rev. **
Page 10 of 27
CY7C1302BV25
Preliminary
Switching Characteristics Over the Operating Range[1,11,12,13]
-200
-167
-133
-100
Cypress
Parameter
Consortium
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
[14]
tPower
VCC (typical) to the first access
read or write
10
10
10
10
us
Cycle Time
tCYC
tKHKH
tKHKL
K Clock and C Clock Cycle Time 5.0
Input Clock (K/K and C/C) HIGH 2.0
6.0
2.4
7.5
3.2
10.0
3.5
ns
ns
tKH
tKL
tKLKH
tKHKH
Input Clock (K/K and C/C) LOW 2.0
2.4
2.7
3.2
3.4
3.5
4.4
ns
ns
tKHKH
K/K Clock rise to K/K Clock rise 2.4
and C/C to C/C rise
(rising edge to rising edge)
2.6
1.5
3.3
2.0
4.1
2.5
5.4
3.0
tKHCH
tKHCH
K/K Clock rise to C/C clock rise
(rising edge to rising edge)
0.0
0.0
0.0
0.0
ns
Set-up Times
tSA
tSA
tSC
tSD
Address set-up to clock (K and
K) rise
0.6
0.7
0.7
0.7
0.8
0.8
0.8
1.0
1.0
1.0
ns
ns
ns
tSC
tSD
Control set-up to clock (K andK) 0.6
rise (RPS, WPS, BWS0, BWS1)
D[17:0] set-up to clock (K and K)
rise
0.6
Hold Times
tHA
tHA
tHC
Address Hold after clock (K and 0.6
K) rise
0.7
0.7
0.8
0.8
1.0
1.0
ns
ns
tHC
Control signals Hold after clock
(K andK) rise (RPS, WPS,
BWS0, BWS1)
0.6
tHD
tHD
D[17:0] Hold after clock (K andK) 0.6
rise
0.7
0.8
1.0
ns
Output Times
tCO
tCHQV
C/C Clock rise (or K/K in single
clock mode) to Data Valid[12]
2.3
2.3
2.5
2.5
3.0
3.0
3.0
3.0
ns
ns
ns
ns
tDOH
tCHZ
tCHQX
tCHZ
tCLZ
Data Output Hold After Output
C/C clock Rise (Active to Active)
0.8
1.2
1.2
1.2
1.2
1.2
1.2
Clock (C andC) rise to High-Z
[12, 13]
(Active to High-Z)
tCLZ
Clock (C andC) rise to Low-Z[12, 0.8
13]
Notes:
11. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250W, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.
12. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
13. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO
.
14. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a
read or write operation can be initiated.
Document #: 38-05XXX Rev. **
Page 11 of 27
CY7C1302BV25
Preliminary
Capacitance[15]
Parameter
Description
Test Conditions
Max.
TBD
TBD
TBD
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 2.5V.
VDDQ = 1.5V
CCLK
Clock Input Capacitance
Output Capacitance
pF
CO
pF
Note:
15. Tested initially and after any design or process change that may affect these parameters.
g
V
/2
DDQ
V
/2
DDQ
V
REF
V
V
/2
REF
R=50Ω
DDQ
OUTPUT
[11]
ALL INPUT PULSES
1.25V
Z =50Ω
0
OUTPUT
Device
Under
Test
R =50Ω
L
0.75V
Device
Under
Test
0.25V
5 pF
V
=0.75V
REF
ZQ
RQ=
250Ω
ZQ
RQ=
250Ω
(a)
1302V25-2
INCLUDING
JIG AND
SCOPE
1304-3
(b)
Document #: 38-05XXX Rev. **
Page 12 of 27
CY7C1302BV25
Preliminary
Switching Waveforms
Read/Deselect Sequence [16]
tCYC
tKHKH
tKL
tKH KH
K
tKH
tKL
K
tKH
tSA
A[x:0]
A
B
C
tSC
tHA
tHC
RPS
Q(A+1)
Q(B+1)
Q(C+1)
Q(A)
Q(B)
Q(C)
Data Out
tCO
tCLZ
tCHZ
tKHCH
C
C
tDOH
tCO
tDOH
= UNDEFINED
= DON’T CARE
Note:
16. Device originally deselected.
Document #: 38-05XXX Rev. **
Page 13 of 27
CY7C1302BV25
Preliminary
Switching Waveforms
Write/Deselect Sequence [17,18]
tCYC
tKL
K
K
tKH
tKL
tSA
A[x:0]
A
B
C
tSC
tHA
tHC
WPS
tSC
tHC
BWSx
D(B+1)
D(C)
D(C+1)
D(A)
D(B)
D(A+1)
Data In
tHD
tSD
= DON’T CARE
= UNDEFINED
Notes:
17. C and C reference to Data Outputs and do not affect Writes.
18. Activity on the BWSx LOW = Valid, Byte writes allowed, see Byte write table for details.
Document #: 38-05XXX Rev. **
Page 14 of 27
CY7C1302BV25
Preliminary
Switching Waveforms
Read/Write/Deselect Sequence[19,19,20]
K
K
A[x:0]
E
D
A
B
B
G
C
WPS
RPS
BWSx
D[x:0]
D(A+1)
D(B+1)
Q(E)
D(A)
D(B)
D(C)
D(C+1)
Q(B)
D(D)
D(D+1)
Q(G)
Write Data Forwarded
Q(E+1)
Q(B+1)
Q[x:0]
Q(G+1)
C
C
= UNDEFINED
= DON’T CARE
Notes:
19. Read Port previously deselected.
20. BWS[1:0] both assumed active.
Document #: 38-05XXX Rev. **
Page 15 of 27
CY7C1302BV25
Preliminary
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port–Test Clock
Boundary Scan Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document #: 38-05XXX Rev. **
Page 16 of 27
CY7C1302BV25
Preliminary
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
SAMPLE Z
BYPASS
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
SAMPLE / PRELOAD is a 1149.1 mandatory instruction.
When the SAMPLE / PRELOAD instructions are loaded into
the instruction register and the TAP controller is in the Cap-
ture-DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the "extest output bus tristate", is
latched into the preload register during the "Update-DR" state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the
boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the "Shift-DR" state. During "Update-DR", the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set LOW to enable the output when the device is
powered-up, and also when the TAP controller is in the
"Test-Logic-Reset" state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05XXX Rev. **
Page 17 of 27
CY7C1302BV25
Preliminary
TAP Controller State Diagram[21]
TEST-LOGIC
RESET
1
0
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
SELECT
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
21. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05XXX Rev. **
Page 18 of 27
CY7C1302BV25
Preliminary
TAP Controller Block Diagram
0
Bypass Register
Selection
TDI
Selection
TDO
Circuitry
2
1
0
0
0
Circuitry
Instruction Register
29
31 30
.
.
2
1
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range [10,22, 23]
Parameter
VOH1
VOH2
VOL1
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min.
1.7
Max.
Unit
V
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
2.1
V
0.7
0.2
V
VOL2
V
VIH
1.7
–0.3
−5
VDD+0.3
0.7
V
VIL
Input LOW Voltage
V
IX
Input and Output Load Current
GND ≤ V ≤ VDDQ
5
µA
I
Notes:
22. Overshoot: VIH(AC)<VDD+0.5V for t <tTCYC/2. Undershoot: VIL(AC)<0.5V for t <tTCYC /2. Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200 ms.
23. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table
Document #: 38-05XXX Rev. **
Page 19 of 27
CY7C1302BV25
Preliminary
TAP AC Switching Characteristics Over the Operating Range [24,25]
Parameter
tTCYC
Description
Min.
Max.
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
tTF
10
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
10
10
10
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK clock rise
TDI Hold after clock rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after clock rise
Output Times
tTDOV
tTDOX
Notes:
TCK Clock LOW to TDO valid
20
ns
ns
TCK Clock LOW to TDO invalid
0
24. TCS and TCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
25. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.
Document #: 38-05XXX Rev. **
Page 20 of 27
CY7C1302BV25
Preliminary
TAP Timing and Test Conditions[25]
1.25V
50Ω
ALL INPUT PULSES
TDO
2.5V
Z =50Ω
0
1.25V
C =20pF
L
0V
GND
(a)
tTL
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Document #: 38-05XXX Rev. **
Page 21 of 27
CY7C1302BV25
Preliminary
Identification Register Definitions
Value
CY7C1302BV25
000
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Description
Version number.
01011010010010101
00000110100
1
Defines the type of SRAM.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
106
Boundary Scan
Instruction Codes
Instruction
Code
Description
EXTEST
IDCODE
000
001
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and plac-
es the register between TDI and TDO. This operation
does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the bound-
ary scan register between TDI and TDO. Forces all
SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the
boundary scan register between TDI and TDO. Does
not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This
operation does not affect SRAM operation.
Boundary Scan Order
Boundary Scan Order
Bit #
Bump ID
6R
Bit #
8
Bump ID
9R
0
1
2
3
4
5
6
7
6P
9
11P
6N
10
11
12
13
14
15
10P
7P
10N
9P
7N
7R
10M
11N
9M
8R
8P
Document #: 38-05XXX Rev. **
Page 22 of 27
CY7C1302BV25
Preliminary
Boundary Scan Order
Boundary Scan Order
Bit #
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Bump ID
Bit #
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Bump ID
9N
8A
11L
7A
11M
7B
9L
6B
10L
6A
11K
5B
10K
5A
9J
4A
9K
5C
10J
4B
11J
3A
11H
Internally Pre-set LOW
10G
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1J
9G
11F
11G
9F
10F
11E
10E
10D
9E
10C
11D
9C
9D
11B
11C
9B
10B
11A
Internally Pre-set LOW
9A
8B
7C
6C
2J
3K
3J
2K
Document #: 38-05XXX Rev. **
Page 23 of 27
CY7C1302BV25
Preliminary
Boundary Scan Order
Bit #
88
Bump ID
1K
89
2L
90
3L
91
1M
1L
92
93
3N
3M
1N
2M
3P
94
95
96
97
98
2N
2P
99
100
101
102
103
104
1P
3R
4R
4P
5P
105
5N
5R
106
I
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Package Type
13 x 15 mm FBGA
200
CY7C1302BV25-200BZC
CY7C1302BV25-167BZC
CY7C1302BV25-133BZC
CY7C1302BV25-100BZC
BB165D
BB165D
BB165D
BB165D
Commercial
167
13 x 15 mm FBGA
13 x 15 mm FBGA
13 x 15 mm FBGA
133
100
Document #: 38-05XXX Rev. **
Page 24 of 27
CY7C1302BV25
Preliminary
165-ball FBGA (13 x 15 x 1.4 mm) BB165D
51-85180 **
Document #: 38-05XXX Rev. **
Page 25 of 27
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license underpatent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
CY7C1302BV25
Preliminary
Document Title:CY7C1302BV25 9 Mb Burst of 2 Pipelined SRAM with QDR Architecture
Document Number: 38-05XXX
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
New Data Sheet
**
XXXXXX
XX/XX/XX
RCS
Document #: 38-05XXX Rev. **
Page 26 of 27
相关型号：
CY7C1302BV25-200BZC
QDR SRAM, 512KX18, 2.3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CYPRESS
CY7C1302DV25-100BZC
QDR SRAM, 512KX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CYPRESS
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