CY7C1305V25-100BZC_技术文档

1305V25

CY7C1305V25

CY7C1307V25

Preliminary

18 Mb Burst of 4 Pipelined SRAM with QDR Architecture

Features

Functional Description

• Separate Independent Read and Write Data Ports

The CY7C1305V25/CY7C1307V25 are 2.5V Synchronous

Pipelined SRAMs equipped with QDR architecture. QDR ar-

chitecture consists of two separate ports to access the mem-

ory array. The Read port has dedicated Data Outputs to sup-

port Read operations and the Write Port has dedicated Data

Inputs to support Write operations. QDR architecture has sep-

arate data inputs and data outputs to completely eliminate the

need to “turn-around” the data bus required with common I/O

devices. Access to each port is accomplished through a com-

mon address bus. Addresses for Read and Write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the device’s Read and Write ports are completely

independent of one another. In order to maximize data

throughput, both Read and Write ports are equipped with Dou-

ble Data Rate (DDR) interfaces. Each address location is as-

sociated with four 18-bit words (CY7C1305V25) and four

36-bit words (CY7C1307V25) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K/K and

C/C) memory bandwidth is maximized while simplifying sys-

tem design by eliminating bus “turn-arounds.”

— Supports concurrent transactions

• 167 MHz Clock for High Bandwidth

— 2.5 ns Clock-to-Valid access time

• 4-Word Burst for reducing the address bus frequency

• DoubleDataRate(DDR)interfacesonbothRead&Write

Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mis-matches

• Single multiplexed address input bus latches address

inputs for both READ and WRITE ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• 13x15 mm 1.0 mm pitch fBGA package, 165 ball

(11x15 matrix)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are con-

ducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1305V25 – 1 Mb x 18

CY7C1307V25 – 512K x 36

Logic Block Diagram (CY7C1305V25)

D

[17:0]

18

Write Write Write

Write

Reg Reg Reg Reg

Address

Register

A

Address

Register

(17:0)

A

(17:0)

18

K

CLK

Gen.

RPS

Control

Logic

C

Read Data Reg.

72

36

Vref

Reg.

18

WPS

BWS

Control

Logic

36

[0:1]

Q

[17:0]

18

Cypress Semiconductor Corporation

Document #: 38-05099 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised December 11, 2002

CY7C1305V25

CY7C1307V25

Preliminary

Logic Block Diagram (CY7C1307V25)

D

[35:0]

36

Write Write Write Write

Reg

Reg Reg Reg

Address

Register

A

Address

Register

(16:0)

A

(16:0)

17

K

CLK

Gen.

RPS

Control

Logic

C

Read Data Reg.

144

72

Vref

Reg.

36

WPS

BWS

Control

Logic

72

[0:3]

Q

[35:0]

36

[1]

Selection Guide

7C1305V25-200

7C1307V25-200

7C1305V25-167

7C1307V25-167

7C1305V25-133

7C1307V25-133

7C1305V25-100

7C1307V25-100

Maximum Operating Frequency (MHz)

Maximum Operating Current (mA)

200

500

167

450

133

350

100

230

Note:

1. Shaded areas contain advance information.

Document #: 38-05099 Rev. *A

Page 2 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Pin Configuration - CY7C1305V25 (TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

Gnd/

NC/

Gnd/

72M

A

B

C

D

E

F

NC

TDO

144M

36M

WPS

A

BWS₁

NC

K

NC

BWS₀

A

RPS

A

NC

VDDQ

NC

A

NC

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

Q9

NC

D9

D10

Q10

Q11

D12

Q13

VDDQ

D14

Q14

D15

D16

Q16

Q17

A

K

NC

Q7

VSS

VDDQ

VSS

A

NC

VSS

A

VSS

VDDQ

VSS

A

D11

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

NC

D6

Q12

D13

VREF

NC

VREF

Q4

G

H

J

K

L

NC

D3

Q15

NC

Q1

M

N

P

R

D17

NC

D0

A

C

A

TCK

A

C

A

TMS

Document #: 38-05099 Rev. *A

Page 3 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Pin Configuration - CY7C1307V25 (TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

Gnd/

NC/

NC/36

M

Gnd/

A

B

C

D

E

F

NC

Q27

D27

D28

Q29

Q30

D30

NC

288M

72M

WPS

A

BWS₂

BWS₃

A

K

BWS₁

BWS₀

A

RPS

A

144M

NC

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

Q18

Q28

D20

D29

Q21

D22

VREF

Q31

D32

Q24

Q34

D26

D35

TCK

D18

D19

Q19

Q20

D21

Q22

VDDQ

D23

Q23

D24

D25

Q25

Q26

A

K

D17

D16

Q16

Q15

D14

Q13

VDDQ

D12

Q12

D11

D10

Q10

Q9

Q17

Q7

VSS

VDDQ

VSS

A

NC

VSS

A

VSS

VDDQ

VSS

A

VSS

VDD

VSS

A

VSS

VDD

VSS

A

D15

D6

Q14

D13

VREF

Q4

G

H

J

D31

Q32

Q33

D33

D34

Q35

TDO

K

L

D3

Q11

Q1

M

N

P

R

D9

A

C

A

D0

A

C

A

TMS

Document #: 38-05099 Rev. *A

Page 4 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Pin Definitions

Name

I/O

Description

Data input signals, sampled on the rising edge of K and K clocks during valid write

D_[x:0]

WPS

Input-

Synchronous

operations.

CY7C1305V25 – D_[17:0]

CY7C1307V25 – D_[35:0]]

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When as-

serted active, a write operation is initiated. Deasserting will deselect the Write port.

Deselecting the Write port will cause D_[x:0]to be ignored.

Input-

Synchronous

Byte Write Select 0, 1, 2, and 3 - active LOW. Sampled on the rising edge of the K and

K clocks during write operations. Used to select which byte is written into the device

during the current portion of the write operations. Bytes not written remain unaltered.

CY7C1305V25 - BWS₀controls D_[8:0]and BWS₁controls D_[17:9].

CY7C1307V25 - BWS₀controls D_[8:0], BWS₁controls D_[17:9], BWS₂controls D_[26:18]

and BWS₃controls D_[35:27]

BWS₀, BWS₁,

BWS₂, BWS₃

Input-

Synchronous

All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write

Select will cause the corresponding byte of data to be ignored and not written into the

device.

Address Inputs. Sampled on the rising edge of the K clock during active read and write

operations. These address inputs are multiplexed for both Read and Write operations.

Internally, the device is organized as 1 Mb x 18 (4 arrays each of 256K x 18) for

CY7C1305V25 and 256K x 36 (4 arrays each of 128K x 36) for CY7C1307V25. There-

fore, only 18 address inputs for CY7C1305V25 and 17 address inputs for

A

Input-

Synchronous

CY7C1307V25.These inputs are ignored when the appropriate port is deselected.

Data Output signals. These pins drive out the requested data during a Read operation.

Valid data is driven out on the rising edge of both the C and C clocks during Read

operations or K and K. when in single clock mode. When the Read port is deselected,

Q_[x:0]are automatically three-stated.

Q_[x:0]

Outputs-

Synchronous

CY7C1305V25 - Q_[17:0]

CY7C1307V25 - Q_[35:0]

Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K).

When active, a Read operation is initiated. Deasserting will cause the Read port to be

deselected. When deselected, the pending access is allowed to complete and the out-

put drivers are automatically three-stated following the next rising edge of the K clock.

Each read access consists of a burst of four sequential 18-bit or 36-bit transfers.

RPS

Input-

Synchronous

Positive Output Clock, input. C is used in conjunction with C to clock out the Read data

from the device. C and C can be used together to deskew the flight times of various

devices on the board back to the controller. See application example for further details.

C

K

Input-Clock

Negative Output Clock, input. C is used in conjunction with C to clock out the Read data

from the device. C and C can be used together to deskew the flight times of various

devices on the board cack to the controller. See application example for further details.

Positive Input Clock, input. The rising edge of K is used to capture synchronous inputs

tothe device and to drive out data through Q_[x:0]when in single clock mode. All accesses

are initiated on the rising edge of K.

Negative Input Clock Input. K is used to capture synchronous inputs being presented

to the device and to drive out data through Q_[x:0]when in single clock mode.

K

Input-Clock

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the

system data bus impedance. Q_[x:0]output impedance are set to 0.2 x RQ, where RQ is

a resistor connected between ZQ and ground. Alternately, this pin can be connected

directly to V_DD, which enables the minimum impedance mode. This pin cannot be con-

nected directly to GND or left unconnected.

ZQ

Document #: 38-05099 Rev. *A

Page 5 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Pin Definitions

TDO

TCK

TDI

Output

Input

TDO for JTAG.

TCK pin for JTAG.

TDI pin for JTAG.

TMS pin for JTAG.

TMS

Address expansion for 36M. This is not connected to the die. Can be connected to any

voltage level on CY7C1305V25/CY7C1307V25.

NC/36M

Input

GND/72M

Address expansion for 72M. This should be tied low on the CY7C1305V25

Address expansion for 72M. This can be connected to any voltage level on

CY7C1307V25

NC/72M

Input

Address expansion for 144M. This should be tied low on

CY7C1305V25/CY7C1307V25.

GND/144M

GND/288M

Input

Address expansion for 144M. This should be tied low on CY7C1307V25.

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs

and Outputs as well as A/C measurement points.

V_REF

Power supply inputs to the core of the device. Should be connected to 2.5V power

V_DD

V_SS

Power Supply supply.

Ground Ground for the device. Should be connected to ground of the system.

Power supply inputs for the outputs of the device. Should be connected to 1.5V power

Power Supply supply.

NC No connect

V_DDQ

NC

18-bit data words. Read operations are initiated by asserting

RPS active at the rising edge of the positive input clock (K).

The address presented to Address inputs are stored in the

Read address register. Following the next K clock rise the cor-

responding lowest order 18-bit word of data is driven onto the

Q_[17:0]using C as the output timing reference. On the subse-

quent rising edge of C the next 18-bit data word is driven onto

the Q_[17:0]. This process continues until all four 18-bit data

words have been driven out onto Q_[17:0]. The requested data

will be valid 2.5ns from the rising edge of the output clock

(C or C, 167 MHz device). In order to maintain the internal

logic, each read access must be allowed to complete. Each

Read access consists of four 18-bit data words and takes 2

clock cycles to complete. Therefore, Read accesses to the

device can not be initiated on two consecutive K clock rises.

The internal logic of the device will ignore the second Read

request. Read accesses can be initiated on every other K

clock rise. Doing so will pipeline the data flow such that data

is transferred out of the device on every rising edge of the

output clocks (C and C, or K and K when in single clock mode).

Introduction

Functional Overview

The CY7C1305V25/CY7C1307V25 are synchronous pipe-

lined Burst SRAMs equipped with both a Read Port and a

Write Port. The Read port is dedicated to Read operations and

the Write Port is dedicated to Write operations. Data flows into

the SRAM through the Write port and out through the Read

Port. These devices multiplex the address inputs in order to

minimize the number of address pins required. By having sep-

arate Read and Write ports, the device completely eliminates

the need to “turn-around” the data bus and avoids any possible

data contention, thereby simplifying system design. Each ac-

cess consists of four 18/36-bit data transfers in two clock cy-

cles.

Accesses for both ports are initiated on the positive input clock

(K). All synchronous input timing is referenced from the rising

edge of the input clocks (K and K) and all output timing is

referenced to the output clocks (C and C, or K and K when in

single clock mode).

When the read port is deselected, the CY7C1305V25 will first

complete the pending read transactions. Synchronous internal

circuitry will automatically three-state the outputs following the

next rising edge of the negative output clock (C). This will allow

for a seamless transition between devices without the inser-

tion of wait states in a depth expanded memory.

All synchronous data inputs (D_[x:0]) inputs pass through input

registers controlled by the input clocks (K and K). All synchro-

nous data outputs (Q_[x:0]) outputs pass through output regis-

ters controlled by the rising edge of the output clocks (C and

C or K and K when in single clock mode).

All synchronous control (RPS, WPS, BWS_[0:x]) inputs pass

through input registers. RPS and WPS are controlled by the

rising edge of the input clock (K). BWS_[0:x]are controlled by

the rising edges of input clocks (K and K).

Write Operations

Write operations are initiated by asserting WPS active at the

rising edge of the positive input clock (K). On the following K

clock rise the data presented to D_[17:0]is latched and stored

into the lower 18-bit Write Data register provided BWS_[1:0]are

both asserted active. On the subsequent rising edge of the

negative input clock (K) the information presented to D_[17:0]is

also stored into the Write Data Register provided BWS_[1:0]are

both asserted active. This process continues for one more cy-

cle until four 18-bit words (a total of 72 bits) of data are stored

in the SRAM. The 72 bits of data are then written into the mem-

The following descriptions take CY7C1305V25 as an exam-

ple. However, the same is true for the other QDR SRAM,

CY7C1307V25.

Read Operations

The CY7C1305V25 is organized internally as a 256Kx72

SRAM. Accesses are completed in a burst of four sequential

Document #: 38-05099 Rev. *A

Page 6 of 28

CY7C1305V25

CY7C1307V25

Preliminary

ory array at the specified location. Therefore, Write accesses

to the device can not be initiated on two consecutive K clock

rises. The internal logic of the device will ignore the second

Write request. Write accesses can be initiated on every other

rising edge of the positive clock (K). Doing so will pipeline the

data flow such that 18-bits of data can be transferred into the

device on every rising edge of the input clocks (K and K).

other port. If the ports access the same location at the same

time, the SRAM will deliver the most recent information asso-

ciated with the specified address location. This includes for-

warding data from a Write cycle that was initiated on the pre-

vious K clock rise.

Read accesses and Write access must be schedule such that

one transaction is initiated on any clock cycle. If both ports are

selected on the same K clock rise, the arbitration depends on

the previous state of the SRAM. If both ports were deselected,

the Read port will take priority. If a Read was initiated on the

previous cycle, the Write port will assume priority (since Read

operations can not be initiated on consecutive cycles). If a

Write was initiated on the previous cycle, the Read port will

assume priority (since Write operations can not be initiated on

consecutive cycles). Therefore, asserting both port selects ac-

tive from a deselected state will result in alternating

Read/Write operations being initiated, with the first access be-

ing a Read.

When deselected, the write port will ignore all inputs after the

pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1305V25. A

write operation is initiated as described in the Write Operation

section above. The bytes that are written are determined by

BWS₀and BWS₁which are sampled with each set of 18-bit

data word. Asserting the appropriate Byte Write Select input

during the data portion of a write will allow the data being pre-

sented to be latched and written into the device. De-asserting

the Byte Write Select input during the data portion of a write

will allow the data stored in the device for that byte to remain

unaltered. This feature can be used to simplify READ/MODI-

FY/WRITE operations to a Byte Write operation.

Depth Expansion

The CY7C1305V25 has a Port Select input for each port. This

allows for easy depth expansion. Both Port Selects are sam-

pled on the rising edge of the positive input clock only (K).

Each port select input can deselect the specified port. Dese-

lecting a port will not affect the other port. All pending transac-

tions (Read and Write) will be completed prior to the device

being deselected.

Single Clock Mode

The CY7C1305V25 can be used with a single clock that con-

trols both the input and output registers. In this mode the de-

vice will recognize only a single pair of input clocks (K and K)

that control both the input and output registers. This operation

is identical to the operation if the device had zero skew be-

tween the K/K and C/C clocks. All timing parameters remain

the same in this mode. To use this mode of operation, the user

must tie C and C HIGH at power-on. This function is a strap

option and not alterable during device operation.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ

pin on the SRAM and V_SSto allow the SRAM to adjust its

output driver impedance. The value of RQ must be 5X the

value of the intended line impedance driven by the SRAM, The

allowable range of RQ to guarantee impedance matching with

a tolerance of ±10% is between 175Ohms and 350Ohms, with

V_DDQ=1.5V. The output impedance is adjusted every 1024 cy-

cles to adjust for drifts in supply voltage and temperature.

Concurrent Transactions

The Read and Write ports on the CY7C1305V25 operate com-

pletely independently of one another. Since each port latches

the address inputs on different clock edges, the user can Read

or Write to any location, regardless of the transaction on the

Document #: 38-05099 Rev. *A

Page 7 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Application Example

CY7C1305V25 in an Application

V_T=V_DDQ/2

SRAM #1

SRAM #4

Q

D

Q

D

18

R=50Ω

Memory

18

Controller

72

Q

18

Din

Add.

Cntr.

72

2

CLK/CLK (input)

CLK/CLK (output)

R=50Ω

V_T=V_DDQ/2

Note:

2. The above concept applies similarly to the CY7C1307V25.

Document #: 38-05099 Rev. *A

Page 8 of 28

CY7C1305V25

CY7C1307V25

Preliminary

[3,4,5,6,7,8,9]

Truth Table

Operation

K

RPS

WPS

DQ

Write Cycle:

L-H

H^[8]

L^[9]

D(A+00)at

K(t+1) ¦

D(A+01) at

K(t+1) ¦

D(A+10) at

K(t+2) ¦

D(A+11) at

K(t+2) ¦

Loadaddress,inputwrite

data on 2 consecutive K

and K rising edges.

Read Cycle:

L-H

L^[9]

X

Q(A+00) at

C(t+1) ¦

Q(A+01) at

C(t+1) ¦

Q(A+10) at

C(t+2) ¦

Q(A+11) at

C(t+2) ¦

Load address, read data

on 2 consecutive C and

C rising edges.

NOP: No operation

L-H

H

X

H

X

High-Z

High-Z)

High-Z

Standby: Clock stopped

Stopped

Notes:

3. X=Don’t Care, H=Logic HIGH, L=Logic LOW ¦represents rising edge.

4. Device will power-up deselected and the outputs in a three-state condition.

5. A represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the addresses

sequence in the burst.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line

charging symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a don’t care for this operation.FM

9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The

device will ignore the second Read request.

Document #: 38-05099 Rev. *A

Page 9 of 28

CY7C1305V25

CY7C1307V25

Preliminary

[10]

Write Cycle Descriptions (CY7C1305V25)

BWS₀

BWS₁

K

Comments

L

L-H

-

During the Data portion of a Write sequence, both bytes (D_[17:0]) are written into the

device.

L

H

L

-

L-H

-

During the Data portion of a Write sequence, both bytes (D_[17:0]) are written into the

device.

L-H

During the Data portion of a Write sequence, only the lower byte (D_[8:0]) is written into

the device. D_[17:9]will remain unaltered.

L

-

L-H

-

During the Data portion of a Write sequence, only the lower byte (D_[8:0]) is written into

the device. D_[17:9]will remain unaltered.

H

L-H

-

During the Data portion of a Write sequence, only the upper byte (D_[17:9]) is written into

the device. D_[8:0]will remain unaltered.

L

L-H

During the Data portion of a Write sequence, only the upper byte (D_[17:9]) is written into

the device. D_[8:0]will remain unaltered.

H

L-H

-

No data is written into the device during this portion of a write operation.

H

L-H

Note:

10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS₀and BWS₁(CY7C1305V25) and BWS₂and BWS₃

(CY7C1307V25) can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.

Document #: 38-05099 Rev. *A

Page 10 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Write Cycle Descriptions (CY7C1307V25)^[10]

BWS₀

BWS₁

BWS₂

BWS₃

K

Comments

L

L-H

-

During the Data portion of a Write se-

quence, all the four bytes (D_[35:0]) are writ-

ten into the device.

L

L-H

-

During the Data portion of a Write se-

quence, all the four bytes (D_[35:0]) are writ-

ten into the device.

H

L-H

During the Data portion of a Write se-

quence, only the lower byte (D_[8:0]) is writ-

ten into the device. D_[35:9]will remain un-

altered.

L

H

L

H

L

H

L

-

L-H

-

During the Data portion of a Write se-

quence, only the lower byte (D_[8:0]) is writ-

ten into the device. D_[17:9]will remain un-

altered.

H

L-H

During the Data portion of a Write se-

quence, only the byte (D_[17:9]) is written

into the device. D_[8:0]and D_[35:18]will re-

main unaltered.

L

-

L-H

-

During the Data portion of a Write se-

quence, only the byte (D_[17:9]) is written

into the device. D_[8:0]and D_[35:18]will re-

main unaltered.

H

L-H

During the Data portion of a Write se-

quence, only the byte (D_[26:18]) is written

into the device. D_[17:0]and D_[35:27]will re-

main unaltered.

L

-

L-H

During the Data portion of a Write se-

quence, only the byte (D_[26:18]) is written

into the device. D_[17:0]and D_[35:27]will re-

main unaltered.

H

L-H

-

During the Data portion of a Write se-

quence, only the byte (D_[35:27]) is written

into the device. D_[26:0]will remain unal-

tered.

L

L-H

During the Data portion of a Write se-

quence, only the byte (D_[35:27]) is written

into the device. D_[26:0]will remain unal-

tered.

H

L-H

-

No data is written into the device during

this portion of a write operation.

L-H

No data is written into the device during

this portion of a write operation.

Document #: 38-05099 Rev. *A

Page 11 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Current into Outputs (LOW).........................................20 mA

Maximum Ratings

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-Up Current .................................................... >200 mA

Storage Temperature

–65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Operating Range

Ambient

Supply Voltage on V_DDRelative to GND........–0.5V to +3.6V

Range Temperature^[12]

V_DD

V_DDQ

DC Voltage Applied to Outputs

in High Z State^[11]................................–0.5V to V_DDQ+ 0.5V

Com’l

0°C to +70°C

2.5 ±100 mV

1.4V to 1.9V

DC Input Voltage^[11].............................–0.5V to V_DDQ+ 0.5V

hh

Electrical Characteristics Over the Operating Range^[1,13]

Parameter

V_DD

V_DDQ

V_OH

V_OL

Description

Test Conditions

Min.

Max.

2.6

Unit

V

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage^[11]

Input Load Current

2.4

1.4

1.9

V

I_OH= -2.0 mA, nominal impedance

I_OL= 2.0 mA, nominal impedance

V_DDQ/2+0.3

V_DDQ

V_DDQ/2–0.3

V_DDQ+0.3

V_REF–0.1

5

V

V_SS

V_REF+0.1

–0.3

V

V_IH

V

V_IL

V

I_X

GND < V_I< V_DDQ

-5

mA

I_OZ

Output Leakage

Current

GND < V_I< V_DDQ,Output Disabled

-5

5

V_REF

I_DD

Input Reference

Voltage

Typical value = 0.75V

0.68

0.95

V

V_DDOperating Supply V_DD= Max.,

I_OUT= 0 mA,

5.0 ns cycle, 200 MHz

6.0 ns cycle, 167MHz

7.5 ns cycle, 133 MHz

10 ns cycle, 100 MHz

5.0 ns cycle, 200 MHz

6.0 ns cycle, 167MHz

7.5 ns cycle, 133 MHz

10 ns cycle, 100 MHz

500

450

350

230

125

100

80

mA

f = f_MAX= 1/t_CYC

I_SB1

Automatic

Power-Down

Current

Max. V_DD, Both

Ports Deselected,

V_INŠ V_IHor

V_IN< V_IL

f = f_MAX= 1/t_CYC,

Inputs Static

60

AC Input Requirements Over the Operating Range

Test Conditions

Parameter

Description

Min.

V_REF+ 0.2

Typ.

Max.

V_IH

Input High (Logic 1)

Voltage

–

V_IL

Input Low (Logic 0)

Voltage

–

V_REF- 0.2

Notes:

11. Minimum voltage equals -2.0V for pulse duration less than 20 ns.

12. T_Ais the case temperature.

13. All voltages referenced to ground.

Document #: 38-05099 Rev. *A

Page 12 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Switching Characteristics Over the Operating Range ^[1,14,15,16]

-200

-167

-133

-100

Cypress

Consortium

Parameter Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Unit

[17]

t_Power

V_CC(typical) to the first access

read or write

10

us

Cycle Time

t_CYC

t_KH

t_KHKH

t_KHKL

K Clock and C Clock Cycle Time

Input Clock (K/K and C/C) HIGH

5.0

2.0

6.0

2.4

7.5

3.2

10.0

3.5

ns

t_KL

t_KLKH

t_KHKH

Input Clock (K/K and C/C) LOW

2.0

2.4

2.7

3.2

3.4

3.5

4.4

ns

t_KHKH

K/K Clock rise to K/K Clock rise

and C/C to C/C rise

(rising edge to rising edge)

2.6

1.5

3.3

2.0

4.1

2.5

5.4

3.0

t_KHCH

K/K Clock rise to C/C clock rise

(rising edge to rising edge)

0.0

ns

Set-up Times

t_SA

t_SC

t_SD

t_SA

t_SC

t_SD

Address set-up to clock (K and K)

rise

0.6

0.7

0.8

1.0

ns

Control set-up to clock (K and K)

rise (RPS, WPS, BWS₀, BWS₁)

D_[17:0]set-up to clock (K and K)

rise

Hold Times

t_HA

t_HC

Address Hold after clock (K and

K) rise

0.6

0.7

0.8

1.0

ns

t_HC

Controlsignals Hold afterclock (K 0.6

and K) rise (RPS, WPS, BWS₀,

BWS₁)

t_HD

D_[17:0]Hold after clock (K and K)

rise

0.6

0.7

0.8

1.0

ns

Output Times

t_CO

t_CHQV

C/C Clock rise (or K/K in single

clock mode) to Data Valid^[15]

2.3

2.5

3.0

ns

t_DOH

t_CHZ

t_CHQX

t_CHZ

t_CLZ

Data Output Hold After Output

C/C clock Rise (Active to Active)

0.8

1.2

Clock (C and C) rise to High-Z

(Active to High-Z)^{[15, 16]}

t_CLZ

Clock (C and C) rise to Low-Z^[15,

16]

Notes:

14. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250 Ohms, V_DDQ= 1.5V,

input pulse levels of 0.25V to 1.25V, and output loading of the specified I_OL/I_OHand load capacitance shown in (a) of AC test loads.

15. t_CHZ, t_CLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

16. At any given voltage and temperature t_CHZis less than t_CLZand, t_CHZless than t_CO

.

17. This part has a voltage regulator that steps down the voltage internally; t_Poweris the time power needs to be supplied above V_DDminimum initially before a

read or write operation can be initiated.

Document #: 38-05099 Rev. *A

Page 13 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Capacitance^[18]

Parameter

C_IN

Description

Test Conditions

Max.

Unit

pF

Input Capacitance

T_A= 25×C, f = 1 MHz,

V_DD= 2.5V.

V_DDQ= 1.5V

3

C_CLK

Clock Input Capacitance

Output Capacitance

pF

C_O

pF

Note:

18. Tested initially and after any design or process change that may affect these parameters.

/2

V

DDQ

V

/2

DDQ

V

REF

V

/2

REF

R=50Ω

DDQ

OUTPUT

[14]

ALL INPUT PULSES

1.25V

Z =50Ω

0

OUTPUT

Device

Under

Test

R =50Ω

L

0.75V

0.25V

5 pF

Under

V

=0.75V

REF

ZQ

(a)

Test

RQ=

250Ω

RQ=

250Ω

1304V25-2

1304V25-3

INCLUDING

JIG AND

SCOPE

(b)

Document #: 38-05099 Rev. *A

Page 14 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Switching Waveforms

Read/Deselect Sequence ^[19]

t_CYC

t_KHKH

t_KL

t_KHKH

K

t_KH

t_KL

K

t_KH

t_SA

t_HA

A_(x:0)

A

B

t_SC

t_HC

Deselect

RPS

t_CLZ

Q(A+1)

Q(A+3)

Q(B+1)

Q(B+2) Q(B+3)

Q(A)

Q(A+2)

Q(B)

Data Out

t_CO

t_KHCH

t_CHZ

C

t_DOH

t_CO

t_DOH

= UNDEFINED

= DON’T CARE

Note:

19. Device originally deselected.

Document #: 38-05099 Rev. *A

Page 15 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Switching Waveforms

Write/Deselect Sequence ^[20,21]

t_CYC

t_KL

K

t_KH

t_KL

K

t_SA

t_HA

A

B

t_H

t_SC

t_HC

WPS

t_HC

t_SC

BWS_x

D(A+3)

D(B)

D(B+1)

D(B+2)

D(B+3)

D(A)

D(A+2)

D(A+1)

Data In

t_HD

t_SD

= UNDEFINED

= DON’T CARE

Notes:

20. C and C reference to Data Outputs and do not affect Writes.

21. Activity on the BWS_xLOW = Valid, Byte writes allowed, see Byte write table for details.

Document #: 38-05099 Rev. *A

Page 16 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Switching Waveforms

Read/Write/Deselect Sequence^[22,23]

K

A

B

C

D

WPS

RPS

D_[x:0]

D(B+1)

Q(A+2)

D(B+2)

Q(A+3)

D(B+3)

Q(C)

D(B)

D(D)

D(D+1)

Q(C+2)

D(D+2)

Q(C+3)

D(D+3)

Q(A+1)

Q(A)

Q(GQ+(C1)+1)

Q_[x:0]

C

= UNDEFINED

= DON’T CARE

Notes:

22. Read Port previously deselected.

23. BWS_[1:0]both assumed active.

Document #: 38-05099 Rev. *A

Page 17 of 28

CY7C1305V25

CY7C1307V25

Preliminary

TDI and TDO pins as shown in TAP Controller Block Diagram.

Upon power-up, the instruction register is loaded with the

IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access

port (TAP) in the FBGA package. This part is fully compliant

with IEEE Standard #1149.1-1900. The TAP operates using

JEDEC standard 1.8V I/O logic levels.

When the TAP controller is in the Capture IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board level serial test path.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V_SS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V_DDthrough a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the operation of the

device.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

register is a single-bit register that can be placed between TDI

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(V_SS) when the BYPASS instruction is executed.

Test Access Port–Test Clock

Boundary Scan Register

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

The boundary scan register is connected to all of the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices.

Test Mode Select

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) on any register.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see Instruction codes). The

output changes on the falling edge of TCK. TDO is connected

to the least significant bit (LSB) of any register.

TAP Instruction Set

Performing a TAP Reset

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

A Reset is performed by forcing TMS HIGH (VDD) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a high-Z state.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

Instruction Register

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the

Document #: 38-05099 Rev. *A

Page 18 of 28

CY7C1305V25

CY7C1307V25

Preliminary

is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required - that is, while data

captured is shifted out, the preloaded data can be shifted in.

SAMPLE Z

BYPASS

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a High-Z state until the next command is

given during the “Update IR” state.

When the BYPASS instruction is loaded in the instruction

register and the TAP is placed in a Shift-DR state, the bypass

register is placed between the TDI and TDO pins. The

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

SAMPLE/PRELOAD

SAMPLE / PRELOAD is a 1149.1 mandatory instruction.

When the SAMPLE / PRELOAD instructions are loaded into

the instruction register and the TAP controller is in the Cap-

ture-DR state, a snapshot of data on the inputs and output pins

is captured in the boundary scan register.

EXTEST

The EXTEST instruction enables the preloaded data to be

driven out through the system output pins. This instruction also

selects the boundary scan register to be connected for serial

access between the TDI and TDO in the shift-DR controller

state.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possi-

ble that during the Capture-DR state, an input or output will

undergo a transition. The TAP may then try to capture a signal

while in transition (metastable state). This will not harm the

device, but there is no guarantee as to the value that will be

captured. Repeatable results may not be possible.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be

able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #47.

When this scan cell, called the "extest output bus tristate", is

latched into the preload register during the "Update-DR" state

in the TAP controller, it will directly control the state of the

output (Q-bus) pins, when the EXTEST is entered as the

current instruction. When HIGH, it will enable the output

buffers to drive the output bus. When LOW, this bit will place

the output bus into a High-Z condition.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (t_CSand t_CH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE / PRELOAD instruction. If

this is an issue, it is still possible to capture all other signals

and simply ignore the value of the CK and CK# captured in the

boundary scan register.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that

cell, duringthe"Shift-DR"state. During"Update-DR", thevalue

loaded into that shift-register cell will latch into the preload

register. When the EXTEST instruction is entered, this bit will

directly control the output Q-bus pins. Note that this bit is

pre-set LOW to enable the output when the device is

powered-up, and also when the TAP controller is in the

"Test-Logic-Reset" state.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the bound-

ary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells pri-

or to the selection of another boundary scan test operation.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document #: 38-05099 Rev. *A

Page 19 of 28

CY7C1305V25

CY7C1307V25

Preliminary

[24]

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

1

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

CAPTURE-IR

0

SHIFT-DR

0

SHIFT-IR

0

1

EXIT1-DR

0

1

EXIT1-IR

0

1

0

PAUSE-DR

1

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-DR

UPDATE-IR

1

0

Note:

24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 38-05099 Rev. *A

Page 20 of 28

CY7C1305V25

CY7C1307V25

Preliminary

TAP Controller Block Diagram

0

Bypass Register

Selection

TDI

Selection

TDO

Circuitry

2

1

0

Circuitry

Instruction Register

29

31 30

.

2

1

Identification Register

.

106 .

.

2

1

Boundary Scan Register

TCK

TMS

TAP Controller

TAP Electrical Characteristics Over the Operating Range^{[13, 25, 26]}

Parameter

V_OH1

V_OH2

V_OL1

V_OL2

V_IH

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Test Conditions

I_OH= −2.0 mA

Min.

1.7

Max.

Unit

V

I_OH= −100 µA

I_OL= 2.0 mA

I_OL= 100 µA

2.1

V

0.7

0.2

V

1.7

–0.3

−5

V_DD+0.3

0.7

V

V_IL

Input LOW Voltage

V

I_X

Input and Output Load Current

GND ≤ V_I≤ V_DDQ

5

µA

Notes:

25. Overshoot: V_IH(AC)<V_DD+0.5V for t<t_TCYC/2. Undershoot V_IL(AC)<0.5V for t<t_TCYC/2. Power-up: V_IH<2.6V and V_DD<2.4V and V_DDQ<1.4V for t<200 ms.

26. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

Document #: 38-05099 Rev. *A

Page 21 of 28

CY7C1305V25

CY7C1307V25

Preliminary

TAP AC Switching Characteristics Over the Operating Range ^[27,28]

Parameter

t_TCYC

Description

Min.

Max.

Unit

ns

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH

100

t_TF

10

MHz

ns

t_TH

40

t_TL

TCK Clock LOW

ns

Set-up Times

t_TMSS

TMS set-up to TCK clock rise

TDI set-up to TCK clock rise

Capture set-up to TCK rise

10

ns

t_TDIS

t_CS

Hold Times

t_TMSH

TMS Hold after TCK clock rise

TDI Hold after clock rise

10

ns

t_TDIH

t_CH

Capture Hold after clock rise

Output Times

t_TDOV

TCK Clock LOW to TDO valid

20

ns

t_TDOX

TCK Clock LOW to TDO invalid

0

Notes:

27. Parameters t_CSand t_CHrefer to the set-up and hold time requirements of latching data from the boundary scan register.

28. Test conditions are specified using the load in TAP AC test conditions. t_R/t_F= 1 ns.

Document #: 38-05099 Rev. *A

Page 22 of 28

CY7C1305V25

CY7C1307V25

Preliminary

TAP Timing and Test Conditions^[28]

1.25V

50Ω

ALL INPUT PULSES

TDO

2.5V

Z =50Ω

0

1.25V

C =20 pF

L

0V

GND

(a)

t_TL

t_TH

Test Clock

TCK

t_TCYC

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOX

t_TDOV

Document #: 38-05099 Rev. *A

Page 23 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Identification Register Definitions

Value

Instruction Field

Revision Number

(31:29)

CY7C1305V25

000

CY7C1307V25

000

Description

Version number.

Cypress Device ID

(28:12)

Defines the type of SRAM.

01011010011010101

01011010011100101

Cypress JEDEC ID

(11:1)

Allows unique identification of

SRAM vendor.

00000110100

1

ID Register Presence

(0)

Indicate the presence of an ID

register.

Scan Register sizes

Register Name

Instruction

Bit Size

3

Bypass

1

ID

32

107

Boundary Scan

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the Input/Output ring contents.

IDCODE

Loads the ID register with the vendor ID code and plac-

es the register between TDI and TDO. This operation

does not affect SRAM operation.

001

SAMPLE Z

Captures the Input/Output contents. Places the bound-

ary scan register between TDI and TDO. Forces all

SRAM output drivers to a High-Z state.

010

011

RESERVED

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures the Input/Output ring contents. Places the

boundary scan register between TDI and TDO. Does

not affect the SRAM operation.

100

101

110

RESERVED

BYPASS

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This

operation does not affect SRAM operation.

111

Boundary Scan Order

Bit #

Bump ID

Bit #

Bump ID

7R

0

1

2

3

4

6R

6P

6N

7P

7N

5

6

7

8

9

8R

8P

9R

11P

Document #: 38-05099 Rev. *A

Page 24 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Boundary Scan Order

Bit #

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

Bump ID

10P

10N

9P

Bit #

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

Bump ID

11A

Internally Pre-set LOW

9A

10M

11N

9M

8B

7C

6C

9N

8A

11L

11M

9L

7A

7B

6B

10L

11K

10K

9J

6A

5B

5A

4A

9K

5C

10J

11J

11H

10G

9G

4B

3A

Internally Pre-set LOW

1A

2B

3B

1C

1B

3D

3C

1D

2C

3E

2D

2E

1E

2F

3F

1G

1F

3G

11F

11G

9F

10F

11E

10E

10D

9E

10C

11D

9C

9D

11B

11C

9B

10B

Document #: 38-05099 Rev. *A

Page 25 of 28

CY7C1305V25

CY7C1307V25

Preliminary

Boundary Scan Order

Bit #

82

83

84

85

86

87

88

89

90

91

92

93

94

95

Bump ID

2G

1J

Bit #

96

Bump ID

2M

3P

97

2J

98

2N

3K

99

2P

3J

100

101

102

103

104

105

106

1P

2K

3R

1K

4R

2L

4P

3L

5P

1M

1L

5N

5R

3N

3M

1N

Ordering Information

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

Package Type

200

CY7C1305V25-200BZC

CY7C1307V25-200BZC

CY7C1305V25-167BZC

CY7C1307V25-167BZC

CY7C1305V25-133BZC

CY7C1307V25-133BZC

CY7C1305V25-1300BZC

CY7C1307V25-100BZC

BB165D

13 x 15 mm FBGA

Commercial

167

133

100

13 x 15 mm FBGA

Document #: 38-05099 Rev. *A

Page 26 of 28

CY7C1305V25

CY7C1307V25

Preliminary

165-ball FBGA (13 x 15 x 1.4 mm) BB165D

51-85180 **

Document #: 38-05099 Rev. *A

Page 27 of 28

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1305V25

CY7C1307V25

Preliminary

Document Title: CY7C1305V25 / CY7C1307V25 18Mb Burst of 4 Pipelined SRAM with QDR Architecture

Document Number: 38-05099

Issue

Orig. of

Change

REV.

**

*A

ECN NO. Date

Description of Change

107654

122949

07/10/01

03/14/03

SKX

RCS

New Data Sheet

1. Changed Status to Preliminary from Advanced Information (All Pages)

2. Added Ex-Test feature to JTAG. This implementation is backwards com-

patible with the previous Non-Ex-Test feature set. (Page 19 and 24)

3. Changed Boundary Scan Order to 106 Cells from 69 (Page 24, 25 and

26)

4. Changed Cells 47 and 63 to an Internal Cells that are Pre-Set to LOW

in the Boundary Scan Order. Note that these pins are 100% compatible

with theprevious scanorder becausethey had previosly been connected

to V_SS. (Page 25)

5. Specified minimum and maximum input voltages for AC conditions.

(Page 12)

6. Changed packaged height to 1.4 mm from 1.2 mm. (Page 27)

7. Changed ball diameter to 0.5 mm from 0.45 mm. (Page 27)

8. Added t_Powerspecification and note 17. These devices require 10 us of

of V_DDabove V_DDminimum (2.4V) before operating. (page 13)

Document #: 38-05099 Rev. *A

Page 28 of 28


型号：	CY7C1305V25-100BZC
厂家：	CYPRESS
描述：	QDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165 时钟静态存储器内存集成电路
文件：	总28页 (文件大小：229K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1305V25-100BZC [CYPRESS]

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