CY7C1305V25-167BZC [CYPRESS]
QDR SRAM, 1MX18, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165;型号: | CY7C1305V25-167BZC |
厂家: | CYPRESS |
描述: | QDR SRAM, 1MX18, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165 时钟 静态存储器 内存集成电路 |
文件: | 总23页 (文件大小:608K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1305V25
CY7C1307V25
PRELIMINARY
18-Mb Burst of 4 Pipelined SRAM with QDR™ Architecture
Features
Functional Description
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 4-Word Burst for reducing the address bus frequency
The CY7C1305V25/CY7C1307V25 are 2.5V Synchronous
Pipelined SRAMs equipped with QDR architecture. QDR
architecture consists of two separate ports to access the
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has dedicated
Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn-around” the data bus required with common
I/O devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the device’s Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 18-bit words (CY7C1305V25) and four
36-bit words (CY7C1307V25) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K and
C/C) memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds.”
• DoubleDataRate(DDR)interfacesonbothRead&Write
Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.2 mm 1.0-mm pitch fBGA package, 165 ball
Depth expansion is accomplished with Port Selects for each
(11x15 matrix)
port. Port selects allow each port to operate independently.
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1305V25 – 1 Mb x 18
CY7C1307V25 – 512K x 36
Logic Block Diagram (CY7C1305V25)
D
[17:0]
18
Write Write Write Write
Reg
Reg Reg
Reg
Address
Register
A
Address
Register
[17:0]
A
(17:0)
18
18
K
CLK
Gen.
K
RPS
Control
Logic
C
C
Read Data Reg.
72
36
Vref
Reg.
Reg.
Reg.
18
WPS
BWS
Control
Logic
36
[0:1]
Q
[17:0]
18
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05099 Rev. *B
Revised February 2, 2004
CY7C1305V25
CY7C1307V25
PRELIMINARY
Logic Block Diagram (CY7C1307V25)
D
[35:0]
36
Write Write Write Write
Reg
Reg Reg
Reg
Address
Register
A
Address
Register
(16:0)
A
(16:0)
17
17
K
CLK
Gen.
K
RPS
Control
Logic
C
C
Read Data Reg.
144
72
Vref
Reg.
Reg.
Reg.
36
WPS
BWS
Control
Logic
72
[0:3]
Q
[35:0]
36
Selection Guide
7C1305V25-167
7C1307V25-167
7C1305V25-133
7C1307V25-133
7C1305V25-100
7C1307V25-100
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
167
550
133
470
100
420
Document #: 38-05099 Rev. *B
Page 2 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Pin Configuration - CY7C1305V25 (Top View)
1
2
3
4
5
6
7
8
9
10
11
Gnd/
Gnd/
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
144M NC/ 36M WPS
BWS1
NC
A
K
K
NC
BWS0
A
RPS
A
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
72M
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Q9
NC
D11
NC
Q12
D13
VREF
NC
NC
Q15
NC
D17
NC
TCK
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
A
VSS
VSS
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
A
A
C
C
A
A
A
Pin Configuration - CY7C1307V25 (Top View)
1
2
3
4
5
6
7
8
9
10
11
Gnd/
NC/
Gnd/
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
Q27
D27
D28
Q29
Q30
D30
NC
D31
Q32
Q33
D33
D34
Q35
TDO
288M NC/ 72M WPS
BWS2
BWS3
A
K
K
BWS1
BWS0
A
RPS
A
36M
144M
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
A
VSS
VSS
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
A
A
C
C
A
A
A
A
TMS
Document #: 38-05099 Rev. *B
Page 3 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Pin Definitions
Name
I/O
Description
D[x:0]
Input-
Data input signals, sampled on the rising edge of K and K clocks during valid
Synchronous
write operations.
CY7C1305V25 – D[17:0]
CY7C1307V25 – D[35:0]
WPS
Input-
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[x:0] to be ignored.
Synchronous
BWS0, BWS1,
BWS2, BWS3
Input-
Byte Write Select 0, 1, 2, and 3 - active LOW. Sampled on the rising edge of the K
and K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations. Bytes not written remain unaltered.
CY7C1305V25 - BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1307V25 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18]
and BWS3 controls D[35:27]
Synchronous
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a
Byte Write Select will cause the corresponding byte of data to be ignored and not written
into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active Read and
Write operations. These address inputs are multiplexed for both Read and Write oper-
ations. Internally, the device is organized as 1M x 18 (4 arrays each of 256K x 18) for
CY7C1305V25 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1307V25. There-
fore, only 18 address inputs for CY7C1305V25 and 17 address inputs for
Synchronous
CY7C1307V25. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
RPS
Outputs-
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Synchronous
Q
[x:0] are automatically three-stated.
CY7C1305V25 - Q[17:0]
CY7C1307V25 - Q[35:0]
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the out-
put drivers are automatically three-stated following the next rising edge of the C clock.
Each read access consists of a burst of four sequential 18-bit or 36-bit transfers.
Input-
Synchronous
C
C
K
Input-Clock
Input-Clock
Input-Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
Negative Output Clock Input. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board cack to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[x:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
K
Input-Clock
Input
Negative Input Clock Input. K is used to capture synchronous inputs to the device and
to drive out data through Q[x:0] when in single clock mode.
ZQ
Output Impedance Matching Input. This input is used to tune the device outputs to
the system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where
RQ is a resistor connected between ZQ and ground. Alternately, this pin can be con-
nected directly to VDD, which enables the minimum impedance mode. This pin cannot
be connected directly to GND or left unconnected.
TDO
TCK
TDI
TMS
NC/36M
Output
Input
Input
Input
N/A
TDO pin for JTAG
TCK pin for JTAG
TDI pin for JTAG
TMS pin for JTAG
Address expansion for 36M. This is not connected to the die. Can be connected to
any voltage level on CY7C1305V25/CY7C1307V25.
Document #: 38-05099 Rev. *B
Page 4 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Pin Definitions (continued)
Name
GND/72M
I/O
Input
Description
Address expansion for 72M. This should be tied LOW on the CY7C1305V25.
NC/72M
N/A
Address expansion for 72M. This can be connected to any voltage level on
CY7C1307V25.
GND/144M
Input
Input
Address expansion for 144M. This should be tied LOW on
CY7C1305V25/CY7C1307V25.
GND/288M
VREF
Address expansion for 144M. This should be tied LOW on CY7C1307V25.
Input-
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
Reference
and Outputs as well as AC measurement points.
VDD
VSS
VDDQ
NC
Power Supply Power supply inputs to the core of the device
Ground Ground for the device
Power Supply Power supply inputs for the outputs of the device
N/A Not connected to the die. Can be tied to any voltage level.
onto the Q[17:0]. This process continues until all four 18-bit data
Introduction
Functional Overview
words have been driven out onto Q[17:0]. The requested data
will be valid 2.5 ns from the rising edge of the output clock
(C and C, or K and K when in single clock mode, 167-MHz
device). In order to maintain the internal logic, each Read
access must be allowed to complete. Each Read access
consists of four 18-bit data words and takes 2 clock cycles to
complete. Therefore, Read accesses to the device can not be
initiated on two consecutive K clock rises. The internal logic of
the device will ignore the second Read request. Read
accesses can be initiated on every other K clock rise. Doing
so will pipeline the data flow such that data is transferred out
of the device on every rising edge of the output clocks (C and
C, or K and K when in single clock mode).
The
CY7C1305V25/CY7C1307V25
are
synchronous
pipelined Burst SRAMs equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write Port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, the device completely elimi-
nates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 18-bit data transfers in the case
of CY7C1305V25 and four 36-bit data transfers in the case of
CY7C1307V25, in two clock cycles.
When the read port is deselected, the CY7C1305V25 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the positive output clock (C). This will allow
for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is refer-
enced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the rising edge of output
clocks (C and C, or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of input clocks (K and
K). All synchronous data outputs (Q[x:0]) pass through output
registers controlled by the rising edge of the output clocks (C
and C, or K and K when in single clock mode).
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Data register provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
negative input clock (K) the information presented to D[17:0] is
also stored into the Write Data Register provided BWS[1:0] are
both asserted active. This process continues for one more
cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the positive clock (K). Doing so will
pipeline the data flow such that 18-bits of data can be trans-
ferred into the device on every rising edge of the input clocks
(K and K).
All synchronous control (RPS, WPS, BWS[0:x]) inputs pass
through input registers controlled by the rising edge of input
clocks (K and K).
CY7C1305V25 is described in the following sections. The
same basic descriptions apply to CY7C1307V25.
Read Operations
The CY7C1305V25 is organized internally as 4 arrays of 256K
x 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the Positive Input Clock (K).
The address presented to Address inputs are stored in the
Read address register. Following the next K clock rise the
corresponding lowest order 18-bit word of data is driven onto
the Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
When deselected, the write port will ignore all inputs after the
pending Write operations have been completed.
Document #: 38-05099 Rev. *B
Page 5 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Byte Write Operations
Read and Write accesses must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on
the previous state of the SRAM. If both ports were deselected,
the Read port will take priority. If a Read was initiated on the
previous cycle, the Write port will assume priority (since Read
operations can not be initiated on consecutive cycles). If a
Write was initiated on the previous cycle, the Read port will
assume priority (since Write operations can not be initiated on
consecutive cycles). Therefore, asserting both port selects
active from a deselected state will result in alternating
Read/Write operations being initiated, with the first access
being a Read.
Byte Write operations are supported by the CY7C1305V25. A
write operation is initiated as described in the Write Operation
section above. The bytes that are written are determined by
BWS0 and BWS1, which are sampled with each set of 18-bit
data word. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
Depth Expansion
The CY7C1305V25 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation.
The CY7C1305V25 has a Port Select input for each port. This
allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the positive input clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
Concurrent Transactions
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
The Read and Write ports on the CY7C1305V25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
V
DDQ=1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Document #: 38-05099 Rev. *B
Page 6 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Application Example[1]
Truth Table[2, 3, 4, 5, 6, 7, 8, 9]
Operation
K
L-H
RPS
WPS
DQ
DQ
DQ
DQ
Write Cycle:
H[8]
L[9] D(A+00)at
D(A+01) at
D(A+10) at
D(A+11) at
Load address on the rising edge
of K; wait one cycle; input write
data on two consecutive K and K
rising edges.
K(t+1) ↑
K(t+1) ↑
K(t+2) ↑
K(t+2) ↑
Read Cycle:
L-H
L[9]
X
Q(A+00) at
Q(A+01) at
Q(A+10) at Q(A+11) at
Load address on the rising edge
of K; wait one cycle; read data on
two consecutive C and C rising
edges.
C(t+1) ↑
C(t+1) ↑
C(t+2) ↑
C(t+2) ↑
NOP: No operation
L-H
H
X
H
X
D = X
D = X
D = X
D = X
Q = High-Z
Q = High-Z
Q = High-Z Q = High-Z
Standby: Clock stopped
Stopped
Previous state Previous state Previous
state
Previous
state
Notes:
1. The above application shows 4 QDR-I being used.
2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a don’t care for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read request.
Document #: 38-05099 Rev. *B
Page 7 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Write Cycle Descriptions (CY7C1305V25)[2, 10]
BWS0
BWS1
K
K
Comments
L
L
L
L
L
H
L-H
-
L-H
-
During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] will remain unaltered.
L-H
-
L
H
H
H
L
L
-
L-H
-
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] will remain unaltered.
L-H
-
During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into
the device. D[8:0] will remain unaltered.
L-H
During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into
the device. D[8:0] will remain unaltered.
H
H
H
H
L-H
-
-
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
L-H
Write Cycle Descriptions (CY7C1307V25)[2, 10]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L-H
-
-
During the Data portion of a Write sequence, all four bytes
(D[35:0]) are written into the device.
L
L
L
L
L
L-H
-
During the Data portion of a Write sequence, all four bytes
(D[35:0]) are written into the device.
During the Data portion of a Write sequence, only the lower
byte (D[8:0]) is written into the device. D[35:9] will remain un-
altered.
H
H
H
L-H
L
H
L
H
H
H
L
H
H
H
H
H
L
-
L-H
-
During the Data portion of a Write sequence, only the lower
byte (D[8:0]) is written into the device. D[35:9] will remain un-
altered.
During the Data portion of a Write sequence, only the byte
(D[17:9]) is written into the device. D[8:0] and D[35:18] will re-
main unaltered.
During the Data portion of a Write sequence, only the byte
(D[17:9]) is written into the device. D[8:0] and D[35:18] will re-
main unaltered.
During the Data portion of a Write sequence, only the byte
(D[26:18]) is written into the device. D[17:0] and D[35:27] will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D[26:18]) is written into the device. D[17:0] and D[35:27] will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D[35:27]) is written into the device. D[26:0] will remain unal-
tered.
During the Data portion of a Write sequence, only the byte
(D[35:27]) is written into the device. D[26:0] will remain unal-
tered.
H
H
H
H
H
H
L-H
L
-
L-H
-
H
H
H
H
L-H
L
-
L-H
H
H
L-H
-
L
L-H
H
H
H
H
H
H
H
H
L-H
-
-
No data is written into the device during this portion of a Write
operation.
No data is written into the device during this portion of a write
operation.
L-H
Note:
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS and BWS in the case of CY7C1305V25 and BWS and BWS in
0
1
2
3
the case of CY7C1307V25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.
Document #: 38-05099 Rev. *B
Page 8 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature ................................. –65°C to +150°C
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
DC Applied to Outputs in High-Z State –0.5V to VDDQ + 0.5V
DC Input Voltage[11] ............................ –0.5V to VDDQ + 0.5V
Ambient
[12]
[12]
Range Temperature (TA)
Com’l
VDD
VDDQ
1.4V to 1.9V
0°C to +70°C
2.5 ± 0.1V
Electrical Characteristics Over the Operating Range[13]
DC Electrical Characteristics Over the Operating Range
Parameter
VDD
VDDQ
VOH
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Min.
2.4
1.4
Typ.
2.5
1.5
Max.
2.6
1.9
Unit
V
V
V
V
V
V
V
V
Note 14
Note 15
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VREF + 0.1
–0.3
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
VOL
VOH(LOW) Output HIGH Voltage
VOL(LOW) Output LOW Voltage
VIH
VIL
VIN
IX
IOH = –0.1 mA, Nominal Impedance
IOH = 0.1 mA, Nominal Impedance
0.2
Input HIGH Voltage[11]
Input LOW Voltage[11, 16]
Clock Input Voltage
Input Load Current
Output Leakage Current
VDDQ + 0.3
VREF – 0.1
VDDQ + 0.3
5
–0.3
–5
–5
0.68
V
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ, Output Disabled
Typical value = 0.75V
µA
µA
V
IOZ
VREF
5
0.95
Input Reference
0.75
Voltage[17]
IDD
VDD Operating Supply
VDD = Max.,
167 MHz
550
470
420
350
330
250
mA
mA
mA
mA
mA
mA
I
OUT = 0 mA,
133 MHz
100 MHz
167 MHz
133 MHz
100 MHz
f = fMAX = 1/tCYC
ISB1
Automatic
Power-Down
Current
Max. VDD, Both Ports
Deselected,
V
IN ≤ VIH or VIN < VIL
f = fMAX = 1/tCYC, Inputs Static
AC Input Requirements Over the Operating Range
Test Conditions Min.
Parameter
VIH
Description
Typ.
–
Max.
–
Unit
V
Input High (Logic 1) Voltage
VREF + 0.2
VIL
Input Low (Logic 0) Voltage
–
–
VREF – 0.2
V
Notes:
11. Overshoot: V (AC) < V
+0.85V (Pulse width less than t
/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than t /2).
CYC
IH
DDQ
CYC
12. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
13. All Voltage referenced to Ground.
14. Output are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
DDQ
OH
OL
15. Output are impedance controlled. I = (V
2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
DDQ/
16. This spec is for all inputs except C and C Clock. For C and C Clock, V (Max.) = V
– 0.2V.
IL
REF
17. V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
(Max.) = 0.95V or 0.54V
, whichever is smaller.
DDQ
REF
DDQ
REF
Document #: 38-05099 Rev. *B
Page 9 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Thermal Resistance[18]
165 FBGA
Parameter
Description
Test Conditions
Package
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow
standard test methods
and procedures for mea-
suring thermal imped-
ance, per EIA/JESD51.
16.7
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.5
°C/W
Capacitance[18]
Parameter
Description
Test Conditions
Max.
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
5
6
7
V
DD = 2.5V.
CCLK
CO
Clock Input Capacitance
Output Capacitance
VDDQ = 1.5V
AC Test Loads and Waveforms
V
DDQ/2
VDDQ/2
VREF
OUTPUT
VREF
VDDQ/2
R = 50Ω
[18]
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
Under
Test
R = 50Ω
L
0.75V
Device
Under
0.25V
5 pF
VREF = 0.75V
ZQ
ZQ
Test
RQ=
RQ =
250 Ω
250Ω
(a)
INCLUDING
JIG AND
SCOPE
(b)
Note:
18. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05099 Rev. *B
Page 10 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Switching Characteristics Over the Operating Range[19]
-167
-133
-100
Cypress
Consortium
Parameter Parameter
Description
VCC (typical) to the First Access Read or Write
Min. Max. Min. Max. Min. Max. Unit
10
[20]
tPower
10
10
µs
Cycle Time
tCYC
tKH
tKL
tKHKH
tKHKL
tKLKH
tKHKH
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K/K Clock Rise to K/K Clock Rise and C/C to C/C 2.7
Rise (rising edge to rising edge)
6.0
2.4
2.4
7.5
3.2
3.2
3.4
10.0
3.5
3.5
4.4
ns
ns
ns
ns
tKHKH
3.3
2.0
4.1
2.5
5.4
3.0
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to 0.0
rising edge)
0.0
0.0
ns
Set-up Times
tSA tSA
tSC tSC
Address Set-up to Clock (K and K) Rise
Control Set-up to Clock (K and K) Rise (RPS,
WPS, BWS0, BWS1)
0.7
0.7
0.8
0.8
1.0
1.0
ns
ns
tSD
tSD
D[x:0] Set-up to Clock (K and K) Rise
0.7
0.8
1.0
ns
Hold Times
tHA
tHC
tHA
tHC
Address Hold after Clock (K and K) Rise
Control Signals Hold after Clock (K and K) Rise 0.7
(RPS, WPS, BWS0, BWS1)
0.7
0.8
0.8
1.0
1.0
ns
ns
tHD
tHD
D[x:0] Hold after Clock (K and K) Rise
0.7
0.8
1.0
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to
Data Valid[21]
Data Output Hold after Output C/C Clock Rise
(Active to Active)
2.5
2.5
3.0
3.0
3.0
3.0
ns
ns
ns
ns
tDOH
tCHZ
tCHQX
tCHZ
tCLZ
1.2
1.2
1.2
1.2
1.2
1.2
Clock (C and C) rise to High-Z (Active to
High-Z)[21, 22]
tCLZ
Clock (C and C) rise to Low-Z[21, 22]
Notes:
19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,V
= 0.75V, RQ = 250Ω, V
= 1.5V, input
DDQ
REF
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads.
OL OH
20. This part has a voltage regulator that steps down the voltage internally; t
or Write operation can be initiated.
is the time power needs to be supplied above V minimum initially before a Read
DD
Power
21. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
22. At any given voltage and temperature t
is less than t
and, t
less than t
.
CHZ
CLZ
CHZ
CO
Document #: 38-05099 Rev. *B
Page 11 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Switching Waveforms[23, 24, 25]
NOP
1
READ
2
WRITE
3
READ
4
WRITE
5
NOP
7
6
K
t
t
t
t
KH
KL
CYC
KHKH
K
RPS
t
t
t
t
SC
HC
HC
SC
WPS
A
A0
A1
A2
A3
t
t
HD
HD
t
t
SA
HA
t
t
SD
SD
D
Q
D10
D11
D12
D13
D30
D31
D32
D33
Qx3
Q00
Q01
Q02
Q03
Q20
Q21
Q22
Q23
t
t
KHCH
CO
t
DOH
t
t
t
CLZ
CHZ
t
t
CO
DOH
C
C
t
t
t
KHCH
CYC
KH
KL
t
KHKH
DON’T CARE
UNDEFINED
Notes:
23. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
24. Outputs are disabled (High-Z) one clock cycle after a NOP.
25. In this example, if address A2 = A1 then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results.This note applies to the whole
diagram.
Document #: 38-05099 Rev. *B
Page 12 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document #: 38-05099 Rev. *B
Page 13 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
SAMPLE Z
BYPASS
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Three-state
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a three-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus three-state”,
is latched into the preload register during the “Update-DR”
state in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05099 Rev. *B
Page 14 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
TAP Controller State Diagram[26]
TEST-LOGIC
RESET
1
0
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
SELECT
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
EXIT1-IR
0
1
0
EXIT1-DR
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
26. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05099 Rev. *B
Page 15 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
TDI
Selection
Circuitry
2
1
0
0
0
TDO
Circuitry
Instruction Register
29
31 30
.
.
2
1
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[11, 13, 27]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
IOH = −2.0 mA
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
Min.
1.7
2.1
Max.
Unit
V
V
V
V
V
V
µA
0.7
0.2
VDD+0.3
0.7
1.7
–0.3
−5
VIL
IX
Input LOW Voltage
Input and Output Load Current
GND ≤ VI ≤ VDDQ
5
Note:
27. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
Document #: 38-05099 Rev. *B
Page 16 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[28, 29]
Parameter
tTCYC
tTF
tTH
Description
Min.
100
Max.
Unit
ns
MHz
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
10
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
tTDIS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
10
10
10
ns
ns
ns
tCH
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
0
Notes:
28. Parameters t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
29. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document #: 38-05099 Rev. *B
Page 17 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
TAP Timing and Test Conditions[29]
1.25V
50Ω
ALL INPUT PULSES
1.25V
TDO
2.5V
Z =50Ω
0
C = 20 pF
L
0V
GND
(a)
tTL
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Document #: 38-05099 Rev. *B
Page 18 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Identification Register Definitions
Value
Instruction Field
CY7C1305V25
CY7C1307V25
Description
Revision Number
000
000
Version number.
(31:29)
Cypress Device ID
01011010011010101
01011010011100101
Defines the type of SRAM.
(28:12)
Cypress JEDEC ID
(11:1)
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence
1
Indicate the presence of an ID
(0)
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
107
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
SAMPLE/PRELOAD
011
100
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document #: 38-05099 Rev. *B
Page 19 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Boundary Scan Order (continued)
Boundary Scan Order
Bit #
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Bump ID
9B
10B
11A
Internal
9A
Bit #
0
1
2
3
4
5
6
Bump ID
6R
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
9M
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9N
11L
11M
9L
10L
11K
10K
9J
9K
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
10D
9E
10C
11D
9C
2F
3F
1G
1F
3G
2G
1J
2J
3K
3J
2K
9D
11B
11C
Document #: 38-05099 Rev. *B
Page 20 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Boundary Scan Order (continued)
Boundary Scan Order (continued)
Bit #
88
89
90
91
92
93
94
95
96
97
98
Bump ID
1K
Bit #
99
Bump ID
2P
2L
3L
1M
1L
3N
3M
1N
2M
3P
100
101
102
103
104
105
106
1P
3R
4R
4P
5P
5N
5R
2N
Ordering Information
Speed
Package
Operating
(MHz)
Ordering Code
CY7C1305V25-167BZC
CY7C1307V25-167BZC
CY7C1305V25-133BZC
CY7C1307V25-133BZC
CY7C1305V25-1300BZC
CY7C1307V25-100BZC
Name
Package Type
13 x 15 x 1.2 mm FBGA
Range
167
BB165A
Commercial
133
100
BB165A
BB165A
13 x 15 x 1.2 mm FBGA
13 x 15 x 1.2 mm FBGA
Document #: 38-05099 Rev. *B
Page 21 of 23
CY7C1305V25
CY7C1307V25
PRELIMINARY
Package Diagram
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress, IDT, NEC and Samsung.
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05099 Rev. *B
Page 22 of 23
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1305V25
CY7C1307V25
PRELIMINARY
Document History Page
Document Title: CY7C1305V25/CY7C1307V25 18-Mb Burst of 4 Pipelined SRAM with QDR™ Architecture
Document Number: 38-05099
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
New Data Sheet
107654
07/10/01
SKX
*A
122949
12/11/02
RCS
Changed Status to Preliminary from Advanced Information
Added Ex-Test feature to JTAG. This implementation is backwards compati-
ble with the previous Non-Ex-Test feature set
Changed Boundary Scan Order to 106 Cells from 69
Changed Cells 47 and 63 to an Internal Cells that are preset to LOW in the
Boundary Scan Order. Note that these pins are 100% compatible with the
previous scan order because they had previously been connected to VSS
Specified minimum and maximum input voltages for AC conditions
Changed packaged height to 1.4 mm from 1.2 mm
Changed ball diameter to 0.5 mm from 0.45 mm
Added tPower specification and note 20. These devices require 10 µs of VDD
above VDD minimum (2.4V) before operating
*B
203862
see ECN
DIM
Changed “Application Example” diagram
Changed “Switching Waveforms” diagram
Added “Thermal Resistance” table and values
Added “Capacitance” table and values
Changed package from BB165D to BB165A
Added VOH(LOW) and VOL(LOW) specs to the “Electrical Characteristics”
table
Revised the functional description of the device
Added IDD and ISB1 values to the Electrical Characteristics table
Document #: 38-05099 Rev. *B
Page 23 of 23
相关型号:
CY7C1305V25-200BZC
QDR SRAM, 1MX18, 2.3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165
CYPRESS
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