CY7C1306AV18-100BZC [CYPRESS]
18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Architecture; 18 -MB突发的2流水线SRAM与QDR ™架构型号: | CY7C1306AV18-100BZC |
厂家: | CYPRESS |
描述: | 18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Architecture |
文件: | 总20页 (文件大小:481K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
18-MbBurstof2PipelinedSRAMwithQDR™Architecture
Features
Functional Description
• Separate independent Read and Write data ports
The CY7C1303AV18 and CY7C1306AV18 are 1.8V
Synchronous Pipelined SRAMs equipped with QDR™ archi-
tecture. QDR architecture consists of two separate ports to
access the memory array. The Read port has dedicated Data
Outputs to support Read operations and the Write Port has
dedicated Data inputs to support Write operations. Access to
each port is accomplished through a common address bus.
The Read address is latched on the rising edge of the K clock
and the Write address is latched on the rising edge of K clock.
QDR has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common I/O devices. Accesses to the CY7C1303AV18/
CY7C1306AV18 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with Double Data Rate (DDR) inter-
faces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K) and out of the
device on every rising edge of the output clock (C and C, or K
and K when in single clock mode) thereby maximizing perfor-
mance while simplifying system design. Each address location
is associated with two 18-bit words (CY7C1303AV18) or two
36-bit words (CY7C1306AV18) that burst sequentially into or
out of the device.
— Supports concurrent transactions
• 167-MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11x15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
Depth expansion is accomplished with a Port Select input for
each port. Each Port Selects allow each port to operate
independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
• Variable Impedance HSTL
Configurations
CY7C1303AV18 – 1M x 18
CY7C1306AV18 – 512K x 36
Logic Block Diagram (CY7C1303AV18)
D[17:0]
18
Write
Write
Data Reg
Data Reg
Address
Register
A
(18:0)
Address
Register
A(18:0)
19
19
512Kx18 512Kx18
Memory Memory
Array
Array
K
CLK
Gen.
RPS
Control
Logic
K
C
C
Read Data Reg.
36
18
Vref
18
Reg.
Reg.
Reg.
18
18
Control
Logic
WPS
18
BWS0
Q[17:0]
BWS1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05492 Rev. *A
Revised June 1, 2004
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Logic Block Diagram (CY7C1306AV18)
D[35:0]
36
Write
Data Reg
Write
Data Reg
Address
A
Register
(17:0)
Address
Register
A(17:0)
18
18
256Kx36 256Kx36
Memory Memory
Array
Array
K
CLK
Gen.
RPS
Control
Logic
K
C
C
Read Data Reg.
72
36
Vref
36
Reg.
Reg.
Reg.
36
36
Control
Logic
WPS
36
BWS0
Q[35:0]
BWS1
BWS2
BWS3
Selection Guide
CY7C1303AV18-167
CY7C1306AV18-167
CY7C1303AV18-133 CY7C1303AV18-100
CY7C1306AV18-133 CY7C1306AV18-100
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
167
750
133
100
650
550
Pin Configuration – CY7C1303AV18 (Top View)
1
2
3
4
5
BWS1
NC
6
K
K
A
7
NC
BWS0
A
8
RPS
A
9
A
10
Gnd/72M
NC
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
Gnd/144M NC/36M
WPS
A
Q9
NC
D11
NC
Q12
D13
VREF
NC
NC
Q15
NC
D17
NC
TCK
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
C
C
A
A
A
A
Document #: 38-05492 Rev. *A
Page 2 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Pin Configuration–CY7C1306AV18 (Top View)
1
NC
2
3
4
5
BWS2
BWS3
A
6
K
K
A
7
BWS1
BWS0
A
8
RPS
A
9
10
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Gnd/288M NC/ 72M WPS
NC/36M Gnd/144M
Q27
D27
D28
Q29
Q30
D30
NC
D31
Q32
Q33
D33
D34
Q35
TDO
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
A
VSS
VSS
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
A
A
C
C
A
A
A
A
TMS
Pin Definitions
Name
I/O
Description
D[x:0]
Input-
Data input signals, sampled on the rising edge of K and K clocks during valid Write
Synchronous
operations.
CY7C1303AV18 – D[17:0]
CY7C1306AV18 – D[35:0]
WPS
Input-
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[x:0] to be ignored.
Synchronous
BWS0, BWS1,
BWS2, BWS3
Input-
Byte Write Select 0, 1, 2, and 3 - active LOW. Sampled on the rising edge of the K and
K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations.
Synchronous
CY7C1303AV18 - BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1306AV18 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18]
and BWS3 controls D[35:27]
Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the corre-
sponding byte of data to be ignored and not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active Read opera-
tions and on the rising edge of K for Write operations. These address inputs are multi-
plexed for both Read and Write operations. Internally, the device is organized as 1M x
18 (2 arrays each of 512K x 18) for CY7C1303AV18 and 512K x 36 (2 arrays each of
256K x 36) for CY7C1306AV18. Therefore, only 19 address inputs are needed to access
the entire memory array of CY7C1303AV18 and 18 address inputs for CY7C1306AV18.
These inputs are ignored when the appropriate port is deselected.
Synchronous
Q[x:0]
RPS
Outputs-
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Synchronous
Q
[x:0] are automatically three-stated.
CY7C1303AV18 - Q[17:0]
CY7C1306AV18 - Q[35:0]
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the K clock. Each
Read access consists of a burst of two sequential 18-bit or 36-bit transfers.
Input-
Synchronous
Document #: 38-05492 Rev. *A
Page 3 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Pin Definitions (continued)
Name
I/O
Description
C
C
K
Input-Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
Negative Output Clock Input. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board cack to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[x:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
Input-Clock
Input-Clock
K
Input-Clock
Input
Negative Input Clock Input. K is used to capture synchronous inputs to the device and
to drive out data through Q[x:0] when in single clock mode.
ZQ
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is
a resistor connected between ZQ and ground. Alternately, this pin can be connected
directly to VDD, which enables the minimum impedance mode. This pin cannot be
connected directly to GND or left unconnected.
TDO
TCK
TDI
TMS
NC/36M
Output
Input
Input
Input
N/A
TDO pin for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Address expansion for 36M. This pin is not connected to the die and so can be tied to
any voltage level on CY7C1303AV18/CY7C1306AV18.
GND/72M
NC/72M
Input
N/A
Address expansion for 72M. This pin has to be tied to GND on CY7C1303AV18.
Address expansion for 72M. This pin can be tied to any voltage level on
CY7C1306AV18.
GND/144M
Input
Address expansion for 144M. This pin has to be tied to GND on
CY7C1303AV18/CY7C1306AV18.
GND/288M
NC
Input
N/A
Address expansion for 288M. This pin has to be tied to GND on CY7C1306AV18.
No connected to the die. Can be tied to any voltage level.
VREF
Input-
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
Reference
and Outputs as well as AC measurement points.
VDD
VSS
Power Supply
Ground
Power supply inputs to the core of the device.
Ground for the device.
VDDQ
Power Supply
Power supply inputs for the outputs of the device.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is refer-
enced from the rising edge of the input clocks (K and K) and
all output timings are referenced to rising edge of output clocks
Introduction
Functional Overview
The CY7C1303AV18/CY7C1306AV18 are synchronous
pipelined Burst SRAMs equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, this architecture completely
eliminates the need to “turn-around” the data bus and avoids
any possible data contention, thereby simplifying system
design. Each access consists of two 18-bit data transfers in
the case of CY7C1303AV18, and two 36-bit data transfers in
the case of CY7C1306AV18, in one clock cycle.
(C and C, or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of the input clocks (K
and K). All synchronous data outputs (Q[x:0]) pass through
output registers controlled by the rising edge of the output
clocks (C and C, or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of input
clocks (K and K).
The following descriptions take CY7C1303AV18 as an
example. The same basic descriptions apply to
CY7C1306AV18.
Document #: 38-05492 Rev. *A
Page 4 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Read Operations
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
The CY7C1303AV18 is organized internally as two arrays of
512K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the positive input
clock (K). The address is latched on the rising edge of the K
clock. Following the next K clock rise the corresponding lower
order 18-bit word of data is driven onto the Q[17:0] using C as
the output timing reference. On the subsequent rising edge of
C the higher order data word is driven onto the Q[17:0]. The
requested data will be valid 2.5 ns from the rising edge of the
output clock (C and C, or K and K when in single clock mode,
167-MHz device).
Synchronous internal circuitry will automatically three-state
the outputs following the next rising edge of the positive output
clock (C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
Single Clock Mode
The CY7C1303AV18 can be used with a single clock mode. In
this mode the device will recognize only the pair of input clocks
(K and K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-up.This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1303AV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D[17:0] is latched and stored into the
lower 18-bit Write Data register provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is stored into the Write Data register
provided BWS[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified
location.
Depth Expansion
The CY7C1303AV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the positive input clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Programmable Impedance
Byte Write operations are supported by the CY7C1303AV18.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
mined by BWS0 and BWS1 which are sampled with each set
of 18-bit data words. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a Write will allow the data stored in the device for that byte
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
V
DDQ = 1.5V. The output impedance is adjusted every 1024
cycles to account for drifts in supply voltage and temperature.
Application Example[1]
Note:
1. The above application shows 4 QDR-I being used.
Document #: 38-05492 Rev. *A
Page 5 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Truth Table[2, 3, 4,5, 6, 7]
Operation
K
RPS
WPS
DQ
DQ
Write Cycle:
L-H
X
L
D(A+0)at
D(A+1) at
Load address on the rising edge of K clock; input write
data on K and K rising edges.
K(t) ↑
K(t) ↑
Read Cycle:
L-H
L
X
Q(A+0) at
Q(A+1) at
Load address on the rising edge of K clock; wait one
cycle; read data on 2 consecutive C and C rising edges.
C(t+1)↑
C(t+1) ↑
NOP: No Operation
L-H
H
X
H
X
D = X
D = X
Q = High-Z Q = High-Z
Standby: Clock Stopped
Stopped
Previous
State
Previous
State
Write Descriptions (CY7C1303AV18)[8]
BWS0
BWS1
L
L
K
L-H
-
K
-
Comments
L
L
L
During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
L-H During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
-
H
L-H
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] remains unaltered.
L
H
H
H
H
L
L
-
L-H
-
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] remains unaltered.
-
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.
[8:0] remains unaltered.
D
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.
D[8:0] remains unaltered.
H
H
L-H
-
-
No data is written into the device during this portion of a Write operation.
H
L-H No data is written into the device during this portion of a Write operation.
Notes:
2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
Document #: 38-05492 Rev. *A
Page 6 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Write Descriptions (CY7C1306AV18)[8]
BWS0 BWS1 BWS2 BWS3
K
L-H
K
Comments
During the Data portion of a Write sequence, all four bytes (D[35:0]
are written into the device.
During the Data portion of a Write sequence, all four bytes (D[35:0]
are written into the device.
During the Data portion of a Write sequence, only the lower byte
(D[8:0]) is written into the device. D[35:9] will remain unaltered.
During the Data portion of a Write sequence, only the lower byte
(D[8:0]) is written into the device. D[35:9] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
L
L
L
L
-
L-H
-
)
)
L
L
L
L
-
L-H
-
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
L
L-H
-
H
H
H
H
H
H
H
H
L-H
-
L
L-H
-
H
H
H
H
H
H
L-H
-
During the Data portion of a Write sequence, only the byte (D[26:18]
)
)
)
)
is written into the device. D[17:0] and D[35:27] will remain unaltered.
L
L-H
-
During the Data portion of a Write sequence, only the byte (D[26:18]
is written into the device. D[17:0] and D[35:27] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[35:27]
is written into the device. D[26:0] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[35:27]
is written into the device. D[26:0] will remain unaltered.
No data is written into the device during this portion of a Write
operation.
H
H
H
H
L-H
-
L
L-H
-
H
H
L-H
-
L-H
No data is written into the device during this portion of a Write
operation.
Note:
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS , BWS , BWS , and BWS can be altered on different portions of a
0
1
2
3
Write cycle, as long as the set-up and hold requirements are achieved.
Document #: 38-05492 Rev. *A
Page 7 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
Ambient
[10]
[10]
DC Applied to Outputs
Range Temperature (TA)
VDD
1.8 ± 0.1V
VDDQ
1.4V to VDD
in High-Z State .................................... –0.5V to VDDQ + 0.5V
Com’l
0°C to +70°C
DC Input Voltage[9].............................. –0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range [11]
DC Electrical Characteristics
Parameter
VDD
VDDQ
VOH
VOL
VOH(LOW)
VOL(LOW)
VIH
VIL
VIN
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
1.7
1.4
Typ.
1.8
1.5
Max.
1.9
VDD
VDDQ/2 + 0.12
Unit
V
V
V
V
V
V
V
V
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[9]
Input LOW Voltage[9, 14]
Clock Input Voltage
Input Load Current
Note 12
Note 13
VDDQ/2 – 0.12
VDDQ/2– 0.12
VDDQ/2 + 0.12
IOH = –0.1 mA, Nominal Impedance VDDQ – 0.2
IOL = 0.1 mA, Nominal Impedance
VDDQ
0.2
VDDQ + 0.3
VREF – 0.1
VDDQ + 0.3
5
VSS
VREF + 0.1
–0.3
–0.3
–5
–5
0.68
V
IX
IOZ
VREF
IDD
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ, Output Disabled
µA
µA
V
mA
mA
mA
mA
mA
mA
Output Leakage Current
5
0.95
750
650
550
470
450
430
Input Reference Voltage[15] Typical value = 0.75V
0.75
VDD Operating Supply
VDD = Max.,
167 MHz
133 MHz
100 MHz
167 MHz
133 MHz
100 MHz
IOUT = 0 mA,
f = fMAX = 1/tCYC
ISB1
Automatic Power-Down
Current
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
V
IN ≤ VIL f = fMAX = 1/tCYC,
Inputs Static
AC Input Requirements
Parameter
Description
Test Conditions
Min.
VREF + 0.2
–
Typ.
–
–
Max.
–
VREF – 0.2
Unit
V
V
VIH
Input High (Logic 1) Voltage
VIL
Input Low (Logic 0) Voltage
Notes:
9. Overshoot: V (AC) < V
+0.85V (Pulse width less than t
/2), Undershoot: V (AC) > –1.5V (Pulse width less than t
/2).
IH
DDQ
CYC
IL
CYC
10. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
11. All voltage referenced to ground.
12. Output are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
DDQ
OH
OL
13. Output are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
DDQ
14. This spec is for all inputs except C and C Clock. For C and C Clock, V (Max.) = V
– 0.2V.
IL
REF
15. V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
(Max.) = 0.95V or 0.54V
, whichever is smaller.
DDQ
REF
DDQ
REF
Document #: 38-05492 Rev. *A
Page 8 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Thermal Resistance[16]
165 FBGA
Parameter
Description
Test Conditions
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard test methods and proce-
16.7
°C/W
(Junction to Ambient)
dures for measuring thermal impedance, per EIA/JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
6.5
°C/W
Capacitance[16]
Parameter
Description
Input Capacitance
Clock Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Max.
Unit
pF
pF
CIN
CCLK
CO
5
6
7
V
DD = 1.8V.
DDQ = 1.5V
V
pF
AC Test Loads and Waveforms
V
DDQ/2
V
DDQ/2
VREF
OUTPUT
VREF
V
DDQ/2
R = 50Ω
[17]
ALL INPUT PULSES
Z = 50Ω
0
OUTPUT
1.25V
Device
Under
Test
R = 50Ω
L
0.75V
Device
Under
0.25V
5 pF
VREF = 0.75V
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
(a)
INCLUDING
JIG AND
SCOPE
(b)
Switching Characteristics Over the Operating Range[17]
-167
-133
-100
Cypress
Consortium
Parameter
Parameter
Description
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
Min. Max. Min. Max. Min. Max. Unit
tCYC
tKH
tKL
tKHKH
tKHKL
tKLKH
tKHKH
6.0
2.4
2.4
7.5
3.2
3.2
3.4
10.0
3.5
3.5
ns
ns
ns
ns
tKHKH
K/K Clock Rise to K/K Clock Rise and C/C to C/C 2.7
Rise (rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to 0.0
rising edge)
3.3
2.0
4.1
2.5
4.4
5.4
3.0
tKHCH
tKHCH
0.0
0.0
ns
Set-up Times
tSA tSA
tSC tSC
Address Set-up to Clock (K and K) Rise
Control Set-up to Clock (K and K) Rise (RPS,
WPS, BWS0, BWS1)
0.7
0.7
0.8
0.8
1.0
1.0
ns
ns
tSD
Hold Times
tHA
tSD
D[x:0] Set-up to Clock (K and K) Rise
0.7
0.7
0.8
0.8
1.0
1.0
ns
ns
tHA
Address Hold after Clock (K and K) Rise
Notes:
16. Tested initially and after any design or process change that may affect these parameters.
17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250Ω, V
= 1.5V, input
DDQ
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC test loads.
OL OH
Document #: 38-05492 Rev. *A
Page 9 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Switching Characteristics Over the Operating Range[17]
-167
-133
-100
Cypress
Consortium
Parameter
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
tHC
tHC
Control Signals Hold after Clock (K and K) Rise 0.7
0.8
0.8
1.0
1.0
ns
ns
(RPS, WPS, BWS0, BWS1)
tHD
Output Times
tHD
D[x:0] Hold after Clock (K and K) Rise
0.7
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to
Data Valid
Data Output Hold after Output C/C Clock Rise
(Active to Active)
2.5
2.5
3.0
3.0
3.0
3.0
ns
ns
ns
ns
tDOH
tCHZ
tCHQX
tCHZ
tCLZ
1.2
1.2
1.2
1.2
1.2
1.2
Clock (C and C) Rise to High-Z (Active to
High-Z)[18, 19]
tCLZ
Clock (C and C) Rise to Low-Z[18, 19]
Notes:
18. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
19. At any given voltage and temperature t
is less than t
and, t
less than t
.
CHZ
CLZ
CHZ
CO
Document #: 38-05492 Rev. *A
Page 10 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Switching Waveforms[20, 21, 22]
READ
1
WRITE
2
READ
3
WRITE
READ
5
WRITE
NOP
7
WRITE
8
NOP
9
6
4
10
K
t
t
t
t
KHKH
KH
KL
CYC
K
RPS
tSC
tHC
WPS
A
A5
A6
A0
A1
A2
A3
A4
t
t
t
t
SA HA
SA HA
D
Q
D10
D11
D30
D31
D50
D51
D60
D61
t
t
HD
t
SD
HD
t
SD
Q00
Q01
Q20
Q21
Q40
Q41
t
CHZ
t
t
t
DOH
DOH
CLZ
t
t
t
t
CO
KHCH
KHCH
CO
C
C
t
t
t
KHKH
tCYC
KH
KL
DON’T CARE
UNDEFINED
Notes:
20. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
21. Outputs are disabled (High-Z) one clock cycle after a NOP.
22. In this example, if address A2 = A1 then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.
Document #: 38-05492 Rev. *A
Page 11 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document #: 38-05492 Rev. *A
Page 12 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
SAMPLE Z
BYPASS
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Three-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a three-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus three-state”,
is latched into the preload register during the “Update-DR”
state in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05492 Rev. *A
Page 13 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
TAP Controller State Diagram[23]
TEST-LOGIC
RESET
1
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
SELECT
0
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
23. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05492 Rev. *A
Page 14 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
TDI
Selection
2
1
0
0
0
TDO
Circuitry
Circuitry
Instruction Register
29
31 30
.
.
2
1
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range [11, 9, 24]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
IOH = −2.0 mA
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
Min.
1.4
1.6
Max.
Unit
V
V
V
V
V
V
µA
0.4
0.2
VDD + 0.3
0.35VDD
5
0.65VDD
–0.3
VIL
IX
Input LOW Voltage
Input and Output Load Current
GND ≤ VI ≤ VDDQ
−5
TAP AC Switching Characteristics Over the Operating Range [25, 26]
Parameter
tTCYC
tTF
tTH
Description
Min.
100
Max.
10
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
ns
MHz
ns
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
tTDIS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
10
10
10
ns
ns
ns
tCH
Notes:
24. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
25. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
26. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document #: 38-05492 Rev. *A
Page 15 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range (continued)[25, 26]
Parameter
Output Times
tTDOV
Description
Min.
Max.
Unit
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
tTDOX
0
TAP Timing and Test Conditions[26]
0.9V
ALL INPUT PULSES
0.9V
1.8V
50Ω
0V
TDO
Z = 50Ω
0
C = 20pF
L
(a)
GND
tTL
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Identification Register Definitions
Value
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
CY7C1303AV18
000
CY7C1306AV18
Description
000
Version number.
11010010010010101 11010010010100101 Defines the type of SRAM.
00000110100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Document #: 38-05492 Rev. *A
Page 16 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
107
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
SAMPLE/PRELOAD
011
100
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Boundary Scan Order (continued)
Boundary Scan Order
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Bump ID
Bit #
0
1
2
3
4
5
6
Bump ID
6R
9J
9K
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
9M
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
10D
9E
10C
11D
9C
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
9N
11L
11M
9L
10L
11K
10K
9D
11B
11C
9B
10B
11A
Document #: 38-05492 Rev. *A
Page 17 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Boundary Scan Order (continued)
Boundary Scan Order (continued)
Bit #
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Bump ID
Bit #
91
92
93
94
95
96
97
Bump ID
1M
1L
Internal
9A
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1J
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
98
99
100
101
102
103
104
105
106
4P
5P
5N
5R
2J
3K
3J
2K
1K
2L
3L
Document #: 38-05492 Rev. *A
Page 18 of 20
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Ordering Information
Speed
Package
Operating
Range
Commercial
(MHz)
Ordering Code
Name
Package Type
13 x 15 x 1.4 mm FBGA
167
CY7C1303AV18-167BZC
CY7C1306AV18-167BZC
CY7C1303AV18-133BZC
CY7C1306AV18-133BZC
CY7C1303AV18-100BZC
CY7C1306AV18-100BZC
BB165D
133
100
BB165D
BB165D
13 x 15 x 1.4 mm FBGA
13 x 15 x 1.4 mm FBGA
Package Diagram
165 FBGA 13 x 15 x 1.40 mm BB165D
51-85180-**
Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress, IDT, NEC and Samsung.
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05492 Rev. *A
Page 19 of 20
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1303AV18
CY7C1306AV18
PRELIMINARY
Document History Page
Document Title: CY7C1303AV18/CY7C1306AV18 18-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture
Document Number: 38-05492
Orig. of
REV.
**
*A
ECN NO.
208401
230396
Issue Date
see ECN
see ECN
Change
DIM
Description of Change
New Data Sheet
VBL
Upload datasheet to the internet
Document #: 38-05492 Rev. *A
Page 20 of 20
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明