CY7C1311AV18-167BZC [CYPRESS]
18-Mb QDRTM-II SRAM 4-Word Burst Architecture; 18 -MB QDRTM - II SRAM 4字突发架构
| 型号： | CY7C1311AV18-167BZC |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mb QDRTM-II SRAM 4-Word Burst Architecture |
| 文件： | 总22页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
18-Mb QDR™-II SRAM 4-Word Burst Architecture
Features
Functional Description
• Separate Independent Read and Write Data Ports
— Supports concurrent transactions
The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are
1.8V Synchronous Pipelined SRAMs, equipped with QDR-II
architecture. QDR-II architecture consists of two separate
ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data Inputs to support Write opera-
tions. QDR-II architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus.
Addresses for Read and Write addresses are latched on
alternate rising edges of the input (K) clock. Accesses to the
QDR-II Read and Write ports are completely independent of
one another. In order to maximize data throughput, both Read
and Write ports are equipped with Double Data Rate (DDR)
interfaces. Each address location is associated with four 8-bit
words (CY7C1311AV18) or 18-bit words (CY7C1313AV18) or
36-bit words (CY7C1315AV18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K and
K and C and C), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
• 250-MHz Clock for High Bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 500 MHz) at 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in high
speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in ×8, ×18, and ×36 configurations
• Full data coherancy providing most current data
• Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd)
• 13 × 15 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball
Depth expansion is accomplished with Port Selects for each
(11 × 15 matrix)
port. Port selects allow each port to operate independently.
• Variable drive HSTL output buffers
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
• JTAG 1149.1 Compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1311AV18–2M x 8
CY7C1313AV18–1M x 18
CY7C1315AV18–512K x 36
Logic Block Diagram (CY7C1311AV18)
D[7:0]
8
Write Write Write Write
Address
Register
A(18:0)
Reg Reg Reg
Reg
19
Address
Register
A(18:0)
19
RPS
K
Control
Logic
CLK
K
Gen.
C
C
DOFF
Read Data Reg.
32
CQ
CQ
16
VREF
WPS
BWS[1:0]
Reg.
Reg.
Reg.
Control
Logic
16
8
Q[7:0]
8
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05498 Rev. *A
Revised June 1, 2004
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Logic Block Diagram (CY7C1313AV18)
D[17:0]
18
Write Write Write Write
Address
Register
A(17:0)
18
Reg Reg Reg
Reg
Address
Register
A(17:0)
18
RPS
C
K
Control
Logic
CLK
K
Gen.
DOFF
Read Data Reg.
72
C
CQ
CQ
36
VREF
WPS
BWS[1:0]
Reg.
Reg.
Reg.
Control
Logic
36
18
Q[17:0]
18
Logic Block Diagram (CY7C1315AV18)
D[35:0]
36
Write
Write Write
Write
Address
Register
A(16:0)
Reg Reg Reg
Reg
17
Address
Register
A(16:0)
17
RPS
K
Control
Logic
CLK
K
Gen.
C
C
DOFF
Read Data Reg.
144
CQ
CQ
72
VREF
WPS
BWS[3:0]
Reg.
Reg.
Reg.
Control
Logic
72
36
Q[35:0]
36
Selection Guide
250 MHz
250
200 MHz
200
167 MHz
167
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
800
700
640
Document #: 38-05498 Rev. *A
Page 2 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Pin Configurations
1
CY7C1311AV18 (2M × 8)–11 × 15 FBGA
2
3
6
K
K
NC
VSS
9
10
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
5
7
8
4
WPS
A
VSS
VSS
VSS/72M
NC
A
NC/144M
A
VSS/36M
A
B
C
D
E
F
CQ
NC
BWS1
NC/288M
RPS
NC
NC
NC
Q4
NC
Q5
VDDQ
NC
NC
D6
NC
NC
Q7
A
VSS
VSS
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
D2
NC
NC
VREF
Q1
NC
NC
NC
NC
NC
BWS0
A
VSS
NC
NC
NC
NC
NC
NC
D4
NC
NC
D5
A
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
G
VREF
NC
NC
Q6
H
DOFF
NC
J
NC
NC
NC
NC
NC
K
L
M
N
P
NC
D7
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
D0
NC
NC
A
C
A
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
CY7C1313AV18 (1M × 18)–11 × 15 FBGA
2
3
5
6
7
9
10
11
1
CQ
NC
NC
NC
NC
NC
NC
4
WPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS/144M NC/36M
K
A
VSS/72M
CQ
Q8
D8
D7
A
NC/288M
BWS1
NC
A
Q9
NC
D11
NC
Q12
D13
VREF
NC
NC
Q15
NC
D17
NC
D9
D10
Q10
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
B
C
D
E
F
G
H
J
K
L
M
N
P
BWS0
A
VSS
VSS
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
DOFF
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
C
VSS
VSS
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
Document #: 38-05498 Rev. *A
Page 3 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Pin Configurations (continued)
CY7C1315AV18 (512K × 36)–11 × 15 FBGA
7
1
CQ
Q27
D27
D28
Q29
Q30
D30
2
3
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
9
10
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
4
WPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
5
6
K
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
VSS/288M NC/72M
NC/36M VSS/144M
A
B
C
D
E
F
G
H
J
K
L
M
N
P
BWS1
BWS0
A
BWS2
BWS3
A
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
DOFF
D31
Q32
Q33
D33
D34
Q35
Q34
D26
D35
D25
Q25
Q26
VSS
VSS
VSS
VSS
D10
Q10
Q9
D2
D1
Q0
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
Pin Definitions
Pin Name
I/O
Pin Description
Data input signals, sampled on the rising edge of K and K clocks during valid write opera-
D[x:0]
Input-
Synchronous tions.
CY7C1311AV18 − D[7:0]
CY7C1313AV18 − D[17:0]
CY7C1315AV18 − D[35:0]
WPS
Input-
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
Synchronous a write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D[x:0] to be ignored.
BWS0,BWS1,
Input-
Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and K clocks
BWS2, BWS3 Synchronous during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1311AV18 − BWS0 controls D[3:0] and BWS1 controls D[7:4]
.
CY7C1313AV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1315AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active read and write opera-
Synchronous tions. These address inputs are multiplexed for both Read and Write operations. Internally, the
device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1311AV18, 1M x 18 (4 arrays
each of 256K x 18) for CY7C1313AV18 and 512K x 36 (4 arrays each of 128K x 36) for
CY7C1315AV18. Therefore, only 19 address inputs are needed to access the entire memory
array of CY7C1311AV18, 18 address inputs for CY7C1313AV18 and 17 address inputs for
CY7C1315AV18.These inputs are ignored when the appropriate port is deselected.
Document #: 38-05498 Rev. *A
Page 4 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Pin Definitions (continued)
Pin Name
Q[x:0]
I/O
Pin Description
Outputs-
Data Output signals. These pins drive out the requested data during a Read operation. Valid
Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K. when in single clock mode. When the Read port is deselected, Q[x:0] are automatically
tri-stated.
CY7C1311AV18 − Q[7:0]
CY7C1313AV18 − Q[17:0]
CY7C1315AV18 − Q[35:0]
RPS
Input-
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When
Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the C clock. Each read access consists of a burst of
four sequential transfers.
C
C
K
Input-
Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Input-
Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
CQ
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the
output clock(C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
CQ
ZQ
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the
output clock(C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ,CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDD, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
More details on this operation can be found in the application note, “DLL Operation in the QDR-II.”
TDO
TCK
TDI
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS
NC
TMS pin for JTAG.
Not connected to the die. Can be tied to any voltage level.
NC/36M
N/A
Address expansion for 36M. This is not connected to the die and so can be tied to any voltage
level.
NC/72M
N/A
Address expansion for 72M. This is not connected to the die and so can be tied to any voltage
level.
VSS/72M
VSS/144M
VSS/288M
Input
Input
Input
Address expansion for 72M. This must be tied LOW on the these devices.
Address expansion for 144M. This must be tied LOW on the these devices.
Address expansion for 288M. This must be tied LOW on the these devices.
Document #: 38-05498 Rev. *A
Page 5 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Pin Definitions (continued)
Pin Name
VREF
I/O
Pin Description
Input-
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
Reference as well as AC measurement points.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
Introduction
Functional Overview
words and takes 2 clock cycles to complete. Therefore, Read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Read request. Read accesses can be initiated on
every other K clock rise. Doing so will pipeline the data flow
such that data is transferred out of the device on every rising
edge of the output clocks (C and C or K and K when in
single-clock mode).
When the read port is deselected, the CY7C1313AV18 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically tri-state the outputs following the
next rising edge of the Positive Output Clock (C). This will
allow for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are
synchronous pipelined Burst SRAMs equipped with both a
Read Port and a Write Port. The Read port is dedicated to
Read operations and the Write Port is dedicated to Write
operations. Data flows into the SRAM through the Write port
and out through the Read Port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate Read and Write ports, the QDR-II
completely eliminates the need to “turn-around” the data bus
and avoids any possible data contention, thereby simplifying
system design. Each access consists of four 8-bit data
transfers in the case of CY7C1311AV18, four 18-bit data
transfers in the case of CY7C1313AV18, and four 36-bit data
in the case of CY7C1315AV18 transfers in two clock cycles.
Accesses for both ports are initiated on the Positive Input
Clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the output clocks (C and C or K and K when
in single clock mode).
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single-clock mode).
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Data register, provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K) the information presented to D[17:0]
is also stored into the Write Data Register, provided BWS[1:0]
are both asserted active. This process continues for one more
cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the Positive Input Clock (K). Doing
so will pipeline the data flow such that 18 bits of data can be
transferred into the device on every rising edge of the input
clocks (K and K).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1313AV18 is described in the following sections. The
same basic descriptions apply to CY7C1311AV18 and
CY7C1315AV18.
Read Operations
When deselected, the write port will ignore all inputs after the
The CY7C1313AV18 is organized internally as 4 arrays of
256K x 18. Accesses are completed in a burst of four
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the Positive Input
Clock (K). The address presented to Address inputs are stored
in the Read address register. Following the next K clock rise,
the corresponding lowest order 18-bit word of data is driven
onto the Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data
will be valid 0.45 ns from the rising edge of the output clock (C
or C or (K or K when in single-clock mode)). In order to
maintain the internal logic, each read access must be allowed
to complete. Each Read access consists of four 18-bit data
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1313AV18.
A write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
mined by BWS0 and BWS1, which are sampled with each set
of 18-bit data words. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Document #: 38-05498 Rev. *A
Page 6 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Single Clock Mode
Depth Expansion
The CY7C1313AV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power on. This function is
a strap option and not alterable during device operation.
The CY7C1313AV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
Concurrent Transactions
The Read and Write ports on the CY7C1313AV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. If the ports access the same location
when a read follows a write in successive clock cycles, the
SRAM will deliver the most recent information associated with
the specified address location. This includes forwarding data
from a Write cycle that was initiated on the previous K clock
rise.
Read accesses and Write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on
the previous state of the SRAM. If both ports were deselected,
the Read port will take priority. If a Read was initiated on the
previous cycle, the Write port will assume priority (since Read
operations can not be initiated on consecutive cycles). If a
Write was initiated on the previous cycle, the Read port will
assume priority (since Write operations can not be initiated on
consecutive cycles). Therefore, asserting both port selects
active from a deselected state will result in alternating
Read/Write operations being initiated, with the first access
being a Read.
V
DDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon powerup to account for drifts in supply voltage and
temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data
capture on high speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are free running
clocks and are synchronized to the output clock of the QDR-II.
In the single clock mode, CQ is generated with respect to K
and CQ is generated with respect to K. The timings for the
echo clocks are shown in the AC timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. The DLL can also be reset by slowing the cycle time
of input clocks K and K to greater than 30 ns.
Application Example[1]
R = 250ohms
SRAM #4
R = 250ohms
ZQ
SRAM #1
R
ZQ
CQ/CQ#
Q
R W
B
W
P
B
W
S
Vt
CQ/CQ#
P
S
#
P
S
#
P
S
#
W
S
D
A
D
A
Q
S
#
R
C
C#
K
K#
C
C#
K
K#
#
#
DATA IN
DATA OUT
Address
Vt
Vt
R
RPS#
BUS
MASTER
(CPU
or
ASIC)
WPS#
BWS#
CLKIN/CLKIN#
Source K
Source K#
Delayed K
Delayed K#
R
R = 50ohms
Vt = Vddq/2
Note:
1. The above application shows four QDRII being used.
Document #: 38-05498 Rev. *A
Page 7 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Truth Table[ 2, 3, 4, 5, 6, 7]
Operation
Write Cycle:
K
RPS
H[8]
WPS
L[9]
DQ
DQ
DQ
D(A + 2) at K(t D(A + 3) at
+ 2) ↑ K(t +2) ↑
DQ
L-H
L-H
D(A) at
D(A + 1) at
Load address on the rising
edgeofK;inputwritedataon
two consecutive K and K
rising edges.
K(t+1) ↑
K(t+1) ↑
Read Cycle:
L[9]
X
Q(A) at
Q(A + 1) at
Q(A + 2) at C(t Q(A + 3) at C(t
Load address on the rising
edge of K; wait one and a
half cycle; read data on two
consecutive C and C rising
edges.
C(t +1)↑
C(t + 2) ↑
+ 2)↑
+ 3) ↑
NOP: No Operation
L-H
H
X
H
X
D=X
D=X
D=X
D=X
Q=High-Z
Q=High-Z
Q=High-Z
Q=High-Z
Standby: Clock Stopped
Stopped
Previous State Previous State Previous
State
Previous State
[2, 10]
Write Cycle Descriptions CY7C1311AV18 and CY7C1313AV18)
BWS0 BWS1
K
K
Comments
L
L
L–H
–
During the Data portion of a Write sequence :
CY7C1311AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1313AV18 − both bytes (D[17:0]) are written into the device.
L
L
–
L–H
–
L-H During the Data portion of a Write sequence :
CY7C1311AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1313AV18 − both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the Data portion of a Write sequence :
CY7C1311AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,
CY7C1313AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
L
L–H During the Data portion of a Write sequence :
CY7C1311AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,
CY7C1313AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
H
H
H
L–H
–
–
During the Data portion of a Write sequence :
CY7C1311AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,
CY7C1313AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.
L
L–H During the Data portion of a Write sequence :
CY7C1311AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,
CY7C1313AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
H
L–H No data is written into the devices during this portion of a write operation.
Notes:
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t”
clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read or Write request.
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS , BWS in the case of CY7C1311AV18 and CY7C1313AV18 and also
0
1
BWS , BWS in the case of CY7C1315AV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
2
3
Document #: 38-05498 Rev. *A
Page 8 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Write Cycle Descriptions[2, 10](CY7C1315AV18)
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L
L
L
L
–
L–H
–
L–H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
L
L–H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
H
H
H
H
H
H
L–H
–
–
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
L
L–H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
H
H
H
H
L–H
–
–
During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
L
L–H During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
H
H
L–H
–
During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
L
L–H During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Document #: 38-05498 Rev. *A
Page 9 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Latch-up Current..................................................... >200 mA
Maximum Ratings (Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
DC Applied to Outputs in High-Z .........–0.5V to VDDQ + 0.5V
DC Input Voltage[14] ............................ –0.5V to VDDQ + 0.5V
Current into Outputs (LOW).........................................20 mA
Operating Range
Ambient
[16]
[16]
Range Temperature(TA)
VDD
VDDQ
1.4V to VDD
Com’l
0°C to +70°C
1.8 ± 0.1V
DC Electrical Characteristics Over the Operating Range[11]
Parameter
VDD
VDDQ
VOH
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Test Conditions
Min.
1.7
1.4
VDDQ/2
-0.12
VDDQ/2
-0.12
Typ.
1.8
1.5
Max.
1.9
VDD
VDDQ/2 +
0.12
Unit
V
V
[12]
[13]
V
VOL
Output LOW Voltage
VDDQ/2 +
0.12
V
VOH(LOW)
VOL(LOW)
VIH
VIL
VIN
IX
IOZ
VREF
IDD
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[14]
Input LOW Voltage[14,15]
Clock Input Voltage
Input Load Current
Output Leakage Current
Input Reference Voltage[17] Typical Value = 0.75V
IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2
VDDQ
0.2
VDDQ+0.3
VREF–0.1
VDDQ + 0.3
5
V
V
V
V
V
µA
µA
V
mA
mA
mA
mA
mA
mA
IOL = 0.1mA, Nominal Impedance
VSS
VREF + 0.1
–0.3
–0.3
-
GND ≤ VI ≤ VDDQ
−5
GND ≤ VI ≤ VDDQ, Output Disabled
−5
5
0.95
640
700
800
420
450
490
0.68
0.75
VDD Operating Supply
VDD = Max., IOUT = 0
mA,
167 MHz
200 MHz
250 MHz
167 MHz
200 MHz
250 MHz
f = fMAX = 1/tCYC
ISB1
Automatic
Power-down
Curren
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
V
IN ≤ VIL f = fMAX =
1/tCYC
,
Inputs Static
Notes:
11. All Voltage referenced to Ground.
12. Output are impedance controlled. Ioh=−(Vddq/2)/(RQ/5) for values of 175ohms <= RQ <= 350ohms.
13. Output are impedance controlled. Iol=(Vddq/2)/(RQ/5) for values of 175ohms <= RQ <= 350ohms.
14. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).
15. This spec is for all inputs except C and C clocks. For C and C clocks, VIL(Max.) = VREF − 0.2V.
17. V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
(Max.) = 0.95V or 0.54V
DDQ
16. Power-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VI,Hw<hVicDhDeavnedr iVsDsDmQa<lleVrD. D
REF
DDQ
REF
Document #: 38-05498 Rev. *A
Page 10 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
AC Electrical Characteristics Over the Operating Range
Parameter
VIH
VIL
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Test Conditions
Min.
VREF + 0.2
–
Typ.
–
–
Max.
–
VREF – 0.2
Unit
V
V
Switching Characteristics Over the Operating Range[18,19]
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
K Clock and C Clock Cycle Time
Input Clock (K/K; C/C) HIGH
Input Clock (K/K; C/C) LOW
Min. Max. Min. Max. Min. Max. Unit
tCYC
tKHKH
tKHKL
tKLKH
tKHKH
4.0
1.6
1.6
1.8
5.25
5.0
2.0
2.0
2.2
6.3
6.0
2.4
2.4
2.7
8.4
–
–
–
ns
ns
ns
ns
tKH
–
–
–
tKL
–
–
tKHKH
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to 0.0
rising edge)
1.8
0.0
2.3
0.0
2.8
ns
Set-up Times
tSA tSA
tSC
Address Set-up to K Clock Rise
0.5
0.5
–
–
0.6
0.6
–
–
0.7
0.7
–
–
ns
ns
tSC
tSC
tSD
Control Set-up to Clock (K, K, C, C) Rise (RPS,
WPS)
tSCDDR
Double Data Rate Control Set-up to Clock (K, K) 0.35
Rise (BWS0, BWS1, BWS2, BWS3)
D[X:0] Set-up to Clock (K/K) Rise
–
–
0.4
0.4
–
–
0.5
0.5
–
–
ns
ns
tSD
0.35
Hold Times
tHA
tHC
tHA
tHC
tHC
Address Hold after Clock (K/K) Rise
Control Hold after Clock (K /K) Rise (RPS, WPS) 0.5
0.5
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
tHCDDR
Double Data Rate Control Hold after Clock (K/K) 0.35
Rise (BWS0, BWS1, BWS2, BWS3)
tHD
tHD
D[X:0] Hold after Clock (K/K) Rise
0.35
–
0.4
–
0.5
–
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to
Data Valid
–
0.45
–
–
0.45
–
–
0.50
–
ns
ns
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise
–0.45
-0.45
-0.50
(Active to Active)
tCCQO
tCQOH
tCQD
tCQDOH
tCHZ
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHZ
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
–
–0.45
–
–0.30
–
0.45
–
0.30
–
–
–0.45
–
–0.35
–
0.45
–
0.35
–
–
–0.50
–
–0.40
–
0.50
–
0.40
–
ns
ns
ns
ns
ns
Echo Clock High to Data Invalid
Clock (C and C) Rise to High-Z (Active to
0.45
0.45
0.50
High-Z)[20, 21]
tCLZ
tCLZ
Clock (C and C) Rise to Low-Z[20, 21]
–0.45
–
–0.45
–
–0.50
–
ns
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
–
1024
30
0.20
–
–
1024
30
0.20
–
–
1024
30
0.20
–
ns
cycles
ns
tKC lock
tKC lock
tKC Reset
tKC Reset
Notes:
18. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequncy,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V
= 1.5V, input
DDQ
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC test loads.
OL OH
20. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
21. At any given voltage and temperature t
is less than t
and t
less than t
.
CO
CHZ
CLZ
CHZ
Document #: 38-05498 Rev. *A
Page 11 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Thermal Resistance[22]
165 FBGA
Parameter
Description
Test Conditions
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard test methods and procedures for
16.7
°C/W
(Junction to Ambient) measuring thermal impedence, per EIA/JESD51.
ΘJC
Thermal Resistance
2.5
°C/W
(Junction to Case)
Capacitance[22]
Parameter
Description
Input Capacitance
Clock Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
5
6
7
pF
pF
pF
V
DD = 1.8V
DDQ = 1.5V
CCLK
CO
V
AC Test Loads and Waveforms
V
REF = 0.75V
0.75V
VREF
OUTPUT
VREF
0.75V
R = 50Ω
[14]
ALL INPUT PULSES
Z = 50Ω
0
OUTPUT
Device
1.25V
Device
Under
Test
R = 50Ω
L
0.75V
0.25V
5 pF
Under
ZQ
V
REF = 0.75V
Slew Rate = 2V / ns
ZQ
Test
RQ =
RQ =
250 Ω
250Ω
Including jig
and scope
(a)
(b)
Note:
22. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05498 Rev. *A
Page 12 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Switching Waveforms[23,24,25]
Read/Write/Deselect Sequence
NOP
1
READ
WRITE
READ
4
WRITE
5
NOP
7
2
3
6
K
t
t
t
t
KHKH
KH
KL
CYC
K
RPS
t
t
t
t
SC
HC
SC
HC
WPS
A
A0
A1
A2
A3
t
t
HD
HD
t
t
HA
SA
t
t
SD
SD
D
Q
D30
Q20
D31
Q21
D32
Q22
D33
Q23
D10
Q00
D11
D12
D13
Q03
Qx2
Qx3
Q01
t
Q02
t
CO
DOH
t
CHZ
t
KHCH
t
t
t
CQD
CLZ
CO
t
t
DOH
CQDOH
C
t
t
t
t
KL
KHCH
CYC
KH
t
KHKH
C
t
CCQO
CQOH
t
CQ
t
t
CCQO
CQOH
CQ
DON’T CARE
UNDEFIN
Notes:
23. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e A0+1.
24. Output are disabled (High-Z) one clock cycle after a NOP
25. In this example , if address A2=A1,then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document #: 38-05498 Rev. *A
Page 13 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port–Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document #: 38-05498 Rev. *A
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CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
SAMPLE Z
BYPASS
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
SAMPLE / PRELOAD is a 1149.1 mandatory instruction.
When the SAMPLE / PRELOAD instructions are loaded into
the instruction register and the TAP controller is in the Cap-
ture-DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the
boundary scan register.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the "extest output bus tristate", is
latched into the preload register during the "Update-DR" state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, duringthe"Shift-DR"state. During"Update-DR", thevalue
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
"Test-Logic-Reset" state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05498 Rev. *A
Page 15 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
TAP Controller State Diagram[26]
TEST-LOGIC
RESET
1
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
SELECT
0
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
26. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05498 Rev. *A
Page 16 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
TDI
Selection
Circuitry
2
1
0
0
0
TDO
Circuitry
Instruction Register
29
31 30
.
.
2
1
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[11,14,27]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
IOH = −2.0 mA
IOH = −100 µA
IOL = 2.0 mA
Min.
1.4
1.6
Max.
Unit
V
V
V
V
V
V
µA
0.4
0.2
VDD + 0.3
0.35VDD
5
IOL = 100 µA
0.65VDD
–0.3
VIL
IX
Input LOW Voltage
Input and Output Load Current
GND ≤ VI ≤ VDD
–5
TAP AC Switching Characteristics Over the Operating Range [28,29]
Parameter
tTCYC
tTF
tTH
Description
Min.
100
Max.
Unit
ns
MHz
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
10
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
tTDIS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
10
10
10
ns
ns
ns
tCH
Notes:
27. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
28. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
29. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document #: 38-05498 Rev. *A
Page 17 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range [28,29]
Parameter
Output Times
tTDOV
Description
Min.
Max.
Unit
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
tTDOX
0
TAP Timing and Test Conditions[29]
0.9V
ALL INPUT PULSES
0.9V
1.8V
50Ω
0V
TDO
Z = 50Ω
0
C = 20 pF
L
GND
tTL
tTH
(a)
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
Value
Instruction Field
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
Description
Revision Number (31:29)
000
000
000
Version number.
Cypress Device ID (28:12) 11010011011000101 11010011011010101 11010011011100101 Defines the type of SRAM.
Cypress JEDEC ID (11:1)
00000110100
00000110100
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
1
Indicates the presence of an ID
register.
Document #: 38-05498 Rev. *A
Page 18 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Scan Register Sizes
Register Name
Instruction
Bit Size
3
Bypass
1
ID
32
107
Boundary Scan
Instruction Codes
Instruction
Code
Description
EXTEST
IDCODE
000
001
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and places
the register between TDI and TDO. This operation does
not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the
boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High-Z state.
RESERVED
SAMPLE/PRELOAD
011
100
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the
boundary scan register between TDI and TDO. Does not
affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This
operation does not affect SRAM operation.
Boundary Scan Order
Boundary Scan Order (continued)
Bit #
0
1
2
3
4
5
6
Bump ID
6R
Bit #
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Bump ID
10K
9J
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
9M
9K
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
10D
9E
10C
11D
9C
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
9N
11L
11M
9L
10L
11K
9D
11B
11C
Document #: 38-05498 Rev. *A
Page 19 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Boundary Scan Order (continued)
Boundary Scan Order (continued)
Bit #
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Bump ID
Bit #
88
89
90
91
92
93
94
95
96
97
98
Bump ID
9B
10B
11A
Internal
9A
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
99
100
101
102
103
104
105
106
3F
1G
1F
3G
2G
1J
2J
3K
3J
2K
Document #: 38-05498 Rev. *A
Page 20 of 22
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Ordering Information
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
Package Type
13 x 15 x 1.4 mm FBGA
250
CY7C1311AV18-250BZC
CY7C1313AV18-250BZC
CY7C1315AV18-250BZC
CY7C1311AV18-200BZC
CY7C1313AV18-200BZC
CY7C1315AV18-200BZC
CY7C1311AV18-167BZC
CY7C1313AV18-167BZC
CY7C1315AV18-167BZC
BB165D
Commercial
Commercial
Commercial
200
167
BB165D
BB165D
13 x 15 x 1.4 mm FBGA
13 x 15 x 1.4 mm FBGA
Package Diagram
165 FBGA 13 x 15 x 1.40 mm BB165D
51-85180-**
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT,NEC, and Samsung
technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05498 Rev. *A
Page 21 of 22
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
PRELIMINARY
Document History Page
Document Title: CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 18-Mb QDR™-II SRAM 4-Word Burst Architecture
Document Number: 38-05498
ISSUE
DATE
see ECN
ORIG. OF
REV.
**
*A
ECN NO.
208405
230396
CHANGE DESCRIPTION OF CHANGE
DIM
VBL
New Data Sheet
Upload datasheet to the internet
see ECN
Document #: 38-05498 Rev. *A
Page 22 of 22
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