CY7C1312BV18-167BZI [CYPRESS]
18-Mbit QDR⑩-II SRAM 2 Word Burst Architecture; 18兆位QDR⑩ - II SRAM的2字突发架构
| 型号： | CY7C1312BV18-167BZI |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit QDR⑩-II SRAM 2 Word Burst Architecture |
| 文件： | 总28页 (文件大小：1075K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
18-Mbit QDR™-II SRAM 2 Word
Burst Architecture
Features
Functional Description
■ Separate Independent read and write data ports
❐ Supports concurrent transactions
■ 250 MHz clock for high bandwidth
■ 2 Word Burst on all accesses
■ DoubleDataRate(DDR)interfacesonbothreadandwriteports
(data transferred at 500 MHz) @ 250 MHz
The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and
CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports to access the memory array. The
read port has dedicated Data Outputs to support read operations
and the Write Port has dedicated Data Inputs to support write
operations. QDR-II architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common IO devices. Access to each
port is accomplished through a common address bus. The read
address is latched on the rising edge of the K clock and the write
address is latched on the rising edge of the K clock. Accesses to
the QDR-II read and write ports are completely independent of
one another. To maximize data throughput, both read and write
ports are equipped with Double Data Rate (DDR) interfaces.
Each address location is associated with two 8-bit words
(CY7C1310BV18), 9-bit words (CY7C1910BV18), 18-bit words
(CY7C1312BV18), or 36-bit words (CY7C1314BV18) that burst
sequentially into or out of the device. Since data is transferred
into and out of the device on every rising edge of both input
clocks (K and K and C and C), maximize the memory bandwidth
while simplifying system design by eliminating bus
“turn-arounds.”
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate Port Selects for depth expansion
■ Synchronous internally self-timed writes
■ Available in x 8, x 9, x 18, and x 36 configurations
■ Full data coherency, providing most current data
Depth expansion is accomplished with Port Selects for each port.
Port selects enable each port to operate independently.
■ Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD
■ Available in 165 ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non-Pb-free packages
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310BV18 – 2M x 8
CY7C1910BV18 – 2M x 9
CY7C1312BV18 – 1M x 18
CY7C1314BV18 – 512K x 36
Selection Guide
250 MHz
250
200 MHz
200
167 MHz
167
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
600
550
500
Cypress Semiconductor Corporation
Document #: 38-05619 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 15, 2007
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Logic Block Diagram (CY7C1310BV18)
8
D
[7:0]
Write
Reg
Write
Reg
20
Address
Register
A
(19:0)
20
Address
Register
A
(19:0)
RPS
K
Control
Logic
CLK
Gen.
K
C
C
DOFF
Read Data Reg.
CQ
CQ
16
V
8
REF
8
8
Reg.
Reg.
Reg.
Control
Logic
WPS
NWS
8
8
Q
[7:0]
[1:0]
QVLD
Logic Block Diagram (CY7C1910BV18)
9
D
[8:0]
Write
Reg
Write
Reg
20
Address
Register
A
(19:0)
20
Address
Register
A
(19:0)
RPS
K
Control
Logic
CLK
Gen.
K
C
C
DOFF
Read Data Reg.
CQ
CQ
18
V
9
REF
9
9
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
9
9
Q
[8:0]
[0]
QVLD
Document #: 38-05619 Rev. *E
Page 2 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Logic Block Diagram (CY7C1312BV18)
18
D
[17:0]
Write
Reg
Write
Reg
19
Address
Register
A
(18:0)
19
Address
Register
A
(18:0)
RPS
K
Control
Logic
CLK
Gen.
K
C
C
DOFF
Read Data Reg.
CQ
CQ
36
18
V
REF
18
18
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
18
18
Q
[17:0]
[1:0]
QVLD
Logic Block Diagram (CY7C1314BV18)
36
D
[35:0]
Write
Reg
Write
Reg
18
Address
Register
A
(17:0)
18
Address
Register
A
(17:0)
RPS
K
Control
Logic
CLK
Gen.
K
C
C
DOFF
Read Data Reg.
CQ
CQ
72
36
V
REF
36
36
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
36
36
Q
[35:0]
[3:0]
QVLD
Document #: 38-05619 Rev. *E
Page 3 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Pin Configurations
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1310BV18 (2M x 8)
2
3
8
9
10
11
4
5
6
7
1
NC/72M
CQ
NC
NC
NC
NC
NC
NC
A
WPS
A
NWS1
K
NC/144M
NWS0
A
RPS
A
A
NC/36M
NC
CQ
Q3
A
B
NC
NC
D4
NC
NC/288M
NC
K
A
NC
NC
VSS
VSS
A
VSS
VSS
NC
NC
NC
D3
NC
Q2
C
D
VSS
VSS
VSS
NC
NC
NC
D5
Q4
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D2
NC
E
F
VDD
VDD
VDD
VDD
VDD
VSS
NC
NC
ZQ
D1
NC
Q0
Q5
NC
NC
G
H
J
VREF
NC
NC
Q6
VDDQ
NC
VDDQ
NC
VREF
Q1
DOFF
NC
NC
NC
NC
NC
NC
K
L
D6
NC
NC
NC
NC
NC
NC
D7
NC
NC
NC
Q7
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
D0
NC
NC
M
N
P
C
A
A
A
A
A
A
A
A
A
TDO
TCK
A
TMS
TDI
R
C
CY7C1910BV18 (2M x 9)
1
2
NC/72M
NC
3
4
WPS
A
5
NC
6
K
7
8
9
10
NC/36M
NC
11
CQ
Q4
D4
NC
CQ
NC
NC
NC
NC
NC
NC
A
NC/144M RPS
A
A
B
C
D
NC
NC
NC
NC/288M
A
K
BWS0
A
A
NC
NC
NC
NC
VSS
VSS
A
VSS
VSS
NC
D5
VSS
VSS
VSS
NC
NC
NC
D6
Q5
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D3
NC
Q3
NC
NC
ZQ
D2
NC
Q1
E
F
Q6
NC
NC
G
H
J
VREF
NC
NC
Q7
VDDQ
NC
VDDQ
NC
VREF
Q2
DOFF
NC
NC
NC
NC
NC
NC
NC
NC
NC
K
L
D7
NC
NC
NC
D8
NC
NC
NC
Q8
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
D0
D1
NC
Q0
M
N
P
C
A
A
A
A
A
A
A
A
A
TDO
TCK
A
TMS
TDI
R
C
Document #: 38-05619 Rev. *E
Page 4 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Pin Configurations (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1312BV18 (1M x 18)
1
2
3
4
5
BWS1
NC
6
K
7
NC/288M
BWS0
A
8
RPS
A
9
10
NC/72M
NC
11
CQ
Q8
D8
D7
Q6
CQ
NC
NC
NC
NC
NC
NC
NC/144M NC/36M
WPS
A
A
A
B
C
D
Q9
NC
D9
NC
NC
NC
K
D10
Q10
VSS
VSS
A
A
VSS
VSS
Q7
D11
VSS
VSS
VSS
NC
NC
Q12
D13
VREF
NC
Q11
D12
Q13
VDDQ
D14
Q14
D15
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D6
NC
NC
VREF
Q4
E
F
VDD
VDD
VDD
VDD
VDD
VSS
Q5
D5
ZQ
D4
Q3
Q2
NC
G
H
J
VDDQ
NC
DOFF
NC
NC
NC
NC
NC
D3
K
L
Q15
NC
NC
NC
NC
NC
NC
D17
NC
D16
Q16
Q17
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
Q1
NC
D0
D2
D1
Q0
M
N
P
C
A
A
A
A
A
A
A
A
A
TDO
TCK
A
TMS
TDI
R
C
CY7C1314BV18 (512K x 36)
1
2
3
5
6
7
8
9
10
11
CQ
Q8
D8
D7
Q6
4
WPS
A
CQ
Q27
D27
D28
NC/288M NC/72M
BWS2
BWS3
A
K
BWS1
BWS0
A
RPS
A
NC/36M NC/144M
A
B
C
D
Q18
Q28
D20
D18
D19
Q19
D17
D16
Q16
Q17
Q7
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D15
Q29
Q30
D30
D29
Q21
D22
VREF
Q31
D32
Q24
Q20
D21
Q22
VDDQ
D23
Q23
D24
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
Q15
D14
D6
Q14
D13
VREF
Q4
E
F
VDD
VDD
VDD
VDD
VDD
VSS
Q5
D5
ZQ
D4
Q3
Q2
Q13
VDDQ
D12
G
H
J
DOFF
D31
Q32
Q33
D33
D34
Q35
Q12
D11
D3
K
L
Q11
Q34
D26
D35
D25
Q25
Q26
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
D10
Q10
Q9
Q1
D9
D0
D2
D1
Q0
M
N
P
A
C
A
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
Document #: 38-05619 Rev. *E
Page 5 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Pin Definitions
Pin Name
IO
Pin Description
Data Input Signals, sampled on the rising edge of K and K clocks during valid write operations.
D[x:0]
Input-
Synchronous CY7C1310BV18 - D[7:0]
CY7C1910BV18 - D[8:0]
CY7C1312BV18 - D[17:0]
CY7C1314BV18 - D[35:0]
WPS
Input-
Write Port Select, Active LOW. Sampled on the rising edge of the K clock. When asserted active,
Synchronous a write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores
D[x:0]
.
Nibble Write Select 0, 1 − Active LOW. (CY7C1310BV18 Only) Sampled on the rising edge of the
K and K clocks during write operations. Used to select which nibble is written into the device during
the current portion of the write operations. Nibbles that are not written remain unaltered. NWS0
controls D[3:0] and NWS1 controls D[7:4]. All Nibble Write Selects are sampled on the same edge as
the data. Deselecting a Nibble Write Select ignores the corresponding nibble of data and is not written
into the device.
NWS0,NWS1
Input-
Byte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and K clocks
BWS0, BWS1,
BWS2, BWS3
Synchronous during write operations. Used to select the byte that is written into the device during the current portion
of the write operations. Bytes that are not written remain unaltered.
CY7C1910BV18 − BWS0 controls D[8:0]
CY7C1312BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9]
.
CY7C1314BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and is not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks
Synchronous during active read and write operations. These address inputs are multiplexed for both read and write
operations. Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1310BV18,
2M x 9 (2 arrays each of 1M x 9) for CY7C1910BV18, 1M x 18 (2 arrays each of 512K x 18) for
CY7C1312BV18, and 512K x 36 (2 arrays each of 256K x 36) for CY7C1314BV18. Therefore, only
20 address inputs are needed to access the entire memory array of CY7C1310BV18 and
CY7C1910BV18, 19 address inputs for CY7C1312BV18, and 18 address inputs for CY7C1314BV18.
These inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Data Output signals. These pins drive out the requested data during a read operation. Valid data is
Synchronous driven out on the rising edge of both the C and C clocks during read operations or K and K when in
single clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1310BV18 − Q[7:0]
CY7C1910BV18 − Q[8:0]
CY7C1312BV18 − Q[17:0]
CY7C1314BV18 − Q[35:0]
RPS
Input-
Read Port Select, Active LOW. Sampled on the rising edge of Positive Input Clock (K). When active,
Synchronous a read operation is initiated. Deasserting deselects the read port. When deselected, the pending
access is allowed to complete and the output drivers are automatically tri-stated following the next
rising edge of the C clock. Each read access consists of a burst of two sequential transfers.
C
C
K
Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data
from the device. C and C are used together to deskew the flight times of various devices on the board
back to the controller. For more information see “Application Example” on page 9.
Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data
from the device. C and C are used together to deskew the flight times of various devices on the board
back to the controller. For more information see “Application Example” on page 9.
Input-Clock Positive Input Clock Input. The rising edge of K captures synchronous inputs to the device and
drives out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge
of K.
Document #: 38-05619 Rev. *E
Page 6 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Pin Definitions (continued)
Pin Name
IO
Pin Description
K
Input-Clock Negative Input Clock Input. K captures synchronous inputs presented to the device and drives out
data through Q[x:0] when in single clock mode.
CQ
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K.
The timings for the echo clocks are shown in the “Switching Characteristics” on page 22.
CQ
ZQ
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K.
“Switching Characteristics” on page 22
The timings for the echo clocks are shown in the
.
Input
Output Impedance Matching Input. This input tunes the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternately, this pin is connected directly to VDDQ, which enables
the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operation is different from those listed in this datasheet.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG
TCK
TCK pin for JTAG
TDI
TDI pin for JTAG
TMS
TMS pin for JTAG
NC
Not connected to the die. It is tied to any voltage level
Not connected to the die. It is tied to any voltage level
Not connected to the die. It is tied to any voltage level
Not connected to the die. It is tied to any voltage level
Not connected to the die. It is tied to any voltage level
Reference Voltage Input. Static input is used to set the reference level for HSTL inputs, Outputs,
NC/36M
NC/72M
NC/144M
NC/288M
VREF
N/A
N/A
N/A
N/A
Input-
Reference and AC measurement points
VDD
VSS
Power Supply Power supply inputs to the core of the device
Ground
Ground for the device
VDDQ
Power Supply Power supply inputs for the outputs of the device
Document #: 38-05619 Rev. *E
Page 7 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
BWS[1:0] are both asserted active. The 36-bits of data is then
written into the memory array at the specified location. When
deselected, the write port ignores all inputs after the pending
Write operations are completed.
Functional Overview
The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and
CY7C1314BV18 are synchronous pipelined Burst SRAMs
equipped with both a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
The QDR-II completely eliminates the need to “turn-around” the
data bus by having separate read and write ports. This avoids
any possible data contention, and thereby simpliflies system
design. Each access consists of two 8-bit data transfers in the
case of CY7C1310BV18, two 9-bit data transfers in the case of
CY7C1910BV18, two 18-bit data transfers in the case of
CY7C1312BV18, and two 36-bit data transfers in the case of
CY7C1314BV18, in one clock cycle.
Byte Write Operations
Byte Write operations are supported by the CY7C1312BV18. A
Write operation is initiated as described in the Write Operations
section above. The bytes that are written are determined by
BWS0 and BWS1, which are sampled with each 18-bit data word.
You can latch and write the data presented into the device by
asserting the appropriate Byte Write Select input during the data
portion of a Write. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are refer-
enced from the rising edge of the input clocks (K and K) and all
output timings are referenced to the rising edge of output clocks
(C and C or K and K when in single clock mode).
The CY7C1312BV18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, the user must tie C
and C HIGH at power on. This function is a strap option and not
alterable during device operation.
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C or K and K when in
single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
Concurrent Transactions
The Read and Write ports on the CY7C1312BV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user can
Read or Write to any location, regardless of the transaction on
the other port. Also, reads and writes can be started in the same
clock cycle. If the ports access the same location at the same
time, the SRAM delivers the most recent information associated
with the specified address location. This includes forwarding
data from a Write cycle that was initiated on the previous K clock
rise.
CY7C1312BV18 is described in the following sections. The
same basic descriptions apply to CY7C1310BV18
CY7C1910BV18 and CY7C1314BV18.
Read Operations
The CY7C1312BV18 is organized internally as 2 arrays of 512K
x 18. Accesses are completed in a burst of two sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the Positive Input Clock (K). The
address is latched on the rising edge of the K Clock. The address
presented to address inputs is stored in the read address
register. Following the next K clock rise, the corresponding
lowest order 18-bit word of data is driven onto the Q[17:0] using
C as the output timing reference. On the subsequent rising edge
of C, the next 18-bit data word is driven onto the Q[17:0]. The
requested data is valid 0.45 ns from the rising edge of the output
clock (C and C or K and K when in single clock mode).
Depth Expansion
The CY7C1312BV18 has a Port Select input for each port. This
enables easy depth expansion. Both Port Selects are sampled
on the rising edge of the Positive Input Clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed prior to the device being deselected.
Programmable Impedance
Synchronous internal circuitry automatically tri-states the outputs
following the next rising edge of the Output Clocks (C/C). This
enables a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V.The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the same K clock
rise, the data presented to D[17:0] is latched and stored into the
lower 18-bit Write Data register provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the Negative
Input Clock (K), the address is latched and the information
presented to D[17:0] is stored into the Write Data register provided
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data capture
on high speed systems. Two echo clocks are generated by the
Document #: 38-05619 Rev. *E
Page 8 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
QDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock (C/C) of the QDR-II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timings for the echo clocks are shown in
the Switching Characteristics.
also be reset by slowing or stopping the input clock K and K for
a minimum of 30 ns. However, it is not necessary to specifically
reset the DLL set to lock the DLL to the desired frequency. The
DLL automatically locks 1024 clock cycles after a stable clock is
presented. The DLL may be disabled by applying ground to the
DOFF pin. For information refer to the application note ‘DLL
Considerations in QDRII/DDRII/QDRII+/DDRII+’.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 80 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
Application Example
Figure 1 shows the use of QDR-II in an application.
Figure 1. Application Example
R = 250οηµσ
SRAM #1
R
SRAM #4
R = 250οηµσ
ZQ
CQ/CQ#
Q
ZQ
CQ/CQ#
Q
R W
B
W
S
W
P
B
W
S
Vt
P
S
#
P
S
#
P
S
#
D
A
D
A
S
#
R
C
C#
K
K#
C C# K
K#
#
#
DATA IN
DATA OUT
Address
Vt
Vt
R
RPS#
BUS
MASTER
(CPU
or
ASIC)
WPS#
BWS#
CLKIN/CLKIN#
Source K
Source K#
Delayed K
Delayed K#
R
R = 50οηµσ
Vt = Vddq/2
Document #: 38-05619 Rev. *E
Page 9 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Truth Table
The truth table for the CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and CY7C1314BV18 follows.[1, 2, 3, 4, 5, 6]
Operation
K
RPS WPS
DQ
DQ
Write Cycle:
L-H
X
L
D(A + 0) at K(t) ↑
D(A + 1) at K(t) ↑
Load address on the rising edge of K clock; input write data
on K and K rising edges.
Read Cycle:
L-H
L
X
Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑
Load address on the rising edge of K clock; wait one and a
half cycle; read data on C and C rising edges.
NOP: No Operation
L-H
H
X
H
X
D = X
Q = High Z
D = X
Q = High Z
Standby: Clock Stopped
Stopped
Previous State
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1314BV18 and CY7C1910BV18 follows. [1, 7]
BWS0/ BWS1/
K
K
Comments
During the data portion of a write sequence:
NWS0 NWS1
L
L
L-H
–
CY7C1310BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1312BV18 − both bytes (D[17:0]) are written into the device.
L
L
–
L-H
–
L-H During the data portion of a write sequence:
CY7C1310BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1312BV18 − both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the data portion of a write sequence:
CY7C1310BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] remains unaltered,
CY7C1312BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] remains unaltered.
L
L-H During the data portion of a write sequence:
CY7C1310BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] remains unaltered,
CY7C1312BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] remains unaltered.
H
H
L-H
–
–
During the data portion of a write sequence:
CY7C1310BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] remains unaltered,
CY7C1312BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] remains unaltered.
L
L-H During the data portion of a write sequence:
CY7C1310BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] remains unaltered,
CY7C1312BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] remains unaltered.
H
H
H
H
L-H
–
–
No data is written into the devices during this portion of a write operation.
L-H No data is written into the devices during this portion of a write operation.
Notes
1. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge.
2. Device powers up deselected and the outputs in a tri-state condition.
3. “A” represents address location latched by the devices when transaction was initiated. A + 0 and A + 1 represent the internal address sequence in the burst.
4. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
5. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
6. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
7. Assumes a write cycle was initiated per the Write Port Cycle Description Truth Table. NWS , NWS , BWS , BWS , BWS and BWS can be altered on different portions
0
1
0
1
2
3
of a write cycle, as long as the setup and hold requirements are achieved.
Document #: 38-05619 Rev. *E
Page 10 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
The write cycle description table for CY7C1910BV18 follows.[1, 7]
BWS0
K
K
Comments
L
L-H
–
During the data portion of a Write sequence:
CY7C1910BV18 − the single byte (D[8:0]) is written into the device
L
–
L-H
During the data portion of a Write sequence:
CY7C1910BV18 − the single byte (D[8:0]) is written into the device,
H
H
L-H
–
–
No data is written into the devices during this portion of a Write operation.
No data is written into the devices during this portion of a Write operation.
L-H
The write cycle description table for CY7C1314BV18 follows. [1, 7]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L-H
-
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
-
L-H
-
L-H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
-
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L-H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L-H
-
-
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L
L-H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
H
H
H
L-H
-
-
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L
L-H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L-H
-
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L-H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L-H
-
-
No data is written into the device during this portion of a write operation.
L-H No data is written into the device during this portion of a write operation.
Document #: 38-05619 Rev. *E
Page 11 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins as shown in TAP Controller Block Diagram on
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull up resistor. TDO should be
left unconnected. Upon power up, the device comes up in a reset
state and does not interfere with the operation of the device.
When the TAP controller is in the Capture IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single bit register that can be placed between TDI
and TDO pins.This enables shifting of data through the SRAM
with minimal delay.The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
Test Mode Select
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this pin unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can
be used to capture the contents of the Input and Output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 14. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order on page 18 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data-Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 17.
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 17.The
output changes on the falling edge of TCK. TDO is connected to
the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RESERVED
and should not be used. The other five instructions are described
in detail below.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins.Once it is
shifted in, the TAP controller is moved into the Update-IR state
to execute the instruction.
Data is scanned into and out of the SRAM test circuitry by
registers that are connected between the TDI and TDO pins.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
Document #: 38-05619 Rev. *E
Page 12 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
IDCODE
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
A vendor specific 32-bit code is loaded into the instruction
register by the IDCODE instruction. It also places the instruction
register between the TDI and TDO pins and the IDCODE is
shifted out of the device when the TAP controller enters the
Shift-DR state.The IDCODE instruction is loaded into the
instruction register upon power up or whenever the TAP
controller is given a test logic reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction is connected between the TDI and
TDO pins by the boundary scan register when the TAP controller
is in a Shift-DR state. The SAMPLE Z command puts the output
bus into a High Z state until the next command is given during
the “Update IR” state.
EXTEST
The EXTEST instruction drives out the preloaded data through
the system output pins.This instruction also selects the boundary
scan register that is connected for serial access between the TDI
and TDO in the shift-DR controller state.
SAMPLE/PRELOAD
EXTEST OUTPUT BUS TRI-STATE
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is pre-set LOW
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
An initial data pattern is placed by PRELOAD at the latched
parallel outputs of the boundary scan register cells prior to the
selection of another boundary scan test operation.
Document #: 38-05619 Rev. *E
Page 13 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
TAP Controller State Diagram
The tap controller state diagram for the CY7C1310BV18, CY7C1910BV18, CY7C1312BV18 and CY7C1314BV18 follows.[8]
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note
8. The 0/1 next to each state represents the value at TMS at the rising edge of TCK
Document #: 38-05619 Rev. *E
Page 14 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
1
0
TDO
TDI
Instruction Register
29
31 30
.
.
2
0
0
Identification Register
106
.
.
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the operating range [9, 10, 11]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min
1.4
1.6
Max
Unit
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
V
0.4
0.2
V
V
0.65VDD VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.35VDD
5
V
IX
Input and OutputLoad Current
GND ≤ VI ≤ VDD
−5
µA
Notes
9. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
10. Overshoot: V (AC) < V +0.85V (Pulse width less than t /2), Undershoot: V (AC) > –1.5V (Pulse width less than t /2).
IH
DDQ
CYC
IL
CYC
11. All voltage referenced to Ground.
Document #: 38-05619 Rev. *E
Page 15 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
TAP AC Switching Characteristics
Over the operating range [12, 13]
Parameter
Description
Min
Max
Unit
ns
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
tTF
20
MHz
ns
tTH
20
20
tTL
TCK Clock LOW
ns
Setup Times
tTMSS
tTDIS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
0
TAP Timing and Test Conditions
The tap timing and test conditions for CY7C1310BV18, CY7C1910BV18, CY7C1312BV18 and CY7C1314BV18 follows.[12]
0.9V
ALL INPUT PULSES
50Ω
1.8V
TDO
0.9V
0V
Z = 50Ω
0
C = 20 pF
L
t
t
TL
TH
GND
(a)
Test Clock
TCK
t
TCYC
t
TMSH
t
TMSS
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data In
TDI
Test Data Out
TDO
t
TDOV
t
TDOX
Notes
12. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
13. t and t refer to the set up and hold time requirements of latching data from the boundary scan register
CS
CH
Document #: 38-05619 Rev. *E
Page 16 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Identification Register Definitions
Value
Instruction Field
Description
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
000
Revision Number
(31:29)
000
000
000
Version number.
Cypress Device ID 11010011010000101
(28:12)
11010011010001101
00000110100
11010011010010101
00000110100
11010011010100101 Defines the type of
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
00000110100
Unique identifi-
cation of SRAM
vendor.
ID Register
Presence (0)
1
1
1
1
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
1
Bypass
ID
32
107
Boundary Scan Cells
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the Input or Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input or Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input or Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Document #: 38-05619 Rev. *E
Page 17 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Bump ID
11H
10G
9G
Bit #
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Bump ID
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
81
Bump ID
3G
2G
1J
1
6P
82
2
6N
83
3
7P
11F
11G
9F
84
2J
4
7N
85
3K
3J
5
7R
86
6
8R
10F
11E
10E
10D
9E
87
2K
1K
2L
7
8P
88
8
9R
89
9
11P
10P
10N
9P
90
3L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
91
1M
1L
10C
11D
9C
92
93
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
10M
11N
9M
94
9D
95
11B
11C
9B
96
9N
97
11L
11M
9L
98
10B
11A
Internal
9A
99
100
101
102
103
104
105
106
10L
11K
10K
9J
8B
7C
9K
6C
3F
10J
11J
8A
1G
1F
7A
Document #: 38-05619 Rev. *E
Page 18 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
❐ Apply VDDQ before VREF or at the same time as VREF
Power Up Sequence in QDR-II SRAM
■ After the power and clock (K, K, C, C) are stable take DOFF
HIGH
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
Power Up, when the DOFF is tied HIGH, the DLL gets locked
after 1024 cycles of stable clock. It is recommended that the
DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
■ The additional 1024 cycles of clocks are required for the DLL
to lock
DLL Constraints
Power Up Sequence
■ DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as tKC
■ Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
Var
❐ Apply VDD before VDDQ
■ The DLL functions at frequencies down to 80 MHz
■ If the input clock is unstable and the DLL is enabled, then the
DLL may lock to an incorrect frequency, causing unstable
SRAM behavior
Power Up Waveforms
K
K
Unstable Clock
> 1024 Stable clock
Stable)
DDQ
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
VDDQ
V
VDD
DD
DDQ
Fix High (or tied to V
DDQ
)
DOFF
Document #: 38-05619 Rev. *E
Page 19 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
DC Input Voltage[10] .............................. –0.5V to VDD + 0.3V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........–0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
Ambient
Temperature (TA)
[16]
[16]
Range
VDD
VDDQ
Commercial
Industrial
0°C to +70°C
1.8 ± 0.1 V
1.4V to
VDD
DC Voltage Applied to Outputs
in High Z State.....................................–0.5V to VDDQ + 0.3V
–40°C to +85°C
Electrical Characteristics
Over the operating range [11, 16]
DC Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
1.7
Typ.
Max
Unit
1.8
1.5
1.9
VDD
V
V
VDDQ
VOH
1.4
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[10]
Input LOW Voltage[10]
Input Leakage Current
Output Leakage Current
Input Reference Voltage[17]
VDD Operating Supply
Note 14
Note 15
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
V
VOL
V
VOH(LOW)
VOL(LOW)
VIH
IOH = −0.1 mA, Nominal Impedance
V
IOL = 0.1 mA, Nominal Impedance
0.2
V
VREF + 0.1
–0.3
VDDQ+0.3
VREF – 0.1
5
V
VIL
V
IX
GND ≤ VI ≤ VDDQ
−5
µA
µA
V
IOZ
GND ≤ VI ≤ VDDQ, Output Disabled
Typical Value = 0.75V
−5
5
VREF
IDD
0.68
0.75
0.95
500
550
600
240
260
280
VDD = Max., IOUT = 0 mA, f 167 MHz
mA
mA
mA
mA
mA
mA
= fMAX = 1/tCYC
200 MHz
250 MHz
ISB1
Automatic Power down
Current
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL f = fMAX = 1/tCYC,
Inputs Static
167 MHz
200 MHz
250 MHz
AC Input Requirements Over the Operating Range
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
VREF + 0.2
–
Typ
–
Max
–
Unit
V
VIH
VIL
–
VREF – 0.2
V
Notes
14. Output are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
OH
DDQ
15. Output are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
OL
DDQ
16. Power up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
DD
IH
DD
DDQ
17. V
(Min) = 0.68V or 0.46V
, whichever is larger, V
(Max) = 0.95V or 0.54V
, whichever is smaller.
REF
DDQ
REF
DDQ
Document #: 38-05619 Rev. *E
Page 20 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Test Conditions
Max
Unit
pF
TA = 25°C, f = 1 MHz,
5
6
7
V
DD = 1.8V
CCLK
Clock Input Capacitance
Output Capacitance
pF
VDDQ = 1.5V
CO
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
28.51
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
5.91
°C/W
AC Test Loads and Waveforms
V
REF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
[18]
ALL INPUT PULSES
Z = 50Ω
0
OUTPUT
1.25V
Device
R = 50Ω
L
0.75V
Under
Device
Under
0.25V
Test
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
(a)
(b)
Note
18. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V
= 1.5V, input pulse
DDQ
levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads.
OL OH
Document #: 38-05619 Rev. *E
Page 21 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Switching Characteristics
Over the operating range [18, 19]
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
Unit
Min Max Min Max Min Max
tPOWER
tCYC
tKH
tKHKH
tKHKL
tKLKH
tKHKH
VDD(Typical) to the first Access[20]
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
1
1
1
ms
ns
ns
ns
4.0 6.3 5.0 7.9 6.0 7.9
1.6
1.6
–
–
2.0
2.0
–
–
2.4
2.4
–
–
tKL
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
tKHKH
tKHCH
Setup Times
tSA tAVKH
tSC
tKHCH
1.8
–
2.2
–
2.7
–
ns
ns
tKHKH
0.0 1.8 0.0 2.2 0.0 2.7
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
Address Setup to K Clock Rise
0.35
0.35
–
–
0.4
0.4
–
–
0.5
0.5
–
–
ns
ns
tIVKH
Control Setup to K Clock Rise (RPS, WPS)
Double Data Rate Control Setup to Clock (K/K) Rise
(BWS0, BWS1, BWS3, BWS4)
tSCDDR
tIVKH
0.35
0.35
–
–
0.4
0.4
–
–
0.5
0.5
–
–
ns
ns
[21]
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
Hold Times
tHA tKHAX
tHC
0.35
0.35
–
–
0.4
0.4
–
–
0.5
0.5
–
–
ns
ns
Address Hold after K Clock Rise
tKHIX
Control Hold after K Clock Rise (RPS, WPS)
Double Data Rate Control Hold after Clock
(K/K) Rise (BWS0, BWS1, BWS3, BWS4)
tHCDDR
tHD
tKHIX
0.35
0.35
–
–
0.4
0.4
–
–
0.5
0.5
–
–
ns
ns
tKHDX
D[X:0] Hold after Clock (K/K) Rise
Output Times
tCO
tCHQV
–
0.45
–
0.45
–
0.50 ns
C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid
Data Output Hold after Output C/C Clock Rise
(Active to Active)
tDOH
tCHQX
–0.45
–
–
0.45
–
-0.45
–
–
0.45
–
-0.50
–
–
ns
0.50 ns
ns
0.40 ns
ns
0.50 ns
ns
tCCQO
tCQOH
tCQD
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHQZ
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
–0.45
–
–0.45
–
–0.50
–
–
0.30
–
0.35
–
tCQDOH
tCHZ
Echo Clock High to Data Invalid
–0.30
–
–0.35
–
–0.40
–
–
Clock (C/C) Rise to High Z (Active to High Z) [22, 23]
Clock (C/C) Rise to Low Z [22,23]
0.45
–
0.45
–
tCLZ
tCHQX1
–0.45
–0.45
–0.50
–
DLL Timing
tKC Var tKC Var
tKC lock tKC lock
Clock Phase Jitter
–
0.20
–
–
0.20
–
–
0.20 ns
DLL Lock Time (K, C)
K Static to DLL Reset
1024
30
1024
30
1024
30
–
–
cycles
ns
tKC Reset tKC Reset
–
–
Notes
19. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency, it
requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.
20. This part has a voltage regulator internally; t
initiated.
is the time that the power needs is supplied above V minimum initially before a read or write operation can be
DD
POWER
21. For D2 data signal on CY7C1910BV18 device, t is 0.5 ns for 200 MHz, and 250 MHz frequencies.
SD
22. t
, t
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
23. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
Document #: 38-05619 Rev. *E
Page 22 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Switching Waveform
Figure 2 shows the read, write, and deselect sequence.[24, 25, 26]
Figure 2. Read/Write/Deselect Sequence
READ
WRITE
2
READ
3
WRITE
4
WRITE
6
WRITE
8
NOP
READ
NOP
7
1
5
9
10
K
t
t
KHKH
t
t
CYC
KH
KL
K
RPS
t
t
SC
HC
WPS
A
A2
A3
A4
A0
A1
A5
A6
t
t
t
t
SA HA
SA HA
D
Q
D31
t
D10
D11
D30
D50
D51
D60
D61
t
t
t
SD
HD
SD
HD
Q20
CQDOH
Q00
Q01
DOH
Q21
Q40
Q41
t
t
CLZ
t
t
CHZ
t
KHCH
t
t
KL
t
CO
CQD
t
C
C
KH
t
t
KHKH
CYC
t
KHCH
t
CCQO
t
CQOH
t
CQ
CQ
CCQO
t
CQOH
DON’T CARE
UNDEFINED
Notes
24. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
25. Output are disabled (High Z) one clock cycle after a NOP.
26. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document #: 38-05619 Rev. *E
Page 23 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered
Speed
(MHz)
Package
Diagram
Operating
Range
Package Type
Ordering Code
250 CY7C1310BV18-250BZC
CY7C1910BV18-250BZC
CY7C1312BV18-250BZC
CY7C1314BV18-250BZC
CY7C1310BV18-250BZXC
CY7C1910BV18-250BZXC
CY7C1312BV18-250BZXC
CY7C1314BV18-250BZXC
CY7C1310BV18-250BZI
CY7C1910BV18-250BZI
CY7C1312BV18-250BZI
CY7C1314BV18-250BZI
CY7C1310BV18-250BZXI
CY7C1910BV18-250BZXI
CY7C1312BV18-250BZXI
CY7C1314BV18-250BZXI
200 CY7C1310BV18-200BZC
CY7C1910BV18-200BZC
CY7C1312BV18-200BZC
CY7C1314BV18-200BZC
CY7C1310BV18-200BZXC
CY7C1910BV18-200BZXC
CY7C1312BV18-200BZXC
CY7C1314BV18-200BZXC
CY7C1310BV18-200BZI
CY7C1910BV18-200BZI
CY7C1312BV18-200BZI
CY7C1314BV18-200BZI
CY7C1310BV18-200BZXI
CY7C1910BV18-200BZXI
CY7C1312BV18-200BZXI
CY7C1314BV18-200BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Commercial
Industrial
Commercial
Industrial
Document #: 38-05619 Rev. *E
Page 24 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered
Speed
(MHz)
Package
Diagram
Operating
Range
Package Type
Ordering Code
167 CY7C1310BV18-167BZC
CY7C1910BV18-167BZC
CY7C1312BV18-167BZC
CY7C1314BV18-167BZC
CY7C1310BV18-167BZXC
CY7C1910BV18-167BZXC
CY7C1312BV18-167BZXC
CY7C1314BV18-167BZXC
CY7C1310BV18-167BZI
CY7C1910BV18-167BZI
CY7C1312BV18-167BZI
CY7C1314BV18-167BZI
CY7C1310BV18-167BZXI
CY7C1910BV18-167BZXI
CY7C1312BV18-167BZXI
CY7C1314BV18-167BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Commercial
Industrial
Document #: 38-05619 Rev. *E
Page 25 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Package Diagram
Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
-0.06
Ø0.50 (165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
13.00 0.10
B
13.00 0.10
B
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*A
Document #: 38-05619 Rev. *E
Page 26 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document History Page
Document Title: CY7C1310BV18/CY7C1910BV18/CY7C1312BV18/CY7C1314BV18, 18-Mbit QDR™-II SRAM 2 Word Burst
Architecture
Document Number: 38-05619
Orig. of
Change
REV.
ECN No. Issue Date
Description of Change
**
252474
325581
See ECN
See ECN
SYT
New datasheet
*A
SYT
Removed CY7C1910BV18 from the title
Included 300 MHz Speed Bin
Added Industrial Temperature Grade
Replaced TBDs for IDD and ISB1 specifications
Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 28.51°C/W
and ΘJC = 5.91°C/W
Replaced TBDs in the Capacitance Table for the 165 FBGA Package
Changed the package diagram from BB165E (15 x 17 x 1.4 mm) to BB165D
(13 x 15 x 1.4 mm)
Added Pb-Free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
*B
413997
See ECN
NXR
Converted from Preliminary to Final
Added CY7C1910BV18 part number to the title
Removed 300MHz Speed Bin
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed C/C Pin Description in the features section and Pin Description
Corrected Typo in Identification Register Definitions for CY7C1910BV18 on
page# 16
Added power up sequence details and waveforms
Added foot notes #15, 16, and 17 on page# 18
Replaced Three state with Tri-state
Changed the description of IX from Input Load Current to Input Leakage Current
on page# 13
Modified the IDD and ISB values
Modified test condition in Footnote #20 on page# 19 from VDDQ < VDD to
VDDQ < VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*C
*D
423334
472384
See ECN
See ECN
NXR
NXR
Changed the IEEE Standard # 1149.1-1900 to 1149.1-2001
Changed the Minimum Value of tSC and tHC from 0.5ns to 0.35ns for 250 MHz
and 0.6 ns to 0.4 ns for 200 MHz speed bins
Changed the description of tSA from K Clock Rise to Clock (K/K) Rise
Changed the description of tSC andtHC from Clock (K and K) Rise to K Clock Rise
Modified the ZQ Definition from Alternately, this pin is connected directly to VDD
to Alternately, this pin is connected directly to VDDQ
Changed the IEEE Standard # from 1149.1-2001 to 1149.1-1900
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH
,
t
CH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in Tap Switching
Characteristics.
Modified Power Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied from
–10°C to +85°C to –55°C to +125°C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Corrected the typo In the Tap Switching Characteristics.
Updated the Ordering Information Table
Document #: 38-05619 Rev. *E
Page 27 of 28
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document Title: CY7C1310BV18/CY7C1910BV18/CY7C1312BV18/CY7C1314BV18, 18-Mbit QDR™-II SRAM 2 Word Burst
Architecture
Document Number: 38-05619
*E
1274723 See ECN
VKN
Corrected typo in the JTAG ID code for CY7C1910BV18
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05619 Rev. *E
Revised July 15, 2007
Page 28 of 28
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明