CY7C1312V18-200BZC_技术文档

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

18-Mb QDR™-II SRAM Two-word

Burst Architecture

Features

Functional Description

• Separate Independent Read and Write Data Ports

The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V

Synchronous Pipelined SRAMs, equipped with QDR^™-II archi-

tecture. QDR^TM-II architecture consists of two separate ports

to access the memory array. The Read port has dedicated

Data Outputs to support Read operations and the Write Port

has dedicated Data Inputs to support Write operations.

QDR^TM-II architecture has separate data inputs and data

outputs to completely eliminate the need to “turn-around” the

data bus required with common I/O devices. Access to each

port is accomplished through a common address bus. The

Read address is latched on the rising edge of the K clock and

the Write address is latched on the rising edge of the K clock.

Accesses to the QDR^TM-II Read and Write ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with two 8-bit words (CY7C1310V18) or 18-bit

words (CY7C1312V18) or 36-bit words (CY7C1314V18) that

burst sequentially into or out of the device. Since data can be

transferred into and out of the device on every rising edge of

both input clocks (K/K and C/C), memory bandwidth is

maximized while simplifying system design by eliminating bus

“turn-arounds.”

— Supports concurrent transactions

• 167-MHz Clock for High Bandwidth

• Two-word Burst on all accesses

• DoubleDataRate(DDR)interfacesonbothRead&Write

Ports (data transferred at 333 MHz) @ 167MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatches

• Echo clocks (CQ and CQ) simplify data capture in high

speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x18, and x36 configurations

• 1.8V core power supply with HSTL Inputs and Outputs

• 13x15 mm 1.0-mm pitch FBGA package, 165 ball (11x15

matrix)

• Variable drive HSTL output buffers

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

• Extended HSTL output voltage (1.4V–V_DD

• JTAG Interface

)

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C/C (or K/K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

• On-chip Delay Lock Loop (DLL)

Configurations

CY7C1310V18 – 2M x 8

CY7C1312V18 – 1M x 18

CY7C1314V18 – 512K x 36

Logic Block Diagram (CY7C1310V18)

D

[7:0]

8

Write

Reg

Write

Reg

Address

Register

A

(19:0)

20

Address

Register

A

(19:0)

20

RPS

K

Control

Logic

CLK

Gen.

C

Read Data Reg.

16

CQ

8

V

REF

8

Reg.

WPS

BWS

Control

Logic

8

[1:0]

Q

[7:0]

8

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05180 Rev. *A

Revised August 2, 2002

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Logic Block Diagram (CY7C1312V18)

D

[17:0]

18

Write

Reg

Write

Reg

Address

Register

A

(18:0)

19

Address

Register

A

(18:0)

19

RPS

C

K

Control

Logic

CLK

Gen.

Read Data Reg.

36

CQ

C

18

V

REF

18

Reg.

18

WPS

BWS

Control

Logic

18

[1:0]

Q

[17:0]

18

Logic Block Diagram (CY7C1314V18)

D

[35:0]

36

Write

Reg

Write

Reg

Address

Register

A

(17:0)

18

Address

Register

A

(17:0)

18

RPS

K

Control

Logic

CLK

Gen.

C

Read Data Reg.

72

CQ

36

V

REF

36

Reg.

WPS

BWS

Control

Logic

36

[3:0]

36

Q

[35:0]

36

Selection Guide^[1]

200 MHz

200

167 MHz

167

133 MHz

133

Unit

MHz

mA

Maximum Operating Frequency

Maximum Operating Current

TBD

Note:

1. Shaded cells indicate advanced information.

Document #: 38-05180 Rev. *A

Page 2 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Pin Configurations

1

CY7C1310V18 (2M x 8) - 11 x 15 BGA

2

3

A

4

WPS

5

6

K

7

NC

8

RPS

9

A

10

V_SS/36M

11

CQ

Q3

D3

NC

CQ

NC

V_SS/72M

BWS₁

A

B

C

D

NC

D4

NC

A

NC

A

K

A

BWS₀

A

NC

V_SS

NC

D5

Q4

NC

V_DDQ

V_SS

V_DD

V_SS

VSS

V_DDQ

NC

D2

NC

Q2

E

F

NC

V_DD

V_SS

NC

ZQ

D1

NC

Q0

Q5

NC

G

H

J

DOFF

NC

V_REF

NC

Q6

V_DDQ

NC

V_DDQ

NC

V_REF

Q1

NC

K

L

NC

D6

NC

D7

NC

Q7

V_SS

A

V_SS

A

V_SS

A

V_SS

NC

D0

NC

M

N

P

A

C

A

TDO

TCK

A

C

A

TMS

TDI

R

CY7C1312V18 (1M x 18) - 11 x 15 BGA

1

2

3

4

WPS

5

6

K

7

NC

8

RPS

9

A

10

V_SS/72M

11

CQ

NC

V_SS/144M NC/36M

BWS₁

CQ

Q8

D8

D7

A

Q9

NC

D11

D9

A

NC

A

K

A

BWS₀

A

NC

Q7

NC

B

C

D

D10

Q10

V_SS

NC

Q11

D12

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

NC

D6

Q6

E

F

NC

Q12

D13

V_REF

NC

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

NC

Q5

D5

ZQ

D4

Q3

Q2

Q13

V_DDQ

D14

NC

G

H

J

DOFF

NC

V_DDQ

NC

V_REF

Q4

NC

Q14

D15

D16

Q16

Q17

V_DD

V_SS

A

NC

D3

K

L

NC

Q15

NC

D17

NC

V_SS

A

V_SS

A

V_SS

Q1

NC

D0

D2

D1

Q0

M

N

P

A

C

A

TDO

TCK

A

C

A

TMS

TDI

R

Document #: 38-05180 Rev. *A

Page 3 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Pin Configurations (continued)

CY7C1314V18 (512k x 36) - 11 x 15 BGA

1

CQ

2

3

4

WPS

5

6

K

7

8

RPS

9

10

11

CQ

Q8

D8

D7

V

_SS/288M NC/72M

BWS₂

BWS₁

BWS₀

A

NC/36M V_SS/144M

A

B

C

D

Q27

D27

D28

Q18

Q28

D20

D18

D19

Q19

A

BWS₃

A

K

A

D17

D16

Q16

Q17

Q7

V_SS

D15

Q29

D29

Q20

D21

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

Q15

D14

D6

Q6

E

F

Q30

D30

Q21

D22

V_REF

Q31

D32

Q24

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

Q14

D13

V_REF

Q4

Q5

D5

ZQ

D4

Q3

Q2

Q22

V_DDQ

D23

Q13

G

H

J

DOFF

D31

VDDQ

D12

Q32

Q33

Q23

D24

D25

Q25

Q26

V_DD

V_SS

A

Q12

D11

D10

Q10

Q9

D3

K

L

Q11

D33

D34

Q35

Q34

D26

D35

V_SS

A

V_SS

A

V_SS

Q1

D9

D0

D2

D1

Q0

M

N

P

A

C

A

TDO

TCK

A

C

A

TMS

TDI

R

Document #: 38-05180 Rev. *A

Page 4 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Pin Definitions

Pin Name

I/O

Pin Description

D_[x:0]

Input-

Synchronous

Data input signals, sampled on the rising edge of K and K clocks during valid

write operations.

CY7C1310V18 - D[7:0]

CY7C1312V18 - D[17:0]

CY7C1314V18 - D[35:0]

WPS

Input-

Synchronous

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When

asserted active, a write operation is initiated. Deasserting will deselect the Write port.

Deselecting the Write port will cause D_[x:0]to be ignored.

BWS₀, BWS₁,

BWS₂, BWS₃

Input-

Synchronous

Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K

and K clocks during write operations. Used to select which byte is written into the device

during the current portion of the write operations. Bytes not written remain unaltered.

CY7C1310V18 − BWS₀controls D_[3:0]and BWS₁controls D_[7:4]

.

CY7C1312V18 − BWS₀controls D_[8:0]and BWS₁controls D_[17:9].

CY7C1314V18 − BWS₀controls D_[8:0], BWS₁controls D_[17:9], BWS₂controls D_[26:18]

and BWS₃controls D_[35:27]

All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write

Select will cause the corresponding byte of data to be ignored and not written into the

device.

A

Input-

Synchronous

Address Inputs. Sampled on the rising edge of the K clock during active read and write

operations. These address inputs are multiplexed for both Read and Write operations.

Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1310V18,

1M x 18 (2 arrays each of 512K x 18) for CY7C1312V18 and 256K x 36 (2 arrays each

of 256K x 36) for CY7C1314V18. Therefore, only 20 address inputs are needed to

access the entirememory array of CY7C1310V18, 19 address inputs for CY7C1312V18

and 18 address inputs for CY7C1314V18. These inputs are ignored when the appro-

priate port is deselected.

Q_[x:0]

Outputs-

Synchronous

Data Output signals. These pins drive out the requested data during a Read operation.

Valid data is driven out on the rising edge of both the C and C clocks during Read

operations or K and K. when in single clock mode. When the Read port is deselected,

Q_[x:0]are automatically three-stated.

CY7C1310V18 − Q_[7:0]

CY7C1312V18 − Q_[17:0]

CY7C1314V18 − Q_[35:0]

RPS

Input-

Synchronous

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).

When active, a Read operation is initiated. Deasserting will cause the Read port to be

deselected. Whendeselected, thependingaccess is allowed tocomplete and theoutput

drivers are automatically three-stated following the next rising edge of the C clock. Each

read access consists of a burst of two sequential transfers.

C

K

Input-

Clock

Positive Output Clock Input. C is used in conjunction with C to clock out the Read

data from the device. C and C can be used together to deskew the flight times of various

devices on the board back to the controller. See application example for further details.

Input-Clock

Negative Output Clock Input. C is used in conjunction with C to clock out the Read

data from the device. C and C can be used together to deskew the flight times of various

devices on the board back to the controller. See application example for further details.

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs

to the device and to drive out data through Q_[x:0]when in single clock mode. All accesses

are initiated on the rising edge of K.

K

Input-Clock

Echo Clock

Negative Input Clock Input. K is used to capture synchronous inputs being presented

to the device and to drive out data through Q_[x:0]when in single clock mode.

CQ

CQ is referenced with respect to C. This is a free running clock and is synchronized

to the output clock of the QDR^TM-II. In the single clock mode, CQ is generated with

respect to K. The timings for the echo clocks are shown in the AC timing table.

CQ

Echo Clock

CQ is referenced with respect to C. This is a free running clock and is synchronized

to the output clock of the QDR^TM-II. In the single clock mode, CQ is generated with

respect to K. The timings for the echo clocks are shown in the AC timing table.

Document #: 38-05180 Rev. *A

Page 5 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Pin Definitions (continued)

Pin Name

ZQ

I/O

Pin Description

Input

Output Impedance Matching Input. This input is used to tune the device outputs to

the system data bus impedance. Q_[x:0]output impedance are set to 0.2 x RQ, where RQ

is a resistor connected between ZQ and ground. Alternately, this pin can be connected

directly to V_DD, which enables the minimum impedance mode. This pin cannot be

connected directly to GND or left unconnected.

DOFF

Input

DLL Turn Off. Connecting this pin to ground will turn off the DLL inside the device. The

timings in the DLL turned off operation will be different from those listed in this data

sheet. More details on this operation can be found in the application note, “DLL

Operation in the QDR^TM-II.”

TDO

TCK

TDI

Output

Input

TDO for JTAG.

TCK pin for JTAG.

TDI pin for JTAG.

TMS

NC

TMS pin for JTAG.

No connects inside the package. Can be tied to any voltage level.

NC/36M

Address expansion for 36M. This is not connected to the die and so can be tied to any

voltage level.

NC/72M

Input

Address expansion for 72M. This is not connected to the die and so can be tied to any

voltage level.

V_SS/72M

V_SS/144M

V_SS/288M

V_REF

Input

Address expansion for 72M. This must be tied LOW on the 18M devices.

Address expansion for 144M. This must be tied LOW on the 18M devices.

Address expansion for 288M. This must be tied LOW on the 18M devices.

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs

and Outputs as well as AC measurement points.

V_DD

Power Supply

Power supply inputs to the core of the device. Should be connected to 1.8V power

supply.

V_SS

Ground

Ground for the device. Should be connected to ground of the system.

V_DDQ

Power Supply

Power supply inputs for the outputs of the device. Should be connected to 1.5V

power supply.

registers controlled by the rising edge of the output clocks (C

and C or K and K when in single clock mode).

Introduction

Functional Overview

All synchronous control (RPS, WPS, BWS_[x:0]) inputs pass

The

CY7C1310V18/CY7C1312V18/CY7C1314V18

are

through input registers controlled by the rising edge of the

input clocks (K and K).

synchronous pipelined Burst SRAMs equipped with both a

Read port and a Write port. The Read port is dedicated to

Read operations and the Write port is dedicated to Write

operations. Data flows into the SRAM through the Write port

and out through the Read Port. These devices multiplex the

address inputs in order to minimize the number of address pins

required. By having separate Read and Write ports, the

QDR^TM-II completely eliminates the need to “turn-around” the

data bus and avoids any possible data contention, thereby

simplifying system design. Each access consists of two 8-bit

data transfers in the case of CY7C1310V18, two 18-bit data

transfers in the case of CY7C1312V18 and two 36-bit data

transfers in the case of CY7C1314V18, in one clock cycles.

The following descriptions take CY7C1312V18 as an

example. However, the same is true for the other QDR^TM-II

SRAMs, CY7C1310V18 and CY7C1314V18.

These chips utilize a Delay Lock Loop (DLL) that is designed

to function between 80 MHz and the specified maximum clock

frequency. The DLL may be disabled by applying ground to the

DOFF pin.

Read Operations

The CY7C1312V18 is organized internally as a 512Kx36

SRAM. Accesses are completed in a burst of two sequential

18-bit data words. Read operations are initiated by asserting

RPS active at the rising edge of the Positive Input Clock (K).

The address is latched on the rising edge of the K Clock. The

address presented to Address inputs is stored in the Read

address register. Following the next K clock rise the corre-

sponding lowest order 18-bit word of data is driven onto the

Q_[17:0]using C as the output timing reference. On the subse-

quent rising edge of C, the next 18-bit data word is driven onto

Accesses for both ports are initiated on the rising edge of the

positive Input Clock (K). All synchronous input timings are

referenced from the rising edge of the input clocks (K and K)

and all output timings are referenced to the output clocks (C

and C or K and K when in single clock mode).

All synchronous data inputs (D_[x:0]) inputs pass through input

registers controlled by the input clocks (K and K). All

synchronous data outputs (Q_[x:0]) outputs pass through output

Document #: 38-05180 Rev. *A

Page 6 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

the Q_[17:0]. The requested data will be valid 0.4 ns from the

rising edge of the output clock (C/C, 167-MHz device).

the user must tie C and C HIGH at power on. This function is

a strap option and not alterable during device operation.

Synchronous internal circuitry will automatically three-state

the outputs following the next rising edge of the Output Clocks

(C/C). This will allow for a seamless transition between

devices without the insertion of wait states in a depth

expanded memory.

Concurrent Transactions

The Read and Write ports on the CY7C1312V18 operate

completely independently of one another. Since each port

latches the address inputs on different clock edges, the user

can Read or Write to any location, regardless of the trans-

action on the other port. Also, reads and writes can be started

in the same clock cycle. If the ports access the same location

at the same time, the SRAM will deliver the most recent infor-

mation associated with the specified address location. This

includes forwarding data from a Write cycle that was initiated

on the previous K clock rise.

Write Operations

Write operations are initiated by asserting WPS active at the

rising edge of the Positive Input Clock (K). On the same K

clock rise, the data presented to D_[17:0]is latched and stored

into the lower 18-bit Write Data register provided BWS_[1:0]are

both asserted active. On the subsequent rising edge of the

Negative Input Clock (K), the address is latched and the infor-

mation presented to D_[17:0]is stored into the Write Data

Register provided BWS_[1:0]are both asserted active. The 36

bits of data are then written into the memory array at the

specified location. When deselected, the write port will ignore

all inputs after the pending Write operations have been

completed.

Depth Expansion

The CY7C1312V18 has a Port Select input for each port. This

allows for easy depth expansion. Both Port Selects are

sampled on the rising edge of the Positive Input Clock only (K).

Each port select input can deselect the specified port.

Deselecting a port will not affect the other port. All pending

transactions (Read and Write) will be completed prior to the

device being deselected.

Byte Write Operations

Byte Write operations are supported by the CY7C1312V18. A

write operation is initiated as described in the Write Operation

section above. The bytes that are written are determined by

BWS₀and BWS₁which are sampled with each set of 18-bit

data word. Asserting the appropriate Byte Write Select input

during the data portion of a write will allow the data being

presented to be latched and written into the device.

Deasserting the Byte Write Select input during the data portion

of a write will allow the data stored in the device for that byte

to remain unaltered. This feature can be used to simplify

Read/Modify/Write operations to a Byte Write operation.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ

pin on the SRAM and V_SSto allow the SRAM to adjust its

output driver impedance. The value of RQ must be 5x the

value of the intended line impedance driven by the SRAM. The

allowable range of RQ to guarantee impedance matching with

a tolerance of ±10% is between 175Ω and 350Ω, with

V

_DDQ= 1.5V. The output impedance is adjusted every 1024

cycles to adjust for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR^TM-II to simplify data

capture on high-speed systems. Two echo clocks are

generated by the QDR^TM-II. CQ is referenced with respect to

C and CQ is referenced with respect to C. These are

free-running clocks and are synchronized to the output clock

of the QDR^TM-II. In the single clock mode, CQ is generated

with respect to K and CQ is generated with respect to K. The

timings for the echo clocks are shown in the AC Timing table.

Single Clock Mode

The CY7C1312V18 can be used with a single clock that

controls both the input and output registers. In this mode, the

device will recognize only a single pair of input clocks (K and

K) that control both the input and output registers. This

operation is identical to the operation if the device had zero

skew between the K/K and C/C clocks. All timing parameters

remain the same in this mode. To use this mode of operation,

Document #: 38-05180 Rev. *A

Page 7 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

\

Application Example^[2]

V_TERM= V_REF

SRAM #1

SRAM #4

Q

D

Q

D

18

R = 50Ω

Memory

18

Controller

72

Q

17

Din

Add.

Cntr.

72

2

CLK/CLK (input)

CLK/CLK (output)

2

R = 50Ω

V_T= V_REF

Truth Table^{[ 3, 4, 5, 6, 7, 8]}

Operation

K

RPS

WPS

DQ

D(A + 00)at K(t) ↑

DQ

Write Cycle:

L-H

X

L

D(A + 01) at K(t) ↑

Load address on the rising edge of K

clock; input write data on K and K

rising edges.

Read Cycle:

L-H

X

Q(A + 00) at C(t + 1)↑ Q(A + 01) at C(t + 2) ↑

Load address on the rising edge of K

clock; wait one and a half cycle; read

data on C and C rising edges.

NOP: No Operation

L-H

H

X

H

X

High-Z

Standby: Clock Stopped

Stopped

Previous State

[3, 9]

Write Cycle Descriptions (CY7C1310V18 and CY7C1312V18)

BWS₀

BWS₁

K

Comments

L

L-H

–

During the Data portion of a Write sequence :

CY7C1310V18 − both nibbles (D_[7:0]) are written into the device,

CY7C1312V18 − both bytes (D_[17:0]) are written into the device.

L

–

L-H During the Data portion of a Write sequence :

CY7C1310V18 − both nibbles (D_[7:0]) are written into the device,

CY7C1312V18 − both bytes (D_[17:0]) are written into the device.

Notes:

2. The above application shows 4 CY7C1312V18 being used. This holds true for CY7C1310V18 and CY7C1314V18 as well.

3. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge.

4. Device will power-up deselected and the outputs in a three-state condition.

5. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01 represents the internal address sequence in the burst.

6. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.

7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line

charging symmetrically.

9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS₀and BWS₁can be altered on different portions of a write cycle, as

long as the set-up and hold requirements are achieved.

Document #: 38-05180 Rev. *A

Page 8 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Write Cycle Descriptions (CY7C1310V18 and CY7C1312V18) (continued)^{[3, 9]}

BWS₀

BWS₁

K

Comments

During the Data portion of a Write sequence :

L

H

L-H

–

CY7C1310V18 − only the lower nibble (D_[3:0]) is written into the device. D_[7:4]will remain

unaltered,

CY7C1312V18 − only the lower byte (D_[8:0]) is written into the device. D_[17:9]will remain

unaltered.

L

H

L

–

L-H

–

L-H During the Data portion of a Write sequence :

CY7C1310V18 − only the lower nibble (D_[3:0]) is written into the device. D_[7:4]will remain

unaltered,

CY7C1312V18 − only the lower byte (D_[8:0]) is written into the device. D_[17:9]will remain

unaltered.

–

During the Data portion of a Write sequence :

CY7C1310V18 − only the upper nibble (D_[7:4]) is written into the device. D_[3:0]will remain

unaltered,

CY7C1312V18 − only the upper byte (D_[17:9]) is written into the device. D_[8:0]will remain

unaltered.

L-H During the Data portion of a Write sequence :

CY7C1310V18 − only the upper nibble (D_[7:4]) is written into the device. D_[3:0]will remain

unaltered,

CY7C1312V18 − only the upper byte (D_[17:9]) is written into the device. D_[8:0]will remain

unaltered.

H

L-H

–

No data is written into the devices during this portion of a write operation.

–

L-H No data is written into the devices during this portion of a write operation.

[3, 9]

Write Cycle Descriptions (CY7C1314V18)

BWS₀

BWS₁

BWS₂

BWS₃

K

Comments

L

L-H

-

During the Data portion of a Write sequence, all four

bytes (D_[35:0]) are written into the device.

L

-

L-H

-

During the Data portion of a Write sequence, all four

bytes (D_[35:0]) are written into the device.

H

L-H

During the Data portion of a Write sequence, only

the lower byte (D_[8:0]) is written into the device.

D_[35:9]will remain unaltered.

L

H

L

H

L

H

L

-

L-H

-

During the Data portion of a Write sequence, only

the lower byte (D_[8:0]) is written into the device.

D_[35:9]will remain unaltered.

H

L-H

-

During the Data portion of a Write sequence, only

the byte (D_[17:9]) is written into the device. D_[8:0]and

D_[35:18]will remain unaltered.

L

L-H

-

During the Data portion of a Write sequence, only

the byte (D_[17:9]) is written into the device. D_[8:0]and

D_[35:18]will remain unaltered.

H

L-H

-

During the Data portion of a Write sequence, only

the byte (D_[26:18]) is written into the device. D_[17:0]

and D_[35:27]will remain unaltered.

L

L-H

During the Data portion of a Write sequence, only

the byte (D_[26:18]) is written into the device. D_[17:0]

and D_[35:27]will remain unaltered.

H

L-H

During the Data portion of a Write sequence, only

the byte (D_[35:27]) is written into the device. D_[26:0]

will remain unaltered.

Document #: 38-05180 Rev. *A

Page 9 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Write Cycle Descriptions (CY7C1314V18) (continued)^{[3, 9]}

BWS₀

BWS₁

BWS₂

BWS₃

K

Comments

H

L

-

L-H

During the Data portion of a Write sequence, only

the byte (D_[35:27]) is written into the device. D_[26:0]

will remain unaltered.

H

L-H

-

No data is written into the device during this portion

of a write operation.

L-H

No data is written into the device during this portion

of a write operation.

Document #: 38-05180 Rev. *A

Page 10 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-up Current.................................................... > 200 mA

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Operating Range

Ambient

Supply Voltage on V_DDRelative to GND........ –0.5V to +2.9V

Range Temperature^[10]

V_DD

V_DDQ

DC Voltage Applied to Outputs

in High-Z State^[12]............................... –0.5V to V_DDQ+ 0.5V

Com’l

0°C to +70°C

1.8 ± 100 mV 1.4V to V_DD

DC Input Voltage^[12]............................ –0.5V to V_DDQ+ 0.5V

Electrical Characteristics Over the Operating Range^{[1, 11]}

Parameter

V_DD

V_DDQ

V_OH

V_OL

Description

Test Conditions

Min.

1.7

Typ.

1.8

Max.

1.9

Unit

V

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage^[12]

Input LOW Voltage^[12]

Input Load Current

1.4

1.5

V_DD

V

I_OH= −2.0 mA, Nominal Impedance

V_DDQ– 0.2 V_DDQ– 0.2

V_SSV_SS

V_REF+ 0.1 V_REF+ 0.1

V_DDQ

0.2

V

I_OL= 2.0 mA, Nominal Impedance

V

V_IH

V_DDQ+0.3

V

V_IL

–0.3

−5

V_REF– 0.1 V_REF– 0.1

V

I_X

GND ≤ V_I≤ V_DDQ

−5

5

µA

I_OZ

Output Leakage

Current

GND ≤ V_I≤ V_DDQ,Output Disabled

−5

V_REF

I_DD

Input Reference

Voltage^[13]

Typical Value = 0.75V

0.68

0.75

0.95

V

V_DDOperating Supply V_DD= Max., I_OUT= 0 mA, 133 MHz

x8, x18

TBD

mA

f = f_MAX= 1/t_CYC

167 MHz

200 MHz

I_DD

V_DDOperating Supply V_DD= Max., I_OUT= 0 mA, 133 MHz

x36

f = f_MAX= 1/t_CYC

167 MHz

200 MHz

133 MHz

167 MHz

200 MHz

I_SB1

Automatic

Power-down

Current, x8, x18

Max. V_DD, Both Ports

Deselected, V_IN≥ V_IHor

V_IN≤ V_ILf = f_MAX=

1/t_CYC,Inputs Static

I_SB1

Automatic

Power-down

Current, x36

Max. V_DD, Both Ports

Deselected, V_IN≥ V_IHor

133 MHz

167 MHz

200 MHz

TBD

mA

V_IN≤ V_ILf = f_MAX

=

1/t_CYC,Inputs Static

Notes:

10. Ambient Temperature = T_A. This is the case temperature.

11. All Voltage referenced to Ground.

12. Overshoot: V_IH(AC)<V_DD+ 0.5V for t < t_TCYC/2; undershoot V_IL(AC)< − 0.5V for t < t_TCYC/2; power-up: V_IH<1.8V and V_DD<1.8V and V_DDQ< 1.4V for t <

200 ms.

13. V_REFMin. = 0.68V or 0.46V_DDQ, whichever is larger, V_REFMax. = 0.95V or 0.54V_DDQ, whichever is smaller.

Document #: 38-05180 Rev. *A

Page 11 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Switching Characteristics Over the Operating Range^{[1, 14]}

200 MHz

167 MHz

133 MHz

Parameter

t_CYC

Description

K Clock and C Clock Cycle Time

Input Clock (K/K and C/C) HIGH

Input Clock (K/K and C/C) LOW

Min.

5.0

2.0

2.2

Max.

Min.

Max.

Min.

7.5

Max.

Unit

ns

6.0

2.4

2.7

7.5

8.0

t_KH

-

3.0

-

ns

t_KL

3.0

ns

t_KHKH

K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise

(rising edge to rising edge)

3.38

ns

t_KHCH

K/K Clock Rise to C/C Clock Rise (rising edge to rising

edge)

0.0

2.3

0.0

2.8

0.0

3.5

ns

Set-up Times

t_SA

t_SC

Address Set-up to K Clock Rise

0.5

-

0.6

-

0.7

-

ns

Control Set-up to Clock (K, K) Rise (RPS, WPS,

BWS₀, BWS₁)

t_SD

D_[17:0]Set-up to Clock (K and K) Rise

0.5

-

0.6

-

0.7

-

ns

Hold Times

t_HA

t_HC

Address Hold after Clock (K and K) Rise

0.5

-

0.6

-

0.7

-

ns

Control Hold after Clock (K and K) Rise (RPS, WPS,

BWS₀, BWS₁)

t_HD

D_[17:0]Hold after Clock (K and K) Rise

0.5

-

0.6

-

0.7

-

ns

Output Times

t_CO

C/C Clock Rise (or K/K in Single Clock Mode) to Data

Valid^[14]

0.38

-

0.40

-

0.40

-

ns

t_DOH

Data Output Hold after Output C/C Clock Rise (Active –0.38

to Active)

–0.40

t_CCQO

t_CQOH

t_CQD

t_CLZ

C/C Clock Rise to Echo Clock Valid

Echo Clock Hold after C/C Clock Rise

Echo Clock High to Data Change

Clock (C and C) Rise to Low-Z^{[15, 16]}

-

0.36

-

0.38

-

0.38

-

–0.36

–0.38

0.38

-

0.40

-

0.40

-

–0.38

–0.40

ns

t_CHZ

Clock (C and C) Rise to High-Z (Active to High-Z)^[15,

-

0.38

-

0.40

-

0.40

16]

DLL Timing

t_KC

Clock Phase Jitter

-

0.13

-

0.15

-

0.15

-

ns

t_{KC lock}

DLL Lock Time (K, C)

1024

cycles

Capacitance^[17]

Parameter

C_IN

Description

Input Capacitance

Test Conditions

Max.

TBD

Unit

T_A= 25°C, f = 1 MHz,

V_DD= 1.8V

V_DDQ= 1.5V

pF

C_CLK

Clock Input Capacitance

Output Capacitance

C_O

Notes:

14. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, V_REF= 0.75V, RQ = 250Ω, V_DDQ= 1.5V,

input pulse levels of 0.25V to 1.25V, and output loading of the specified I_OL/I_OHand load capacitance shown in (a) of AC Test Loads.

15. t_CHZ, t_CLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

16. At any given voltage and temperature t_CHZis less than t_CLZand t_CHZless than t_CO

.

17. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05180 Rev. *A

Page 12 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

AC Test Loads and Waveforms

V

= 0.75V

REF

0.75V

V

REF

V

0.75V

REF

R = 50Ω

OUTPUT

[14]

ALL INPUT PULSES

1.25V

Z = 50Ω

0

OUTPUT

Device

Under

Test

R = 50Ω

L

0.75V

0.25V

5 pF

Slew Rate = 2V / ns

Under

V

= 0.75V

REF

ZQ

Test

RQ =

250Ω

RQ =

250Ω

(a)

INCLUDING

JIG AND

SCOPE

(b)

Switching Waveforms

Read/Deselect Sequence

Read

Deselect

Read

t_KHKH

t_KL

t_CYC

t_KHKH

K

t_KH

t_KL

K

t_KH

t_SA

A

B

C

t_SC

t_HA

t_HC

RPS

Q(A+1)

Q(B+1)

Q(C+1)

Q(A)

Q(B)

Q(C)

Data Out

t_CQD

t_CO

t_CLZ

t_KHCH

t_CQD

t_CO

t_KL

t_KHKH

t_KH

C

t_DOH

t_CHZ

t_KL

t_KHCH

C

t_KH

t

CQOH

t_CCQO

CQ

t_CQOH

t_CCQO

= UNDEFINED

= DON’T CARE

Document #: 38-05180 Rev. *A

Page 13 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Switching Waveforms

Write/Deselect Sequence^{[18, 19]}

Write

Deselect

Write

Deselect

t_KL

t_CYC

K

t_KH

t_KL

K

t_SA

t_HA

A

B

t_HD

t_SC

t_HC

WPS

t_HC

t_SC

BWS_x

D(B+1)

D(A)

D(B)

D(A+1)

Data In

t_HD

t_SD

= UNDEFINED

= DON’T CARE

Notes:

18. C and C reference to Data Outputs and do not affect Write operations.

19. BWS_xLOW = Valid, Byte writes allowed, see Byte write table for details.

Document #: 38-05180 Rev. *A

Page 14 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Switching Waveforms

Read/Write/Deselect Sequence^[20]

Read/Write

Read

Deselect

K

A

F

A

B

E

C

D

WPS

RPS

D_[x:0]

Q_[x:0]

D(B)

D(B+1)

D(D)

D(D+1)

D(E)

D(E+1)

Q(A+1)

Q(C+1)

Q(A)

Q(C)

Q(E)

Q(GQ+(E1)+1)

Q(F)

Q(F+1)

C

CQ

= UNDEFINED

= DON’T CARE

Note:

20. BWS[0:X] is LOW during these cycles.

of other devices using 1149.1 fully compliant TAPs. The TAP

operates using JEDEC standard 1.8V I/O logic levels.

IEEE 1149.1 Serial Boundary Scan (JTAG)

The QDR^TM-II devices incorporate a serial boundary scan test

access port (TAP) in the FBGA package. This port operates in

accordance with IEEE Standard 1149.1-1900, but does not

have the set of functions required for full 1149.1 compliance.

These functions from the IEEE specification are excluded

because their inclusion places an added delay in the critical

speed path of the SRAM. Note that the TAP controller

functions in a manner that does not conflict with the operation

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V_SS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V_DDthrough a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

Document #: 38-05180 Rev. *A

Page 15 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

in a reset state which will not interfere with the operation of the

device.

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(V_SS) when the BYPASS instruction is executed.

Test Access Port–Test Clock

Boundary Scan Register

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

The boundary scan register is connected to all the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices.

Test Mode Select

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

Test Data-In (TDI)

The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) on any register.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

Test Data Out (TDO)

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see Instruction codes). The

output changes on the falling edge of TCK. TDO is connected

to the least significant bit (LSB) of any register.

TAP Instruction Set

Performing a TAP Reset

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

A Reset is performed by forcing TMS HIGH (V_DD) for five rising

edges of TCK. This RESET does not affect the operation of

the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a high-Z state.

The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented. The TAP controller

cannot be used to load address, data or control signals into the

SRAM and cannot preload the Input or output buffers. The

SRAM does not implement the 1149.1 commands EXTEST or

INTEST or the PRELOAD portion of SAMPLE/PRELOAD;

rather it performs a capture of the Input and Output ring when

these instructions are executed.

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

Instruction Register

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the

TDI and TDO pins as shown in TAP Controller Block Diagram.

Upon power-up, the instruction register is loaded with the

IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in the TAP controller, and

therefore this device is not compliant to the 1149.1 standard.

When the TAP controller is in the Capture IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board level serial test path.

Bypass Register

The TAP controller does recognize an all-0 instruction. When

an EXTEST instruction is loaded into the instruction register,

the SRAM responds as if a SAMPLE / PRELOAD instruction

has been loaded.

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

register is a single-bit register that can be placed between TDI

Document #: 38-05180 Rev. *A

Page 16 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

IDCODE

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture set-up plus

hold times (t_CSand t_CH). The SRAM clock inputs might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the K, K, C and C captured in the

boundary scan register.

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

SAMPLE Z

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state.

Note that since the PRELOAD part of the command is not

implemented, putting the TAP into the Update to the

Update-DR state while performing a SAMPLE/PRELOAD

instruction will have the same effect as the Pause-DR

command.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The

PRELOAD portion of this instruction is not implemented, so

the TAP controller is not fully 1149.1 compliant.

Bypass

When the SAMPLE/PRELOAD instructions loaded into the

instruction register and the TAP controller in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

When the BYPASS instruction is loaded in the instruction

register and the TAP is placed in a Shift-DR state, the bypass

register is placed between the TDI and TDO pins. The

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document #: 38-05180 Rev. *A

Page 17 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

TAP Controller State Diagram^[21]

TEST-LOGIC

1

RESET

0

1

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

CAPTURE-IR

0

SHIFT-DR

0

SHIFT-IR

0

1

EXIT1-DR

0

1

EXIT1-IR

0

1

0

PAUSE-DR

1

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-DR

UPDATE-IR

1

0

Note:

21. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 38-05180 Rev. *A

Page 18 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

TAP Controller Block Diagram

0

Bypass Register

Selection

Circuitry

Selection

Circuitry

2

1

0

TDO

TDI

Instruction Register

29

31 30

.

2

0

Identification Register

106

.

2

1

Boundary Scan Register

TCK

TMS

TAP Controller

TAP Electrical Characteristics Over the Operating Range^{[11, 12, 22, 23 ]}

Parameter

V_OH1

V_OH2

V_OL1

V_OL2

V_IH

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Test Conditions

I_OH= −2.0 mA

Min.

Max.

Unit

V

_DD− 0.45

V

I_OH= −100 µA

I_OL= 2.0 mA

I_OL= 100 µA

V_DD− 0.2

0.45

0.2

V

0.65V_DD

–0.3

V_DD+ 0.3

0.35V_DD

5

V

V_IL

Input LOW Voltage

V

I_X

Input and OutputLoad Current

GND ≤ V_I≤ V_DD

−5

µA

Notes:

22. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

23. _DDmeans core supply voltage.

V

Document #: 38-05180 Rev. *A

Page 19 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

TAP AC Switching Characteristics Over the Operating Range^{[24, 25]}

Parameter

t_TCYC

Description

Min.

Max.

Unit

ns

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH

100

t_TF

10

MHz

ns

t_TH

40

t_TL

TCK Clock LOW

ns

Set-up Times

t_TMSS

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

10

ns

t_TDIS

t_CS

Hold Times

t_TMSH

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

10

ns

t_TDIH

t_CH

Capture Hold after Clock Rise

Output Times

t_TDOV

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

20

ns

t_TDOX

0

Notes:

24.

t_CSand t_CHrefer to the set-up and hold time requirements of latching data from the boundary scan register.

25. Test conditions are specified using the load in TAP AC test conditions. t_R/t_F= 1 ns.

Document #: 38-05180 Rev. *A

Page 20 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

TAP Timing and Test Conditions^[25]

0.9V

50Ω

ALL INPUT PULSES

0.9V

TDO

1.8V

Z = 50Ω

0

C = 20 pF

L

0V

GND

t_TL

t_TH

(a)

Test Clock

TCK

t_TCYC

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOV

t_TDOX

Identification Register Definitions

CY7C1310V18

CY7C1312V18

1M x 18

CY7C1314V18

512K x 36

000

Instruction Field

2M x 8

Description

Revision Number (31:29)

000

Version number.

Cypress Device ID

(28:12)

11010011010000101 11010011010010101 11010011010100101 Defines the type of SRAM.

Cypress JEDEC ID (11:1)

00000110100

1

00000110100

1

00000110100

1

Allows unique identification of

SRAM vendor.

ID Register Presence (0)

Indicates thepresenceofanID

register.

Scan Register Sizes

Register Name

Instruction

Bit Size

3

1

Bypass

ID

32

107

Boundary Scan

Document #: 38-05180 Rev. *A

Page 21 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the Input/Output ring contents. Places the boundary scan register

between the TDI and TDO. This instruction is not 1149.1 compliant. The

EXTEST command implemented by these devices will NOT place the

output buffers into a high-Z condition. If the output buffers need to be

in high-Z condition, this can be accomplished by deselecting the Read

port.

IDCODE

001

010

Loads the ID register with the vendor ID code and places the register between

TDI and TDO. This operation does not affect SRAM operation.

SAMPLE Z

Captures the Input/Output contents. Places the boundary scan register

between TDI and TDO. The SAMPLE Z command implemented by these

devices will place the output buffers into a high-Z condition.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures the Input/Output ring contents. Places the boundary scan register

between TDI and TDO. Does not affect the SRAM operation. This instruction

does not implement 1149.1 preload function and is therefore not 1149.1

compliant.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not

affect SRAM operation.

Boundary Scan Order

Boundary Scan Order (continued)

Bit #

0

Bump ID

6R

Bit #

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

Bump ID

10J

11J

1

6P

2

6N

11H

10G

9G

3

7P

4

7N

5

7R

11F

11G

9F

6

8R

7

8P

8

9R

10F

11E

10E

10D

9E

9

11P

10P

10N

9P

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

10M

11N

9M

10C

11D

9C

9N

9D

11L

11M

9L

11B

11C

9B

10L

11K

10K

9J

10B

11A

10A

9A

9K

8B

Document #: 38-05180 Rev. *A

Page 22 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Boundary Scan Order (continued)

Bit #

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

Bump ID

Bit #

94

Bump ID

3M

1N

7C

6C

8A

7A

7B

6B

6A

5B

5A

4A

5C

4B

3A

2A

1A

2B

3B

1C

1B

3D

3C

1D

2C

3E

2D

2E

1E

2F

3F

1G

1F

3G

2G

1J

95

96

2M

3P

97

98

2N

99

2P

100

101

102

103

104

105

106

1P

3R

4R

4P

5P

5N

5R

2J

3K

3J

2K

1K

2L

3L

1M

1L

3N

Document #: 38-05180 Rev. *A

Page 23 of 25

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Ordering Information^[1]

Speed

Package

Operating

Range

(MHz)

Ordering Code

Name

Package Type

13 x 15 mm FBGA

200

CY7C1310V18-200BZC

CY7C1312V18-200BZC

CY7C1314V18-200BZC

CY7C1310V18-167BZC

CY7C1312V18-167BZC

CY7C1314V18-167BZC

CY7C1310V18-133BZC

CY7C1312V18-133BZC

CY7C1314V18-133BZC

BB165A

Commercial

167

133

BB165A

13 x 15 mm FBGA

Package Diagram

165-ball FBGA (13 x 15 x 1.2 mm) BB165A

51-85122-*B

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC,

and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective

holders.

Document #: 38-05180 Rev. *A

Page 24 of 25

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1310V18

CY7C1312V18

CY7C1314V18

PRELIMINARY

Document Title: CY7C1310V18/CY7C1312V18/CY7C1314V18 18-Mb QDR™-II SRAM Two-word Burst Architecture

Document Number: 38-05180

Issue

Date

Orig. of

Change

REV.

**

ECN No.

110859

115917

Description of Change

11/09/01

08/05/02

SKX

RCS

New Data Sheet

*A

Changed Status to Preliminary.

Removed 250 MHz Speed Bin.

Shaded 200 MHz Speed Bin.

Added 133 MHz Speed Bin.

Updated JTAG Scan Order.

Document #: 38-05180 Rev. *A

Page 25 of 25


型号：	CY7C1312V18-200BZC
厂家：	CYPRESS
描述：	QDR SRAM, 1MX18, 0.38ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165 时钟静态存储器内存集成电路
文件：	总25页 (文件大小：443K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1312V18-200BZC [CYPRESS]

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