CY7C1324-100AC [CYPRESS]
Cache SRAM, 128KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | CY7C1324-100AC |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 128KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总15页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1324
3.3V 128K x 18 Synchronous
Cache RAM
Features
Functional Description
• Supports117-MHzmicroprocessorcachesystems with
zero wait states
• 128K by 18 common I/O
• Fast clock-to-output times
— 7.5 ns (117 MHz)
The CY7C1324 is a 3.3V, 128K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
• Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequence
• Separate processorand controller address strobes pro-
vides direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• I/Os capable of 2.5–3.3V operation
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
The CY7C1324 allows both interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH input on
MODE selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be initiat-
ed with the Processor Address Strobe (ADSP) or the cache
Controller Address Strobe (ADSC) inputs. Address advance-
ment is controlled by the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
MODE
2
(A ,A )
0
1
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
15
17
ADDRESS
REGISTER
CE
D
128K X 18
MEMORY
ARRAY
A
[16:0]
GW
17
15
BWE
BW
D
Q
Q
DQ[15:8]
BYTEWRITE
REGISTERS
1
D
DQ[7:0]
BYTEWRITE
REGISTERS
BW
0
CE
1
2
CE
D
CE
ENABLE
REGISTER
CLK
Q
CE
3
18
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
DP
[15:0]
[1:0]
Pin
Selection Guide
7C1324–117
7C1324–100
7C1324–80
7C1324–50
11.0
Maximum Access Time (ns)
7.5
350
1.0
8.0
325
1.0
8.5
300
1.0
Maximum Operating Current (mA)
Maximum Standby Current (mA)
250
1.0
Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 4, 1999
CY7C1324
Pin Configuration
100-Lead TQFP
NC
NC
NC
1
A10
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
NC
3
NC
VDDQ
VSS
4
VDDQ
VSS
NC
5
NC
6
NC
7
DP0
DQ7
DQ6
VSS
VDDQ
DQ5
DQ4
VSS
NC
DQ8
DQ9
VSS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQ10
DQ11
NC
CY7C1324
BYTE0
VDD
NC
VDD
ZZ
BYTE1
VSS
DQ12
DQ13
VDDQ
VSS
DQ3
DQ2
VDDQ
VSS
DQ1
DQ0
NC
DQ14
DQ15
DP1
NC
NC
VSS
VSS
VDDQ
NC
VDDQ
NC
NC
NC
NC
NC
2
CY7C1324
input is asserted LOW, the requested data will be available at
Functional Description (continued)
the data outputs a maximum to t
after clock rise. ADSP is
CDV
Single Write Accesses Initiated by ADSP
ignored if CE is HIGH.
1
This access is initiated when the following conditions are sat-
Burst Sequences
isfied at clock rise: (1) CE , CE , and CE are all asserted
1
2
3
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
counter/control logic and delivered to the RAM core. The write
This family of devices provide a 2-bit wrap around burst
counter inside the SRAM. The burst counter is fed by A
,
[1:0]
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
inputs (GW, BWE, and BWS
) are ignored during this first
[1:0]
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BWS controls DQ
and DP while
0
[7:0]
0
BWS controls DQ
and DP . All I/Os are three-stated dur-
1
[15:8]
1
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
ing a byte write. Since these are common I/O devices, the
asynchronous OE input signal must be deasserted and the
I/Os must be three-stated prior to the presentation of data to
First
Address
Second
Address
Third
Address
Fourth
Address
DQ
and DP
. As a safety precaution, the data lines are
[15:0]
[1:0]
three-stated once a write cycle is detected, regardless of the
state of OE.
A
,A
A
, A
A
, A
A
, A
X + 1 x
X + 1
x
X + 1
x
X + 1
x
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE , CE , and CE are all asserted
1
2
3
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWS
indicate a write access. ADSC is ignored if ADSP is active LOW.
)
Table 2. Counter Implementation for a Linear Sequence
[1:0]
First
Address
Second
Address
Third
Address
Fourth
Address
The addresses presented are loaded into the address register,
burst counter/control logic and delivered to the RAM core. The
A
, A
A
, A
A
, A
A
, A
X + 1 x
X + 1
x
X + 1
x
X + 1
x
information presented to DQ
and DP
will be written
[15:0]
[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
into the specified address location. Byte writes are allowed,
with BWS controlling DQ and DP while BWS controlling
0
[7:0]
0
1
DQ
and DP . All I/Os are three-stated when a write is
[15:8]
1
detected, even a byte write. Since these are common I/O de-
vices, the asynchronous OE input signal must be deasserted
and the I/Os must be three-stated prior to the presentation of
data to DQ
and DP
. As a safety precaution, the data
[15:0]
[1:0]
Sleep Mode
lines are three-stated once a write cycle is detected, regard-
less of the state of OE.
The ZZ input pin is an asynchronous input. Asserting a HIGH
input on ZZ places the SRAM in a power conservation “sleep”
mode. Two clock cycles are required to enter into or exit from
this “sleep” mode. While in this mode, data integrity is guaran-
teed. Accesses pending when entering the “sleep” mode are
not considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE , CE , and CE are all as-
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the Address Register, burst counter
/control logic and presented to the memory core. If the OE
1
2
3
the “sleep” mode. CE , CE , CE , ADSP, and ADSC must re-
1
2
3
main inactive for the duration of t
after the ZZ input re-
ZZREC
turns low
3
CY7C1324
Cycle Description Table[1, 2, 3]
ADD
Cycle Description
Used
CE
H
L
CE
X
X
H
X
X
X
L
CE
X
L
ZZ ADSP ADSP ADV WE OE
CLK
DQ
1
3
2
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
SNOOZE MODE, Power-down
READ Cycle, Begin Burst
None
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
HIGH-Z
Q
External
External
External
External
External
Next
L-H
READ Cycle, Begin Burst
L
L
L
H
X
L
L-H High-Z
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
READ Cycle, Begin Burst
L
L
L
H
L
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
X
L-H
L-H
D
D
WRITE Cycle, Suspend Burst
L
Notes:
1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[1:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
4
CY7C1324
Pin Descriptions
TQFP Pin
Number
Name
I/O
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
is captured in the address registers. A are also loaded into the burst
85
ADSC
Input-
Synchronous LOW, A
[16:0]
[1:0]
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
84
ADSP
Input-
Synchronous LOW, A
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
is captured in the address registers. A
are also loaded into the burst
[1:0]
[16:0]
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE is deasserted HIGH.
1
36, 37
A
A
Input-
Synchronous well as being used to access a particular memory location in the memory array.
Input- Address Inputs used in conjunction with A to select one of the 128K address
Synchronous locations. Sampled at the rising edge of the CLK, if CE , CE , and CE are sampled
A , A Address Inputs, These inputs feed the on-chip burst counter as the LSBs as
[1:0]
1 0
49–44,
80–82, 99,
100,
[16:2]
[1:0]
1
2
3
active, and ADSP or ADSC is active LOW.
32–35
94, 93
BWS
ADV
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
and DP , BWS controls DQ
[15:8]
[1:0]
Synchronous Sampled on the rising edge. BWS controls DQ
0
[7:0]
0
1
and DP . See Write Cycle Descriptions table for further details.
1
83
Input-
Advance Input used to advance the on-chip address counter. When LOW the internal
Synchronous burst counter is advanced in a burst sequence. The burst sequence is selected using
the MODE input.
87
88
BWE
GW
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
Synchronous must be asserted LOW to conduct a byte write.
Input-
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used
Synchronous to conduct a global write, independent of the state of BWE and BWS
override byte writes.
. Global writes
[1:0]
89
98
CLK
Input-Clock
Input-
Clock Input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
CE
CE
CE
1
2
3
Synchronous junction with CE and CE , to select/deselect the device. CE gates ADSP.
2
3
1
97
92
86
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-
Synchronous junction with CE and CE to select/deselect the device.
1
3
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
Synchronous junction with CE and CE to select/deselect the device.
1
2
OE
ZZ
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins.
64
31
Input-
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power
Asynchronous standby mode in which all other inputs are ignored, but the data in the memory array
is maintained. Leaving ZZ floating or NC will default the device into an active state.
MODE
-
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOWselects the linearburst order. When left floating orNC, defaults
to interleaved burst order.
23, 22, 19, DQ
18, 13, 12,
9, 8, 73,
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
[15:0]
Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A during the previous clock rise of the read cycle.
[17:0]
72, 69, 68,
63, 62, 59,
58
The direction of the pins is controlled by OE in conjunction with the internal control
logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[15:0]
and DP
are placed in a three-state condition. The outputs are automatically
[1:0]
three-stated when a WRITE cycle is detected.
74, 24
DP
I/O-
Bidirectional Data Parity lines. These behave identical to DQ
described above.
[15:0]
[1:0]
Synchronous These signals can be used as parity bits for bytes 0 and 1 respectively.
15, 41, 65,
91
V
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
DD
5
CY7C1324
Pin Descriptions
TQFP Pin
Number
Name
I/O
Description
5, 10, 17,
21, 26, 40,
55, 60, 67,
71, 76, 90
V
Ground
Ground for the device. Should be connected to ground of the system.
SS
4, 11, 20,
27, 54, 61,
70, 77
V
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 2.5 or 3.3V power supply.
No connects.
DDQ
1–3, 6, 7,
14, 16, 25,
28–30,
NC
-
50–53, 56,
57, 66, 75,
78, 79,
95–96
38, 39, 42, DNU
43
-
Do not use pins. Should be left unconnected or tied LOW.
Write Cycle Descriptions[1, 2, 3, 4]
Function
GW
1
BWE
BWS
BWS
1
0
Read
Read
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
1
Write Byte 0 - DQ
Write Byte 1 - DQ
Write All Bytes
and DP
1
[7:0]
0
and DP
1
[15:8]
1
1
Write All Bytes
0
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
ZZ > V − 0.2V
Min
Max
Unit
I
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
10
mA
ns
DDZZ
DD
t
ZZ > V − 0.2V
2t
CYC
ZZS
DD
t
ZZ < 0.2V
2t
ns
ZZREC
CYC
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ...................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Ambient
Range Temperature
[6]
V
V
DDQ
DD
Supply Voltage on V Relative to GND................ –0.5V to +4.6V
DD
DC Voltage Applied to Outputs
in High Z State ...............................................–0.5V to V + 0.5V
Com’l
0°C to +70°C
3.135V to 3.6V 2.375V to V
DD
[5]
DD
[5]
DC Input Voltage ...........................................–0.5V to V + 0.5V
DD
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA is the case temperature.
6
CY7C1324
Electrical Characteristics Over the Operating Range
7C1324
Parameter
Description
Test Conditions
= 3.3V, V = Min., I = –4.0 mA
Min.
Max.
Unit
V
V
Output HIGH Voltage
V
V
V
V
2.4
1.7
OH
DDQ
DDQ
DDQ
DDQ
DD
OH
= 2.5V, V = Min., I = –2.0 mA
V
DD
OH
V
Output LOW Voltage
Input HIGH Voltage
= 3.3V, V = Min., I = 8.0 mA
0.4
0.7
V
OL
DD
OL
= 2.5V, V = Min., I = 2.0 mA
V
DD
OL
V
V
1.7
V
+
DD
V
IH
IL
0.3V
0.8
1
[5]
Input LOW Voltage
–0.3
−1
V
I
Input Load Current
GND ≤ V ≤ V
µA
X
I
DDQ
(except ZZ and MODE)
Input Current of MODE
Input = V
Input = V
Input = V
Input = V
–30
–5
µA
µA
SS
5
DDQ
SS
Input Current of ZZ
µA
30
5
µA
DDQ
I
I
I
Output Leakage Current
GND ≤ V ≤ V Output Disabled
–5
µA
OZ
OS
DD
I
DD,
[7]
Output Short Circuit Current
V
V
f=f
=Max., V
=GND
–300
325
300
275
225
35
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD
OUT
V
Operating Supply Current
=Max., Iout=0mA,
=1/t
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
All speeds
DD
DD
MAX
.
CYC
I
Automatic CE Power-Down
Current—TTL Inputs
Max. V , Device Deselected,
DD
SB1
V ≥ V or V ≤ V ,
IN IH IN IL
30
f=f
inputs switching
MAX,
25
20
I
I
Automatic CE Power-Down
Current — CMOS Inputs
Max. V , Device Deselected,
10
SB2
SB3
DD
V ≥ V –0.3V or V ≤ 0.3V, f=0,
IN DD IN
inputs static
Max. V , Device Deselected,
Automatic CE Power-Down
Current—CMOS Inputs
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
All speeds
10
10
10
10
18
mA
mA
mA
mA
mA
DD
V
≥ V
- 0.3V or V ≤ 0.3V,
IN
DDQ IN
f=f
inputs switching
MAX,
I
Automatic CE
Max. V , Device Deselected,
DD
SB4
Power-Down Current — TTL In- V ≥ V or V ≤ V ,
IN
IH
IN
IL
puts static, F=0
f=0, inputs static
Capacitance[8]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
4
4
pF
pF
IN
A
V
= 5.0V
DD
C
I/O
Notes:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
8. Tested initially and after any design or process changes that may affect these parameters.
7
CY7C1324
AC Test Loads and Waveforms[10]
R1
2.5V
OUTPUT
OUTPUT
ALL INPUT PULSES
Z =50
Ω
0
2.5V
90%
10%
R =50
Ω
L
90%
10%
2.5 ns
R2
5 pF
GND
V =1.5V
L
INCLUDING
JIG AND
SCOPE
2.5 ns
≤
≤
[9]
1324–3
(a)
(b)
1324–4
[10]
Switching Characteristics Over the Operating Range
-117
-100
-90
-50
Parameter
Description
Clock Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
8.5
3.0
3.0
2.0
0.5
10
4.0
4.0
2.0
0.5
11
4.5
4.5
2.0
0.5
20
4.5
4.5
2.0
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CYC
CH
Clock HIGH
Clock LOW
CL
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
AS
AH
7.5
8.0
8.5
11.0
CDV
DOH
ADS
ADH
WES
WEH
ADVS
ADVH
DS
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
BWS
BWS
, GW,BWE Set-Up Before CLK Rise
[1:0]
[1:0]
, GW,BWE Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-Up
DH
CES
CEH
CHZ
CLZ
EOHZ
EOLZ
EOV
Chip Enable Hold After CLK Rise
[11,12]
Clock to High-Z
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
[11,12]
Clock to Low-Z
0
0
0
0
0
0
0
0
[11,13]
OE HIGH to Output High-Z
[11,13]
OE LOW to Output Low-Z
OE LOW to Output Valid
Notes:
9. R1=1667Ω and R2=1538Ω for IOH/IOL= –4/8mA, R1=521Ω and R2=481Ω for IOH/IOL= –2/2mA.
10. Unless otherwise noted, test conditions assume signal transition time of 2.5ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads.
11. tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. At any given voltage and temperature, tCHZ (max) is less than tCLZ (min).
13. This parameter is sampled and not 100% tested.
8
CY7C1324
Timing Diagrams
[14, 15]
Write Cycle Timing
Single W rite
Burst Write
Pipelined Write
t
Unselected
CH
t
CYC
CLK
t
ADH
t
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
t
ADH
t
ADSC initiated write
ADS
ADSC
ADV
t
t
ADVH
ADVS
t
ADV Must Be Inactive for ADSP Write
WD2
AS
WD3
WD1
ADD
GW
WE
t
AH
t
WH
t
WH
t
WS
t
WS
t
t
CES
CE masks ADSP
CEH
1
CE
1
t
t
CEH
CES
Unselected with CE
2
CE
CE
2
3
t
CES
t
CEH
OE
t
DH
t
DS
High-Z
High-Z
Data-
In
3a
2a
= UNDEFINED
2c
2d
1a
2b
= DON’T CARE
Note:
14. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table).
15. WDx stands for Write Data to Address X.
9
CY7C1324
Timing Diagrams (continued)
[14, 16]
Read Cycle Timing
Burst Read
Single Read
Unselected
t
t
CYC
CH
Pipelined Read
CLK
t
t
ADH
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
t
ADS
ADSC initiated read
ADSC
ADV
t
ADVS
t
ADH
Suspend Burst
t
t
ADVH
AS
ADD
GW
WE
RD3
RD1
RD2
t
AH
t
WS
t
WS
t
WH
t
t
CES
CEH
t
WH
CE masks ADSP
1
CE
CE
1
2
Unselected with CE
2
t
t
CES
t
CEH
CE
OE
3
t
CEH
CES
t
EOV
t
OEHZ
t
DOH
t
CDV
3a
Data Out
2d
2a
2b
2c
1a
t
CLZ
t
CHZ
= DON’T CARE
= UNDEFINED
Note:
16. RDx stands for Read Data from Address X.
10
CY7C1324
Timing Diagrams (continued)
READ/WRITE Timing
t
t
t
CYC
CL
CH
CLK
t
AH
t
t
AS
A
D
B
C
ADD
t
ADH
ADS
ADSP
t
t
ADH
ADS
ADSC
ADV
t
t
ADVH
ADVS
t
CEH
t
CES
CE1
CE
t
t
CEH
CES
t
t
WES
WEH
WE
OE
ADSP ignored
with CE1 HIGH
t
EOHZ
t
t
CLZ
Data
Q
(B+3)
D
(C+1)
D
(C+2)
D
(C+3)
Q
(B+2)
Q
(B+1)
Q(B)
Q(B)
D(C)
Q(D)
Q(A)
In/Out
CDV
t
DOH
t
CHZ
Device originally
deselected
WE is the combination of BWE, BWS
and GW to define a write cycle (see Write Cycle Definitions table).
[1:0]
CE is the combination of CE and CE . All chip selects need to be active in order to select
2
3
the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
11
CY7C1324
Timing Diagrams (continued)
Pipeline Timing
t
t
t
CYC
CL
CH
CLK
t
t
AS
C
E
F
G
H
B
D
A
ADD
t
ADH
ADS
ADSP
ADSC
ADV
t
t
CEH
CES
CE
CE
1
t
t
WES
WEH
WE
OE
ADSP ignored
with CE HIGH
1
t
t
CLZ
Data
D (E)
D (F)
D (H)
Q(A)
D (G)
Q(B)
Q(C)
Q(D)
CDV
t
DOH
t
CHZ
Device originally
deselected
CE is the combination of CE and CE . All chip selects need to be active in order to select
2
3
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
12
CY7C1324
Timing Diagrams (continued)
OE Switching Waveforms
OE
t
EOV
t
EOHZ
three-state
I/Os
t
EOLZ
13
CY7C1324
Timing Diagrams (continued)
[17 ,18
ZZ Mode Timing
CLK
ADSP
HIGH
ADSC
CE
1
2
LOW
HIGH
CE
CE
3
ZZ
t
ZZS
I
CC
I
(active)
CC
t
ZZREC
I
CCZZ
I/Os
Three-state
Notes:
17. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device.
18. I/Os are in three-state when exiting ZZ sleep mode.
14
CY7C1324
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
117
100
80
Ordering Code
Package Type
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
CY7C1324–117AC
CY7C1324–100AC
CY7C1324–80AC
CY7C1324–50AC
A101
A101
A101
A101
Commercial
Commercial
Commercial
Commercial
50
Document #: 38–00651–A
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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