CY7C1327B-166AC [CYPRESS]
256K x 18 Synchronous-Pipelined Cache RAM; 256K ×18的同步流水线高速缓存RAM
| 型号： | CY7C1327B-166AC |
| 厂家： | 
CYPRESS |
| 描述： | 256K x 18 Synchronous-Pipelined Cache RAM |
| 文件： | 总17页 (文件大小：597K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
327
CY7C1327B
256K x 18 Synchronous-Pipelined Cache RAM
The CY7C1327B I/O pins can operate at either the 2.5V or the
3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V.
Features
• Supports 100-MHz bus for Pentium and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 256K by 18 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1327B supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input. A 2-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP pinout
Byte write operations are qualified with the four Byte Write
Select (BW[1:0]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
The CY7C1327B is a 3.3V, 256K by 18 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
MODE
Logic Block Diagram
2
(A[1;0]
)
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
16
18
ADDRESS
REGISTER
CE
D
256KX18
MEMORY
ARRAY
A[17:0]
GW
18
16
DQ[15:8], DP[1]
BYTEWRITE
REGISTERS
D
Q
BWE
BW
1
DQ[7:0], DP[0]
BYTEWRITE
REGISTERS
D
Q
BW
0
18
18
CE
2
1
CE
D
CE
Q
ENABLE CE
REGISTER
CE
3
D
Q
OUTPUT
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ[15:0]
DP[1:0]
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05140 Rev. **
Revised September 6, 2001
CY7C1327B
Selection Guide
7C1327-166
7C1327-133
7C1327-100
Maximum Access Time (ns)
3.5
420
10
4.0
375
10
5.5
325
10
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
Commercial
Pin Configurations
100-Lead TQFP
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
2
NC
NC
V
3
V
4
DDQ
DDQ
V
5
V
SS
SS
NC
NC
6
NC
DP
7
0
DQ
DQ
V
8
DQ
DQ
V
8
9
7
6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
SS
V
V
DDQ
DDQ
DQ
DQ
DQ
DQ
V
10
11
5
4
NC
CY7C1327B
SS
BYTE0
V
NC
DD
NC
V
DD
BYTE1
V
ZZ
SS
DQ
DQ
DQ
V
12
13
3
2
DQ
V
DDQ
DDQ
SS
V
V
SS
DQ
DQ
DQ
NC
NC
V
14
15
1
0
DQ
DP
1
NC
V
SS
SS
V
V
DDQ
DDQ
NC
NC
NC
NC
NC
NC
Document #: 38-05140 Rev. **
Page 2 of 17
CY7C1327B
Pin Configurations (continued)
119-Ball BGA
2
1
3
A
4
5
6
A
7
A
B
C
D
E
F
VDDQ
NC
A
ADSP
ADSC
VDD
NC
A
VDDQ
NC
CE2
A
A
A
CE3
A
NC
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
VSS
Vss
VSS
NC
VSS
DQPa
NC
DQa
NC
DQa
VDD
NC
NC
CE1
OE
DQa
VDDQ
DQa
NC
VDDQ
NC
G
H
J
ADV
GW
DQb
VDDQ
NC
VDD
CLK
VDDQ
DQa
K
L
M
N
DQb
VDDQ
DQb
NC
DQb
NC
Vss
VSS
VSS
NC
BWE
A1
BWa
VSS
VSS
DQa
NC
NC
VDDQ
NC
DQa
P
R
T
NC
NC
DQPb
A
VSS
MODE
A
A0
VDD
NC
NC
VSS
VSS
A
NC
A
DQa
NC
NC
A
A
ZZ
U
VDDQ
NC
NC
NC
NC
VDDQ
Pin Definitions
Name
I/O
Input-
Description
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
A[17:0]
Synchronous CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the
2-bit counter.
BW[1:0]
GW
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[1:0] and BWE).
BWE
CLK
CE1
CE2
CE3
OE
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-Clock
Input-
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
Synchronous ments the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[17:0]
Synchronous is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Document #: 38-05140 Rev. **
Page 3 of 17
CY7C1327B
Pin Definitions (continued)
Name
I/O
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[17:0] is
ADSC
Input-
Synchronous captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. Leaving ZZ floating or NC will default the device into an active state.
ZZ pin has an internal pull-down.
DQ[15:0]
DP[1:0]
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[15:0] and DP[1:0] are placed
in a three-state condition.
VDD
Power Supply Power Supply inputs to the core of the device. Should be connected to 3.3V power supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the system.
Power Supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
VDDQ
I/O Power
Supply
VSSQ
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left
floating selects interleaved burst sequence. This is astrap pin and should remain static during device
operation. When left floating or NC, defaults to interleaved burst order. Mode pin has an internal
pull-up.
NC
No Connects.
is HIGH. The address presented to the address inputs (A[17:0]
)
Introduction
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (tCO) is 3.5 ns (166-MHz
device).
The CY7C1327B supports secondary cache in systems utiliz-
ing either a linear or interleaved burst sequence. The inter-
leaved burst order supports Pentium and i486 processors. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or
the Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The address presented
to A[17:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW[1:0]) and ADV inputs are ig-
nored during this first cycle.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[1:0]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ[15:0] and DP[1:0] inputs is written into
the corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW[1:0] signals. The CY7C1327B provides byte write capabil-
ity that is described in the Write Cycle Description table. As-
serting the Byte Write Enable input (BWE) with the selected
Byte Write (BW[1:0]) input will selectively write to only the de-
sired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
Document #: 38-05140 Rev. **
Page 4 of 17
CY7C1327B
Because the CY7C1327B is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[15:0] and DP[1:0] inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ[15:0] and DP[1:0] are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
ear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
Single Write Accesses Initiated by ADSC
First
Second
Third
Fourth
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW[1:0]) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A[17:0] is loaded into the address register and the address ad-
vancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-
ducted, the data presented to the DQ[15:0] and DP[1:0] is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Address
Address
Address
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Because the CY7C1327B is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[15:0] and DP[1:0] inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ[15:0] and DP[1:0] are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW.
Burst Sequences
The CY7C1327B provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a lin-
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Test Conditions
Min.
Max.
Unit
Snooze mode
standby current
ZZ > VDD − 0.2V
3
mA
tZZS
Deviceoperationto
ZZ
ZZ > VDD − 0.2V
2tCYC
ns
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
Document #: 38-05140 Rev. **
Page 5 of 17
CY7C1327B
Cycle Descriptions[1, 2, 3]
Next Cycle
Unselected
Add. Used
None
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
CE3
X
1
CE2
X
X
0
CE1
1
ADSP
X
0
ADSC
ADV
X
X
X
X
X
X
X
0
OE
X
X
X
X
X
X
X
1
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Write
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
Unselected
None
0
X
Unselected
None
X
1
0
0
X
Unselected
None
X
0
0
1
X
Unselected
None
X
0
0
1
X
Begin Read
External
External
Next
1
0
0
X
Begin Read
0
1
0
1
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
X
X
1
1
Next
1
0
0
Next
X
X
1
0
1
Hi-Z
DQ
Next
1
0
0
Current
Current
Current
Current
Current
Current
External
Next
X
X
1
1
1
Hi-Z
DQ
1
1
0
X
X
1
1
1
Hi-Z
DQ
1
1
0
X
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Begin Write
X
1
1
Begin Write
0
X
0
Continue Write
Continue Write
Suspend Write
Suspend Write
X
X
X
X
X
X
X
X
X
X
X
1
1
Next
X
1
0
Current
Current
None
X
1
1
X
X
1
ZZ “Sleep”
X
X
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BW[1:0], and GW. See Write Cycle Description table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Document #: 38-05140 Rev. **
Page 6 of 17
CY7C1327B
Write Cycle Description[4, 5, 6]
Function
Read
GW
1
BWE
1
BW3
X
1
BW2
X
1
BW1
X
1
BW0
X
1
Read
1
0
Write Byte 0 - DQ[7:0]
Write Byte 1 - DQ[15:8]
Write Bytes 1, 0
Write Byte 2 - DQ[23:16]
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 - DQ[31:24]
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Ambient
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Range
Temperature[8]
VDD
VDDQ
DC Voltage Applied to Outputs
in High Z State[7] ....................................... −0.5V to VDD + 0.5V
Com’l
0°C to +70°C
3.3V
−5%/+10%
2.5V −5%
3.3V +10%
DC Input Voltage[7].................................... −0.5V to VDD + 0.5V
Industrial –40°C to +85°C
Notes:
4. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[1:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ[15:0];DP[1:0] = High-Z when OE is
inactive or when the device is deselected, and DQ[15:0];DP[1:0] = data when OE is active.
7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
8.
TA is the case temperature.
Document #: 38-05140 Rev. **
Page 7 of 17
CY7C1327B
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Test Conditions
Min.
3.135
2.375
2.4
Max.
3.6
Unit
V
Power Supply Voltage 3.3V −5%/+10%
VDDQ
I/O Supply Voltage
2.5V −5% to 3.3V +10%
3.6
V
VOH
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA
VDDQ = 3.3V
V
2.0
V
VOL
Output LOW Voltage
0.4
0.7
V
V
VIH
VIH
VIL
VIL
IX
Input HIGH Voltage
Input HIGH Voltage
Input LOW Voltage[7]
Input LOW Voltage[7]
2.0
1.7
VDD + 0.3V
VDD + 0.3V
0.8
V
VDDQ = 2.5V
V
VDDQ = 3.3V
–0.3
–0.3
−5
V
VDDQ = 2.5V
0.7
V
Input Load Current
GND ≤ VI ≤ VDDQ
5
µA
except ZZ and MODE
Input Current of MODE Input = VSS
Input = VDDQ
−30
−5
µA
µA
µA
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDDQ
30
5
IOZ
IDD
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
−5
VDD Operating Supply VDD = Max., IOUT = 0 mA,
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
420
375
325
150
125
115
10
mA
mA
mA
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
Automatic CS
Power-Down
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
Current—TTL Inputs
f = fMAX = 1/tCYC
ISB2
Automatic CS
Power-Down
Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CS
Power-Down
Current—CMOS Inputs f = fMAX = 1/tCYC
Max. VDD, Device Deselected, or 6-ns cycle, 166 MHz
120
95
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
85
ISB4
Automatic CS
Power-Down
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
18
Current—TTL Inputs
Capacitance[9]
Parameter
Description
Input Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
VDD = 3.3V,
VDDQ = 3.3V
4
4
4
pF
pF
pF
CCLK
Clock Input Capacitance
Input/Output Capacitance
CI/O
Note:
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05140 Rev. **
Page 8 of 17
CY7C1327B
AC Test Loads and Waveforms
R=317Ω
3.3V
[10]
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
2.5V
GND
90%
10%
Z =50Ω
0
R =50Ω
10%
L
5 pF
R=351Ω
≤ 2.5 ns
≤ 2.5 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Switching Characteristics Over the Operating Range[11, 12, 13]
-166
-133
-100
Parameter
tCYC
tCH
Description
Clock Cycle Time
Min.
6.0
1.7
1.7
2.0
0.5
Max.
Min.
Max.
Min.
10
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.5
1.9
1.9
2.5
0.5
Clock HIGH
3.5
3.5
2.5
0.5
tCL
Clock LOW
tAS
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
tAH
tCO
3.5
4.0
5.5
tDOH
tADS
tADH
tWES
1.5
2.0
0.5
2.0
2.0
2.5
0.5
2.5
2.0
2.5
0.5
2.5
BWE, GW, BW[1:0] Set-Up Before CLK
Rise
tWEH
tADVS
tADVH
tDS
BWE, GW, BW[1:0] Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
0.5
2.0
0.5
2.0
0.5
2.0
0.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Select Set-Up
tDH
tCES
tCEH
tCHZ
tCLZ
Chip Select Hold After CLK Rise
Clock to High-Z[12]
Clock to Low-Z[12]
OE HIGH to Output High-Z[12, 13]
OE LOW to Output Low-Z[12, 13]
OE LOW to Output Valid[12]
3.5
3.5
3.5
3.5
3.5
4.0
3.5
5.5
5.5
0
0
0
0
0
0
tEOHZ
tEOLZ
tEOV
Notes:
10. Input waveform should have a slew rate of 1 V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads.
12.
tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ
.
Document #: 38-05140 Rev. **
Page 9 of 17
CY7C1327B
Switching Waveforms
Write Cycle Timing[14, 15]
Single Write
Burst Write
Pipelined Write
t
Unselected
CH
t
CYC
CLK
t
ADH
t
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
ADSC
ADV
t
ADH
t
ADSC initiated write
ADS
t
t
ADVH
ADVS
t
ADV Must Be Inactive for ADSP Write
WD2
AS
WD3
ADD
GW
WE
WD1
t
AH
t
WH
t
WH
t
WS
t
WS
t
t
CES
CEH
CE masks ADSP
1
CE
1
t
t
CEH
CES
Unselected with CE
2
CE
2
CE
3
t
CES
t
CEH
OE
t
DH
t
DS
High-Z
High-Z
Data
In
3a
2a
= UNDEFINED
1a
2b
2c
2d
= DON’T CARE
Notes:
14. WE is the combination of BWE, BW[1:0], and GW to define a write cycle (see Write Cycle Description table).
15. WDx stands for Write Data to Address X.
Document #: 38-05140 Rev. **
Page 10 of 17
CY7C1327B
Switching Waveforms (continued)
Read Cycle Timing[14, 16]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
RD1
RD3
RD2
tAH
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
OE
tCES
tEOV
tCEH
tOEHZ
tDOH
tCO
Data Out
2c
1a
2d
3a
2a
2b
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
16. RDx stands for Read Data from Address X.
Document #: 38-05140 Rev. **
Page 11 of 17
CY7C1327B
Switching Waveforms (continued)
Read/Write Cycle Timing[14, 15, 16, 17]
Single Read
tCYC
Single Write
tCH
Unselected
Burst Read
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADS
tADVS
tADH
tAS
tADVH
WD2
ADD
RD1
RD3
tAH
GW
WE
CE1
tWS
tWS
tWH
tCES
tCEH
tWH
CE1 masks ADSP
CE2
CE3
tCES
tCEH
tEOV
tCES
tCEH
OE
tEOHZ
tDS
tDH
tDOH
See Note 17
2a
tEOLZ
tCO
3b
Out
3c
Out
3a
Out
3d
Out
Data In/Out
1a
2a
Out
Out
In
tCHZ
= UNDEFINED
= DON’T CARE
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
Document #: 38-05140 Rev. **
Page 12 of 17
CY7C1327B
Switching Waveforms (continued)
Pipeline Timing[18, 19]
tCYC
tCL
tCH
CLK
tAS
WD1
WD2
WD3
WD4
RD1
RD2
RD3
RD4
ADD
tADS
tADH
ADSC initiated Reads
ADSC
ADSP
ADV
ADSP initiated Reads
tCEH
tCES
CE1
CE
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tCLZ
Data In/Out
1a
In
1a
2a
3a
4a
2a
In
3a
In
4a
Out Out Out Out
In
tCO
tDOH
Back to Back Reads
tCHZ
= UNDEFINED
= DON’T CARE
Notes:
18. Device originally deselected.
19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Document #: 38-05140 Rev. **
Page 13 of 17
CY7C1327B
Switching Waveforms (continued)
ZZ Mode Timing[20, 21]
CLK
ADSP
HIGH
ADSC
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
IDD
IDD(active)
tZZREC
IDDZZ
I/Os
Three-state
Notes:
20. Device must be deselected when entering “ZZ” mode. See Cycle Description table for all possible signal conditions to deselect the device.
21. I/Os are in three-state when exiting “ZZ” sleep mode.
Document #: 38-05140 Rev. **
Page 14 of 17
CY7C1327B
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Package Type
100-Lead Thin Quad Flat Pack
119-Ball BGA
166
CY7C1327B-166AC
CY7C1327B-166BGC
CY7C1327B-133AC
CY7C1327B-133BGC
CY7C1327B-133AI
CY7C1327B-133BGI
CY7C1327B-100AC
CY7C1327B-100BGC
CY7C1327B-100AI
CY7C1327B-100BGI
A101
BG119
A101
Commercial
Commercial
Industrial
133
100
100-Lead Thin Quad Flat Pack
119-Ball BGA
BG119
A101
100-Lead Thin Quad Flat Pack
119-Ball BGA
BG119
A101
100-Lead Thin Quad Flat Pack
119-Ball BGA
Commercial
Industrial
BG119
A101
100-Lead Thin Quad Flat Pack
119-Ball BGA
BG119
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05140 Rev. **
Page 15 of 17
CY7C1327B
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
Document #: 38-05140 Rev. **
Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1327B
Document Title: CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM
Document Number: 38-05140
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
109884
09/10/01
SZV
Change from Spec number: 38-00935 to 38-05140
Document #: 38-05140 Rev. **
Page 17 of 17
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