CY7C1327F_技术文档

CY7C1327F

4-Mb (256K x 18) Pipelined Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• 256K ×18 common I/O architecture

• 3.3V core power supply

• 3.3V / 2.5V I/O operation

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

The CY7C1327F SRAM integrates 262,144 x 18 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

2

Control inputs (

,

and

ADSC ADSP

), Write Enables

ADV

(

, and

), and Global Write (

BWE

). Asynchronous

GW

BW_[A:B]

inputs include the Output Enable ( ) and the ZZ pin.

OE

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

• Provide high-performance 3-1-1-1 access rate

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

• User-selectable burst counter supporting Intel^

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

controlled by the byte write control inputs.

when active

GW

causes all bytes to be written.

LOW

The CY7C1327F operates from a +3.3V core power supply

while all outputs also operate with a +3.3V or a +2.5V supply.

• Offered in JEDEC-standard 100-pin TQFP and 119 Ball

All

inputs

and

outputs

are

JEDEC-standard

BGA packages.

JESD8-5-compatible.

• “ZZ” Sleep Mode Option

Logic Block Diagram

ADDRESS

A0, A1, A

REGISTER

A[1:0]

2

MODE

Q1

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

Q0

ADSC

ADSP

DQB,DQP

B

DQB,DQP

WRITE REGISTER

B

WRITE DRIVER

OUTPUT

BUFFERS

BW

B

A

DQs

DQP

OUTPUT

REGISTERS

SENSE

AMPS

MEMORY

ARRAY

A

B

DQA,DQP

A

E

DQA,DQP

WRITE REGISTER

A

WRITE DRIVER

BW

BWE

GW

INPUT

REGISTERS

ENABLE

REGISTER

CE1

CE2

PIPELINED

ENABLE

CE3

OE

ZZ

SLEEP

CONTROL

1

Note:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05216 Rev. *B

Revised December 12, 2003

CY7C1327F

Selection Guide

250 MHz

2.6

225 MHz

2.6

200 MHz

2.8

166 MHz

3.5

133 MHz

4.0

100 MHz

Unit

ns

mA

Maximum Access Time

Maximum Operating Current

4.5

205

40

325

40

290

40

265

40

240

40

225

40

Maximum CMOS Standby

Current

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Pin Configurations

NC

A

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

2

NC

3

V_DDQ

V_SS

NC

V_DDQ

V_SS

NC

4

5

6

NC

DQP_A

DQ_A

V_SS

V_DDQ

DQ_A

V_SS

NC

7

DQ_B

V_SS

V_DDQ

DQ_B

8

9

10

11

12

13

14

15

16

NC

BYTE B

BYTE A

V_DD

100-pin TQFP

CY7C1327F

NC

V_DD

ZZ

V_SS

17

18

19

20

21

22

23

24

25

26

27

28

29

30

DQ_B

DQ_A

V_DDQ

V_SS

DQ_A

NC

DQ_B

V_DDQ

V_SS

DQ_B

DQP_B

NC

V_SS

V_DDQ

NC

V_DDQ

NC

Document #: 38-05216 Rev. *B

Page 2 of 17

CY7C1327F

Pin Configurations

119-ball BGA

2

A

CE₂

A

1

3

A

4

5

A

6

A

CE₃

A

7

V_DDQ

NC

ADSP

ADSC

V_DD

V_DDQ

NC

A

B

C

D

E

F

G

H

J

A

DQ_B

NC

V_DDQ

NC

DQ_B

NC

DQ_B

NC

V_DD

V_SS

BW_B

V_SS

NC

V_SS

NC

CE₁

OE

V_SS

V_ss

V_SS

NC

V_SS

DQP_A

NC

DQ_A

NC

DQ_A

V_DD

NC

DQ_A

V_DDQ

DQ_A

NC

V_DDQ

DQ_A

NC

ADV

DQ_B

V_DDQ

NC

GW

V_DD

CLK

K

DQ_B

L

M

N

DQ_B

V_DDQ

DQ_B

NC

DQ_B

NC

V_ss

V_SS

NC

BWE

A1

BW_A

V_SS

DQ_A

NC

DQ_A

NC

V_DDQ

NC

P

R

T

NC

DQP_B

A

V_SS

MODE

A

A0

V_DD

NC

V_SS

NC

A

NC

A

DQ_A

NC

ZZ

V_DDQ

NC

V_DDQ

U

Document #: 38-05216 Rev. *B

Page 3 of 17

CY7C1327F

Pin Definitions

Name

TQFP

BGA

I/O

Description

A₀, A₁, A

37,36,

P4,N4,A2,

Input-

Address Inputs usedto select one of the 256K address locations. Sampled

32,33,34, C2,R2,T2, Synchronous at the rising edge of the CLK if ADSP or

ADSC is active LOW, and CE₁,

35,44,45, A3,B3,C3,

46,47,48, T3,A5,B5,

49,50,80, C5,T5,A6,

81,82,99, C6,R6,T6

100

CE₂, and CE₃are sampled active. A1, A0 feed the 2-bit counter.

93,94

L5,G3

Input-

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct

BW_A,BW_B

GW

Synchronous byte writes to the SRAM. Sampled on the rising edge of CLK.

88

H4

Input-

Global Write Enable Input, active LOW. When asserted LOW on the

Synchronous rising edge of CLK, a global write is conducted (ALL bytes are written,

regardless of the values on BW_[A:B]and BWE).

87

89

M4

K4

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of

BWE

CLK

Synchronous CLK. This signal must be asserted LOW to conduct a byte write.

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also

used to increment the burst counter when ADV is asserted LOW, during

a burst operation.

98

E4

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.

CE₁

CE

Synchronous Usedinconjunctionwith

and

to select/deselect the device.

CE₃ADSP

2

is ignored if CE₁is HIGH.

CE₂

CE₃

97

92

B2

B6

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.

Synchronous Used in conjunction with

and to select/deselect the device.

CE₁

CE₃

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.

Synchronous Used in conjunction with CE and CE to select/deselect the device.

Not

1

2

connected for BGA. Where referenced, CE₃is assumed active throughout

this document for BGA.

86

F4

Input-

Output Enable, asynchronous input, active LOW. Controls the

OE

Asynchronous direction of the I/O pins. WhenLOW, the I/O pins behave as outputs. When

deasserted HIGH, I/O pins are three-stated, and act as input data pins.

OE is masked during the first clock of a read cycle when emerging from a

deselected state.

83

84

G4

A4

Input-

Advance Input signal, sampled on the rising edge of CLK, active

ADV

Synchronous LOW. When asserted, it automatically increments the address in a burst

cycle.

Input-

Address Strobe from Processor, sampled on the rising edge of CLK,

ADSP

Synchronous active LOW. When asserted LOW, A is captured in the address registers.

A1, A0 are also loaded into the burst counter. When

and

are

is

ADSP

ADSC

both asserted, only

deasserted HIGH.

is recognized.

ASDP

is ignored when

ADSP

CE₁

ZZ

64

85

T7

B4

Input-

ZZ “sleep” Input, active HIGH. This input, when High places the device

Asynchronous in a non-time-critical “sleep” condition with data integrity preserved. For

normal operation, this pin has to be LOW or left floating. ZZ pin has an

internal pull-down.

Input-

Synchronous active LOW. When asserted LOW, A is captured in the address registers.

A1, A0 are also loaded into the burst counter. When and are

Address Strobe from Controller, sampled on the rising edge of CLK,

ADSC

ADSP

ADSC

both asserted, only

is recognized.

ADSP

DQ_A,

DQ_B

58,59,62, F6,H6,L6,

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data

63,68,69, N6,E7,G7, Synchronous register that is triggered by the rising edge of CLK. As outputs, they deliver

72,73

K7,P7

the data contained in the memory location specified by “A” during the

previous clock rise of the read cycle. The direction of the pins is controlled

8,9,12,13, D1,H1,L1,

18,19,22, N1,E2,G2,

by

. When

OE

is asserted LOW, the pins behave as outputs. When

OE

23

K2,M2,

D6,P2

HIGH, DQs and DQP_[A:B]are placed in a three-state condition.

DQP_A,

DQP_B

74,24

Document #: 38-05216 Rev. *B

Page 4 of 17

CY7C1327F

Pin Definitions (continued)

Name

V_DD

TQFP

15,41,65, J2,C4,J4, Power Supply Power supply inputs to the core of the device.

91 R4,J6

BGA

I/O

Description

V_SS

5,10,17, D3,E3,F3,

21,26,40, H3,K3,L3,

55,60,67, M3,N3,P3,

71,76,90 D5,E5,F5,

G5,H5,K5,

Ground

Ground for the device.

M5,N5,P5

V_DDQ

MODE

NC

4,11,20, A1,F1,J1,

I/O Ground Ground for the I/O circuitry.

27,54,61, M1,U1,A7,

70,77

31

F7,J7,M7,

U7

R3

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence.

When tied to V_DDor left floating selects interleaved burst sequence. This

is a strap pin and should remain static during device operation. Mode Pin

has an internal pull-up.

1,2,3,6,7, B1,C1,E1,

14,16,25, G1,K1,P1,

28,29,30, R1,T1,D2,

38,39,42, F2,H2,L2,

43,51,52, N2,U2,J3,

53,56,57, U3,D4,L4,

66,75,78, T4,U4,J5,

79,95,96 U5,E6,G6,

K6,M6,P6,

No Connects. Not internally connected to the die

U6,B7,C7,

D7,H7,L7,

N7,R5,R7

Single Read Accesses

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

CE₁, CE₂, CE₃are all asserted active, and (3) the Write

signals (GW, BWE) are all deserted HIGH. ADSP is ignored if

The CY7C1327F supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW_[A:B]) inputs. A Global Write

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. ADSP is ignored if

CE₁is HIGH.

CE₁is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the Address

Register while being presented to the memory array. The

corresponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within tco if OE is active LOW. The only exception

occurs when the SRAM is emerging from a deselected state

to a selected state, its outputs are always three-stated during

the first cycle of the access. After the first cycle of the access,

the outputs are controlled by the OE signal. Consecutive

single Read cycles are supported. Once the SRAM is

deselected at clock rise by the chip select and either ADSP or

ADSC signals, its output will three-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE₁, CE₂, CE₃are all asserted active. The address

presented to A is loaded into the address register and the

address advancement logic while being delivered to the

memory array. The Write signals (GW, BWE, and BW_[A:B]) and

ADV inputs are ignored during this first cycle.

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

Document #: 38-05216 Rev. *B

Page 5 of 17

CY7C1327F

data presented to the DQ inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the Write operation is controlled by BWE and BW_[A:B]

signals. The CY7C1327F provides Byte Write capability that is

described in the Write Cycle Descriptions table. Asserting the

Byte Write Enable input (BWE) with the selected Byte Write

(BW_[A:B]) input, will selectively write to only the desired bytes.

Bytes not selected during a Byte Write operation will remain

unaltered. A synchronous self-timed Write mechanism has

been provided to simplify the Write operations.

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both Read and Write burst operations are supported.

Sleep Mode

Because the CY7C1327F is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

to the DQ inputs. Doing so will three-state the output drivers.

As a safety precaution, DQs are automatically three-stated

whenever a Write cycle is detected, regardless of the state of

OE.

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

Single Write Accesses Initiated by ADSC

t

he “sleep” mode. CE₁, CE₂, CE₃, ADSP, and ADSC must

ADSC Write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deserted HIGH, (3) CE₁, CE₂, CE₃are all asserted active, and

(4) the appropriate combination of the Write inputs (GW, BWE,

and BW_[A:B]) are asserted active to conduct a Write to the

desired byte(s). ADSC-triggered Write accesses require a

single clock cycle to complete. The address presented to A is

loaded into the address register and the address

advancement logic while being delivered to the memory array.

The ADV input is ignored during this cycle. If a global Write is

conducted, the data presented to DQ is written into the corre-

sponding address location in the memory core. If a Byte Write

is conducted, only the selected bytes are written. Bytes not

selected during a Byte Write operation will remain unaltered.

A synchronous self-timed Write mechanism has been

provided to simplify the Write operations.

remain inactive for the duration of t_ZZRECafter the ZZ input

returns LOW.

Interleaved Burst Address Table (MODE =

Floating or V_DD

)

First

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

Address

A1, A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Linear Burst Address Table (MODE = GND)

Because the CY7C1327F is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

to the DQ inputs. Doing so will three-state the output drivers.

As a safety precaution, DQs are automatically three-stated

whenever a Write cycle is detected, regardless of the state of

OE.

First

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

Address

A1, A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

Burst Sequences

The CY7C1327F provides a two-bit wraparound counter, fed

by A1, A0, that implements either an interleaved or linear burst

ZZ Mode Electrical Characteristics

Parameter

I_DDZZ

t_ZZS

Description

Snooze mode standby current

Device operation to ZZ

Test Conditions

ZZ > V_DD– 0.2V

Min.

Max.

40

2t_CYC

Unit

mA

ns

t_ZZREC

t_ZZI

t_RZZI

ZZ recovery time

ZZ active to snooze current

ZZ Inactive to exit snooze current

ZZ < 0.2V

This parameter is sampled

2t_CYC

0

ns

2t_CYC

Document #: 38-05216 Rev. *B

Page 6 of 17

CY7C1327F

Truth Table^{[ 2, 3, 4, 5, 6]}

Next Cycle

Unselected

Begin Read

Continue Read Next

Suspend Read Current

Begin Write

Continue Write Next

Suspend Write Current

Add. Used

None

External

ZZ

L

H

CE₂

X

L

X

L

DQ

CE₃

X

CE₁

H

L

X

H

X

H

X

H

L

X

H

X

H

X

ADSP

X

ADSC

ADV

X

OE

X

WRITE

L

three-state X

three-state Read

DQ

three-state Read

DQ Read

three-state Read

DQ Read

three-state Read

DQ Read

three-state Write

three-state X

H

X

H

X

L

H

L

X

L

X

L

X

L

H

X

H

X

H

L

H

L

H

L

H

X

H

X

L

H

X

H

X

H

X

H

X

H

X

L

X

H

X

Read

H

L

Current

External

X

ZZ “Sleep”

None

Truth Table for Read/Write^[2]

Function

BW_B

BW_A

GW

BWE

Read

H

L

H

L

X

H

L

H

L

H

L

X

Write Byte A – (DQ_Aand DQP_A)

Write Byte B – (DQ_Band DQP_B)

Write Bytes B, A

Write All Bytes

X

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE = L when any one or more Byte Write enable signals (BW , BW ) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BW , BW ),

A

B

A

B

BWE, GW = H.

4. The DQ pins are controlled by the current cycle and the

signal.

is asynchronous and is not sampled with the clock.

OE

5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW

. Writes may occur only on subsequent clocks

[A: B]

after the

or with the assertion of

. As a result,

must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state.

OE

is

ADSC

OE

ADSP

a don't care for the remainder of the write cycle.

6.

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when

OE

is

OE

.

is active (LOW)

inactive or when the device is deselected, and all data bits behave as output when

OE

Document #: 38-05216 Rev. *B

Page 7 of 17

CY7C1327F

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

Static Discharge Voltage.......................................... > 2001V

(Above which the useful life may be impaired. For user guide-

(per MIL-STD-883, Method 3015)

lines, not tested.)

Latch-up Current.................................................... > 200 mA

Storage Temperature .................................–65°C to +150°C

Operating Range

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Ambient

Range

Temperature

V_DD

V_DDQ

Supply Voltage on V_DDRelative to GND........ –0.5V to +4.6V

Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V –5%

DC Voltage Applied to Outputs

to V_DD

in three-state....................................... –0.5V to V_DDQ+ 0.5V

Industrial

–40°C to +85°C

DC Input Voltage....................................–0.5V to V_DD+ 0.5V

Electrical Characteristics Over the Operating Range ^{[7, 8]}

Parameter

V_DD

V_DDQ

V_OH

Description

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

Test Conditions

Min.

3.135

2.375

2.4

Max.

3.6

V_DD

Unit

V

V_DDQ= 3.3V, V_DD= Min., I_OH= –4.0 mA

V_DDQ= 2.5V, V_DD= Min., I_OH= –2.0 mA

V_DDQ= 3.3V, V_DD= Min., I_OL= 8.0 mA

_DDQ= 2.5V, V_DD= Min., I_OL= 2.0 mA

V_DDQ= 3.3V

_DDQ= 2.5V

2.0

V_OL

V_IH

V_IL

I_X

Output LOW Voltage

Input HIGH Voltage^[7]

Input LOW Voltage^[7]

0.4

V_DD+ 0.3V

0.8

V

2.0

1.7

–0.3

–5

V

V_DDQ= 3.3V

V_DDQ= 2.5V

GND ≤ V_I≤ V_DDQ

V

µA

0.7

5

Input Load Current

except ZZ and MODE

Input Current of MODE Input = V_SS

Input = V_DD

–30

–5

µA

5

Input Current of ZZ

Input = V_SS

Input = V_DD

30

5

I_OZ

I_DD

Output Leakage Current GND ≤ V_I≤ V_DDQ,Output Disabled

–5

V_DDOperating Supply V_DD= Max.,

4-ns cycle,250MHz

325

290

265

240

225

205

120

115

110

100

90

mA

Current

I_OUT= 0 mA,

4.4-ns cycle,225MHz

5-ns cycle,200MHz

6-ns cycle,166MHz

7.5-ns cycle,133MHz

10-ns cycle,100MHz

4-ns cycle,250MHz

4.4-ns cycle,225MHz

5-ns cycle,200MHz

6-ns cycle,166MHz

7.5-ns cycle,133MHz

10-ns cycle,100MHz

All speeds

f = f_MAX

1/t_CYC

=

I_SB1

Automatic CE

V_DD= Max, Device

Power-down

Deselected, V_IN≥ V_IHor

Current—TTL Inputs

V_IN≤ V_IL

f = f_MAX= 1/t_CYC

80

40

I_SB2

Automatic CE

Power-down

V_DD= Max, Device

Deselected, V_IN≤ 0.3V or

Current—CMOS Inputs V_IN> V_DDQ– 0.3V, f = 0

Shaded areas contain advance information.

Notes:

7. Overshoot: V (AC) < V +1.5V (Pulse width less than t

/2), undershoot: V (AC) > -2V (Pulse width less than t

/2).

IH

DD

CYC

IL

CYC

8. T

: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V

< V

.

DD

Power-up

DD

IH

DD

DDQ

Document #: 38-05216 Rev. *B

Page 8 of 17

CY7C1327F

Electrical Characteristics Over the Operating Range (continued)^{[7, 8]}

Parameter

I_SB3

Description

Automatic CE

Power-down

Test Conditions

Min.

Max.

105

100

95

85

75

Unit

mA

V_DD= Max, Device

4-ns cycle,250MHz

4.4-ns cycle,225MHz

5-ns cycle,200MHz

6-ns cycle,166MHz

7.5-ns cycle,133MHz

10-ns cycle,100MHz

All speeds

Deselected, or V_IN≤ 0.3V

Current—CMOS Inputs or V_IN> V_DDQ– 0.3V

f = f_MAX= 1/t_CYC

65

45

I_SB4

Automatic CE

V_DD= Max, Device

Power-down

Deselected, V_IN≥ V_IHor

Current—TTL Inputs

V_IN≤ V_IL, f = 0

Thermal Resistance^[9]

TQFP

BGA

Parameter

Description

Test Conditions

Package

Unit

Θ_JA

Thermal Resistance

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA / JESD51.

41.83

47.63

°C/W

(Junction to Ambient)

Θ_JC

Thermal Resistance

(Junction to Case)

9.99

11.71

°C/W

Capacitance^[9]

TQFP

BGA

Parameter

Description

Test Conditions

Package Package

Unit

C_IN

C_CLK

C_I/O

Input Capacitance

Clock Input Capacitance

Input/Output Capacitance

T_A= 25°C, f = 1 MHz,

5

7

pF

V

_DD= 3.3V.

_DDQ= 3.3V

V

AC Test Loads and Waveforms

3.3V I/O Test Load

R = 317Ω

3.3V

OUTPUT

ALL INPUT PULSES

90%

V_DD

OUTPUT

90%

10%

Z = 50Ω

0

10%

R = 50Ω

L

GND

5 pF

R = 351Ω

≤ 1ns

V = 1.5V

L

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

2.5V I/O Test Load

R = 1667Ω

2.5V

OUTPUT

R = 50Ω

OUTPUT

ALL INPUT PULSES

90%

V_DD

90%

10%

Z = 50Ω

0

10%

L

GND

≤ 1ns

5 pF

R =1538Ω

≤ 1ns

V = 1.25V

L

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

Notes:

9. Tested initially and after any design or process change that may affect these parameters

Document #: 38-05216 Rev. *B

Page 9 of 17

CY7C1327F

Switching Characteristics Over the Operating Range^{[14, 15]}

250 MHz

225 MHz

200 MHz

166 MHz

133 MHz

100 MHz

Parameter

t_POWER

Description

Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max Unit

V_DD(Typical) to the first^[10]

1

ms

Clock

t_CYC

t_CH

Clock Cycle Time

Clock HIGH

Clock LOW

4.0

1.7

4.4

2.0

5.0

2.0

6.0

2.5

7.5

3.0

10

3.5

ns

t_CL

Output Times

t_CO

Data Output Valid After CLK

2.6

2.8

3.5

4.0

4.5 ns

ns

Rise

t_DOH

Data Output Hold After CLK

1.0

0

1.0

0

1.0

0

2.0

0

2.0

0

2.0

0

Rise

t_CLZ

Clock to Low-Z^{[11, 12, 13]}

Clock to High-Z^{[11, 12, 13]}

ns

4.5 ns

ns

t_CHZ

t_OEV

t_OELZ

2.6

2.8

3.5

4.0

4.5

OE LOW to Output Valid

LOW to Output Low-Z^[11,

OE

0

12, 13]

OE HIGH to Output High-Z^[11,

t_OEHZ

2.6

2.8

3.5

4.0

4.5 ns

12, 13]

Set-up Times

t_AS

Address Set-up Before CLK

0.8

1.2

1.5

ns

Rise

t_ADS

,

ADSC ADSP Set-up Before

CLK Rise

t_ADVS

t_WES

0.8

1.2

1.5

ns

ADV Set-up Before CLK Rise

Set-up

GW, BWE, BW_[A:B]

Before CLK Rise

t_DS

Data Input Set-up Before CLK 0.8

Rise

1.2

1.5

ns

t_CES

Chip Enable Set-Up Before

0.8

CLK Rise

Hold Times

t_AH

t_ADH

Address Hold After CLK Rise 0.4

0.5

ns

0.4

,

Hold After CLK

ADSP ADSC

Rise

t_ADVH

t_WEH

0.4

0.5

ns

ADV Hold After CLK Rise

,

GW BWE BW_[A:B]Hold After

CLK Rise

t_DH

Data Input Hold After CLK

Rise

0.4

0.5

ns

t_CEH

Chip Enable Hold After CLK

Rise

Shaded areas contain advance information.

Notes:

10. This part has a voltage regulator internally; t

can be initiated.

is the time that the power needs to be supplied above V (minimum) initially before a read or write operation

DD

POWER

11. t

, t

,t

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

CHZ CLZ OELZ

OEHZ

12. At any given voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same

CLZ

OEHZ

OELZ

CHZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

13. This parameter is sampled and not 100% tested.

14. Timing references level is 1.5V when V

= 3.3V and is 1.25V when V

= 2.5V on all data sheets.

DDQ

15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05216 Rev. *B

Page 10 of 17

CY7C1327F

Switching Waveforms

Read Cycle Timing^[16]

t

CYC

CLK

t

CL

CH

t

ADH

ADS

ADSP

ADSC

t

ADH

ADS

t

AH

AS

A1

A2

A3

ADDRESS

Burst continued with

new base address

t

WEH

WES

GW, BWE,

BW^[A:B]

Deselect

cycle

t

CEH

CES

CE

t

ADVH

ADVS

ADV

OE

ADV

suspends

burst.

t

OEV

CO

t

OEHZ

t

OELZ

t

CHZ

DOH

t

CLZ

t

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Q(A1)

Data Out (Q)

High-Z

CO

Burst wraps around

to its initial state

Single READ

BURST READ

DON’T CARE

UNDEFINED

Notes:

16. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.

1

2

3

1

2

3

17.

Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW

LOW.

[A:B]

Document #: 38-05216 Rev. *B

Page 11 of 17

CY7C1327F

Switching Waveforms (continued)

Write Cycle Timing^{[16, 17]}

t

CYC

CLK

t

CL

CH

t

ADH

ADS

ADSP

ADSC extends burst

t

ADH

ADS

t

ADH

ADS

ADSC

t

AH

AS

A1

A2

A3

ADDRESS

Byte write signals are

ignored for first cycle when

ADSP initiates burst

t

WEH

WES

BWE,

BW[A :B]

t

WEH

WES

GW

CE

t

CEH

CES

t

ADVH

ADVS

ADV

OE

ADV suspends burst

t

DH

DS

Data In (D)

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A1)

High-Z

t

OEHZ

Data Out (Q)

BURST READ

Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Document #: 38-05216 Rev. *B

Page 12 of 17

CY7C1327F

Switching Waveforms (continued)

Read/Write Cycle Timing[16, 18, 19]

t

CYC

CLK

t

CL

CH

t

ADH

ADS

ADSP

ADSC

t

AH

AS

A1

A2

A3

A4

A5

A6

ADDRESS

t

WEH

WES

BWE,

BW^[A:B]

t

CEH

CES

CE

ADV

OE

t

DH

t

CO

DS

t

OELZ

Data In (D)

High-Z

D(A3)

D(A5)

D(A6)

t

OEHZ

CLZ

Data Out (Q)

Q(A1)

Q(A2)

Q(A4)

Q(A4+1)

Q(A4+2)

Q(A4+3)

Back-to-Back READs

Single WRITE

BURST READ

Back-to-Back

WRITEs

DON’T CARE

UNDEFINED

Notes:

18.

19.

.

The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by

ADSP or ADSC

GW is HIGH.

Document #: 38-05216 Rev. *B

Page 13 of 17

CY7C1327F

Switching Waveforms (continued)

ZZ Mode Timing ^{[20, 21]}

CLK

t

ZZ

ZZREC

ZZ

t

ZZI

I

SUPPLY

I

DDZZ

t

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Ordering Information

Speed

Package

Name

Operating

Range

(MHz)

Ordering Code

Package Type

250

CY7C1327F-250AC

CY7C1327F-250BGC

CY7C1327F-250AI

CY7C1327F-250BGI

CY7C1327F-225AC

CY7C1327F-225BGC

CY7C1327F-225AI

CY7C1327F-225BGI

CY7C1327F-200AC

CY7C1327F-200BGC

CY7C1327F-200AI

CY7C1327F-200BGI

CY7C1327F-166AC

CY7C1327F-166BGC

CY7C1327F-166AI

CY7C1327F-166BGI

CY7C1327F-133AC

CY7C1327F-133BGC

CY7C1327F-133AI

CY7C1327F-133BGI

A101

BG119

A101

BG119

A101

BG119

A101

BG119

A101

BG119

A101

BG119

A101

BG119

A101

BG119

A101

100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)