CY7C1329_04 [CYPRESS]
64K x 32 Synchronous-Pipelined Cache RAM; 64K ×32的同步流水线高速缓存RAM
| 型号： | CY7C1329_04 |
| 厂家： | 
CYPRESS |
| 描述： | 64K x 32 Synchronous-Pipelined Cache RAM |
| 文件： | 总15页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1329
64K x 32 Synchronous-Pipelined Cache RAM
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
Features
• Supports 133-MHz bus for Pentium and PowerPC
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 4.2 ns (133-MHz
device).
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 64K x 32 common I/O architecture
• Single 3.3V power supply
The CY7C1329 supports either the interleaved burst
sequence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input. A 2-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the four Byte Write
Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides
all Byte Write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed Write
circuitry.
• Fast clock-to-output times
— 4.2 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
• User-selectable burst counter supporting Intel®
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-lead TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a Read cycle when emerging from a deselected
state.
Functional Description
The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
MODE
Logic Block Diagram
2
(A
)
[1:0]
Q
Q
CLK
ADV
0
BURST
COUNTER
CE
ADSC
1
CLR
ADSP
Q
14
16
ADDRESS
REGISTER
CE
D
64K × 32
Memory
Array
A
[15:0]
GW
16
14
Q
Q
Q
Q
DQ[31:24]
D
BYTEWRITE
REGISTERS
BWE
BW
3
D
D
D
DQ[23:16]
BYTEWRITE
REGISTERS
BW
2
DQ[15:8]
BYTEWRITE
REGISTERS
BW
1
DQ[7:0]
BYTEWRITE
REGISTERS
BW
0
32
32
CE
1
CE
D
ENABLE
2
Q
CE
REGISTER
CE
3
CLK
D
Q
OUTPUT
INPUT
ENABLE DELAY
REGISTER
CLK
REGISTERS
CLK
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[31:0]
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05279 Rev. *B
Revised March 31, 2004
CY7C1329
Pin Configuration
100-pin TQFP
NC
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ15
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
2
3
4
5
6
7
BYTE2
BYTE1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
NC
VDD
VSS
CY7C1329
ZZ
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
NC
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
NC
BYTE3
BYTE0
Selection Guide
7C1329-133
7C1329-100
Unit
ns
mA
mA
Maximum Access Time
4.2
325
5
5.5
310
5
Maximum Operating Current
Maximum CMOS Standby Current
Commercial
Commercial
Document #: 38-05279 Rev. *B
Page 2 of 15
CY7C1329
Pin Definitions
Pin Number
Name
I/O
Description
49–44, 81,82, A[15:0]
Input-
Address Inputs used to select one of the 64K address locations. Sampled at
99, 100, 32–37
Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampled active. A[1:0] feed the 2-bit counter.
96–93
88
BW[3:0]
GW
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes
Synchronous to the SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
Synchronous of CLK, a global Write is conducted (ALL bytes are written, regardless of the values
on BW[3:0] and BWE).
87
89
98
97
92
86
BWE
CLK
CE1
CE2
CE3
OE
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
Synchronous signal must be asserted LOW to conduct a Byte Write.
Input-Clock Clock input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunc-
Input-
Synchronous tion with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the
Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a Read cycle when emerging from a deselected state.
83
84
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When
Synchronous asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
85
64
ADSC
ZZ
Input-
Address Strobe from Controller, sampled on the rising edge of CLK. When
Synchronous asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved.
29, 28, 25–22, DQ[31:0]
19, 18,13,12,
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A[15:0] during the previous clock rise of the Read
cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQ[31:0] are placed in a three-state condition.
9–6, 3, 2, 79,
78, 75–72, 69,
68, 63, 62
59–56, 53, 52
15, 41, 65, 91 VDD
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V
power supply.
17, 40, 67, 90 VSS
4, 11, 20, 27, VDDQ
54, 61, 70, 77
Ground
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
I/O Power
Supply
5, 10, 21, 26, VSSQ
I/O Ground Ground for the I/O circuitry. Should be connected to ground of the system.
55, 60, 71, 76
31
MODE
Input-
Static
Selects burst order. When tied to GND selects linear burst sequence. When tied
to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation.
1, 14, 16, 30, NC
38, 39, 42, 43,
50, 51, 66, 80
–
No Connects.
Document #: 38-05279 Rev. *B
Page 3 of 15
CY7C1329
Write signals (GW, BWE, and BW0–BW3) and ADV inputs are
Introduction
Functional Overview
ignored during this first cycle.
ADSP triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ[31:0] inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the Write operation is controlled by BWE and BW[3:0]
signals. The CY7C1329 provides Byte Write capability that is
described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
(BW[3:0]) input will selectively write to only the desired bytes.
Bytes not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1329 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[31:0] inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ[31:0] are automatically
three-stated whenever a Write cycle is detected, regardless of
the state of OE.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 4.2 ns
(133-MHz device).
The CY7C1329 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or
the Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BW[3:0]) are asserted active to conduct a Write to
the desired byte(s). ADSC triggered Write accesses require a
single clock cycle to complete. The address presented to
A[15:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQ[31:0] is written into the
corresponding address location in the RAM core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A Synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
(A[15:0]) is stored into the address advancement logic and the
Address Register while being presented to the memory core.
The corresponding data is allowed to propagate to the input of
the Output Registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 4.2 ns (133-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always three-stated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will three-state immediately.
Because the CY7C1329 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[31:0] inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ[31:0] are automatically
three-stated whenever a Write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1329 provides a two-bit wraparound counter, fed by
A
[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The address presented
to A[15:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Document #: 38-05279 Rev. *B
Page 4 of 15
CY7C1329
Sleep Mode
Interleaved Burst Sequence
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
First
Second
Third
Fourth
Address
Address
Address
Address
A[1:0]
00
01
10
A[1:0]
01
00
11
A[1:0]
10
11
00
A[1:0]
11
10
01
11
10
01
00
Linear Burst Sequence
First
Second
Third
Fourth
Address
Address
Address
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby cur- ZZ > VDD − 0.2V
3
mA
rent
tZZS
tZZREC
Device operation to ZZ
ZZ recovery time
ZZ > VDD − 0.2V
2tCYC
ns
ns
ZZ < 0.2V
2tCYC
Cycle Descriptions [1,2,3]
Next Cycle
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Add. Used
None
None
None
None
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CE3
X
1
X
1
X
0
0
X
X
X
X
X
X
X
X
X
CE2
X
X
0
X
0
CE1
1
0
0
0
0
0
0
ADSP
ADSC
ADV
X
X
X
X
X
X
X
0
0
0
0
1
OE
X
X
X
X
X
X
X
1
0
1
0
1
DQ
Hi-Z
Write
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
None
External
External
Next
Next
Next
1
1
X
X
X
X
X
X
X
X
X
X
X
1
Next
1
Current
Current
Current
Current
Current
X
X
1
1
X
1
1
1
1
0
1
0
X
Hi-Z
DQ
Hi-Z
Begin Write
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BW
, and GW. See Write Cycle Descriptions table.
[3:0]
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Document #: 38-05279 Rev. *B
Page 5 of 15
CY7C1329
Cycle Descriptions (continued)[1,2,3]
Next Cycle
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “sleep”
Add. Used
Current
External
Next
ZZ
L
L
L
L
L
L
H
CE3
X
0
X
X
X
X
X
CE2
X
1
X
X
X
X
X
CE1
1
0
X
1
X
1
X
ADSP
X
1
1
X
1
ADSC
ADV
1
X
0
0
1
1
X
OE
X
X
X
X
X
X
X
DQ
Hi-Z
Write
Write
Write
Write
Write
Write
Write
X
1
0
1
1
1
1
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Next
Current
Current
None
X
X
Write Cycle Descriptions[4,5,6]
Function
Read
Read
GW
BWE
BW3
BW2
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
BW1
BW0
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
1
1
1
1
11
1
1
1
0
0
0
0
0
0
0
0
X
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
Write Byte 0 – DQ[7:0]
Write Byte 1 – DQ[15:8]
Write Bytes 1, 0
Write Byte 2 – DQ[23:16]
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 - DQ[31:24]
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
0
X
0
X
Write All Bytes
Document #: 38-05279 Rev. *B
Page 6 of 15
CY7C1329
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature ..................................... −65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Range Ambient Temperature[8]
VDD
VDDQ
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
3.3V
3.3V
DC Voltage Applied to Outputs
−5%/+10% −5%/+10%
in High-Z State[7] .....................................−0.5V to VDDQ + 0.5V
DC Input Voltage[7]..................................−0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Description
Power Supply Voltage 3.3V −5%/+10%
Test Conditions
Min.
3.135
3.135
2.4
Max.
3.6
3.6
Unit
V
V
V
V
V
V
µA
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[7]
3.3V −5%/+10%
VDD = Min., IOH = −4.0 mA
VDD = Min., IOL = 8.0 mA
0.4
DDQ + 0.3V
2.0
–0.3
−5
V
0.8
5
Input Load Current
GND ≤ VI ≤ VDDQ
Except ZZ and MODE
Input Current of MODE Input = VSS
Input = VDDQ
–30
–5
µA
µA
µA
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDDQ
30
5
IOZ
IDD
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
−5
VDD Operating Supply VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
325
260
60
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
Automatic CS
Max. VDD, Device Deselected,
Power-down
VIN ≥ VIH or VIN ≤ VIL
50
Current—TTL Inputs
f = fMAX = 1/tCYC
Automatic CS
Power-down
Max. VDD, Device Deselected,
All speeds
5
mA
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
Automatic CS
Power-down
Max. VDD, Device Deselected, or 7.5-ns cycle, 133 MHz
IN ≤ 0.3V or VIN > VDDQ – 0.3V
40
30
mA
mA
V
10-ns cycle, 100 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
ISB4
Automatic CS
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
25
mA
Power-down
Current—TTL Inputs
Notes:
4. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
5. The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[3:0]
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE
is a “don't care” for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive
or when the device is deselected, and DQ = data when OE is active.
7. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
8. T is the case temperature.
A
Document #: 38-05279 Rev. *B
Page 7 of 15
CY7C1329
Capacitance[9]
Parameter
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Max.
Unit
pF
pF
CIN
CCLK
CI/O
4
4
4
VDD = 3.3V,
VDDQ = 3.3V
pF
AC Test Loads and Waveforms
R = 317Ω
3.3V
[10]
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
3.3V
GND
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
5 pF
R = 351Ω
< 3.3 ns
< 3.3 ns
INCLUDING
V = 1.5V
L
JIG AND
SCOPE
(a)
(b)
(c)
Switching Characteristics Over the Operating Range[11,12,13]
-133
-100
Parameter
tCYC
tCH
tCL
tAS
Description
Min.
7.5
1.9
1.9
1.5
0.5
Max.
Min.
10
3.2
3.2
2.5
0.5
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWE, GW, BW[3:0] Set-up Before CLK Rise
BWE, GW, BW[3:0] Hold After CLK Rise
ADV Set-up Before CLK Rise
ADV Hold After CLK Rise
tAH
tCO
4.2
5.0
tDOH
tADS
tADH
tWES
tWEH
tADVS
tADVH
tDS
1.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0
2.0
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
1.5
0
Data Input Set-up Before CLK Rise
Data Input Hold After CLK Rise
Chip Select Set-up
tDH
tCES
tCEH
tCHZ
tCLZ
tEOHZ
tEOLZ
Chip Select Hold After CLK Rise
Clock to High-Z[12]
3.5
3.5
4.2
5
Clock to Low-Z[12]
OE HIGH to Output High-Z[12, 13]
OE LOW to Output Low-Z[12, 13]
OE LOW to Output Valid[12]
5.5
5.0
0
0
tEOV
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Input waveform should have a slew rate of 1V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified I /I and load capacitance. Shown in (a) and (b) of AC Test Loads.
OL OH
EOHZ
12. t
, t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state
CHZ CLZ EOV EOLZ
voltage.
13. At any given voltage and temperature, t
is less than t
and t
is less than t
.
CLZ
EOHZ
EOLZ
CHZ
Document #: 38-05279 Rev. *B
Page 8 of 15
CY7C1329
Switching Waveforms
Write Cycle Timing[14, 15]
Single Write
tCYC
tADH
Burst Write
Pipelined Write
tCH
Unselected
CLK
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADH
tADS
ADSC initiated Write
tADVH
tADVS
tAS
ADV Must Be Inactive for ADSP Write
WD3
ADD
GW
WE
CE1
WD1
WD2
tAH
tWH
tWH
tWS
tWS
tCES
tCEH
CE1 masks ADSP
tCEH
tCES
Unselected with CE2
CE2
CE3
OE
tCES
tCEH
tDH
tDS
High-Z
High-Z
Data-
In
3a
2a
= UNDEFINED
1a
2b
2c
2d
= DON’T CARE
Notes:
14. WE is the combination of BWE, BW
and GW to define a Write cycle (see Write Cycle Descriptions table).
[3:0]
15. WDx stands for Write Data to Address X.
Document #: 38-05279 Rev. *B
Page 9 of 15
CY7C1329
Switching Waveforms (continued)
Read Cycle Timing[14, 16]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated Read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
WE
RD3
RD1
RD2
tAH
tWS
tWS
tWH
tCES
tCEH
tWH
CE1 masks ADSP
CE
1
2
Unselected with CE2
CE
tCES
tCEH
CE
3
tCES
tDOE
tCEH
OE
tOEHZ
tDOH
tCO
Data-
Out
2c
1a
2d
3a
tCHZ
2a
2b
tCLZ
= DON’T CARE
= UNDEFINED
Note:
16. RDx stands for Read Data from Address X.
Document #: 38-05279 Rev. *B
Page 10 of 15
CY7C1329
Switching Waveforms (continued)
Read/Write Cycle Timing[14,15,16, 17]
Single Read
tCYC
Single Write
tCH
Unselected
Burst Read
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADS
tADVS
tADH
tAS
tADVH
WD2
ADD
RD1
RD3
tWS
tAH
GW
WE
tWS
tWH
tCES
tCEH
tWH
CE1 masks ADSP
CE
1
CE
2
3
tCES
tCEH
CE
tDOE
tCES
tCEH
OE
tOEHZ
tDS
3a
tDH
tDOH
See Note 17
tOELZ
tCO
2a
3b
3c
3d
Out
Data-
1a
2a
In
Out
Out
Out
Out
Out
In/Out
TCHZ
= UNDEFINED
= DON’T CARE
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
Document #: 38-05279 Rev. *B
Page 11 of 15
CY7C1329
Switching Waveforms (continued)
Pipeline Timing[18,19]
tCYC
tCL
tCH
CLK
tAS
WD1
WD2
WD3
WD4
RD1
RD2
RD3
RD4
ADD
tADS
tADH
ADSC initiated Reads
ADSC
ADSP initiated Reads
ADSP
ADV
tCEH
tCES
CE
1
CE
tWES
tWEH
WE
ADSP ignored
with CE1 HIGH
OE
tCLZ
Data In/Out
1a
In
1a
2a
3a
4a
2a
In
3a
In
4a
Out Out Out Out
In
tCO
tDOH
Back to Back Reads
tCHZ
= UNDEFINED
= DON’T CARE
Notes:
18. Device originally deselected.
19. CE is the combination of CE and CE . All chip selects need to be active in order to select the device.
2
3
Document #: 38-05279 Rev. *B
Page 12 of 15
CY7C1329
Switching Waveforms (continued)
ZZ Mode Timing[20, 21]
CLK
ADSP
HIGH
ADSC
CE
1
LOW
HIGH
CE
2
CE
ZZ
3
t
ZZS
I
DD
I
(active)
DD
t
ZZREC
I
DDZZ
I/Os
Three-state
Ordering Information
Speed
Package
Operating
Range
Commercial
(MHz)
133
Ordering Code
CY7C1329-133AC
CY7C1329-100AC
CY7C1329-100AI
Name
A101
A101
A101
Package Type
100-lead Thin Quad Flat Pack
100-lead Thin Quad Flat Pack
100-lead Thin Quad Flat Pack
100
Industrial
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device.
21. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05279 Rev. *B
Page 13 of 15
CY7C1329
Package Diagram
100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05279 Rev. *B
Page 14 of 15
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1329
Document History Page
Document Title: CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM
Document Number:38-05279
REV.
ECN NO Issue Date Orig. of
Description of changes
Change
**
*A
*B
114388
114499
212291
03/25/02
04/11/02
See ECN
DSG
GLC
VBL
Changed from Spec number: 38-00561 to 38-05279
Changed to 1.5 set-up
Updated ordering info: added -100AI
Added Industrial to Operating Range section,
delete -75 from AC characteristics table
Document #: 38-05279 Rev. *B
Page 15 of 15
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