CY7C1340F-200AXC [CYPRESS]
Standard SRAM, 128KX32, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | CY7C1340F-200AXC |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX32, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1340F
4-Mb (128K x 32) Pipelined DCD Sync SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
• 128K × 32-bit common I/O architecture
• 3.3V –5% and +10% core power supply (VDD
)
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
2
• 3.3V / 2.5V I/O supply (VDDQ
)
Control inputs (
,
,
), Write Enables
). Asynchronous
and
ADV
ADSC ADSP
(
, and
), and Global Write (
BWE GW
BW[A:D]
• Fast clock-to-output times
inputs include the Output Enable ( ) and the ZZ pin.
OE
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (
) or
ADSP
Address Strobe Controller (
) are active. Subsequent
ADSC
burst addresses can be internally generated as controlled by
the Advance pin ( ).
ADV
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
controlled by the byte write control inputs.
active
GW
LOW
Pentium interleaved or linear burst sequences
This device incorporates an
causes all bytes to be written.
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100-pin TQFP package and pinout
• “ZZ” Sleep Mode option
The CY7C1340F operates from a +3.3V core power supply
while all outputs operate with a +3.3V or a +2.5V supply. All
inputsand outputs are JEDEC-standard JESD8-5-compatible..
Selection Guide
250 MHz
2.6
225 MHz
2.6
200 MHz
2.8
166 MHz
3.5
133 MHz
4.0
100 MHz
4.5
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
325
40
290
40
265
40
240
40
225
40
205
40
mA
mA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05219 Rev. *A
Revised January 19, 2004
[+] Feedback
CY7C1340F
Functional Block Diagram—128Kx32
ADDRESS
A0,A1,A
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
D
DQD
BYTE
BYTE
BW
D
WRITE REGISTER
WRITE DRIVER
DQ
BYTE
WRITE DRIVER
C
DQ
BYTE
WRITE REGISTER
c
MEMORY
ARRAY
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQ
BYTE
WRITE DRIVER
B
E
DQ
BYTE
WRITE REGISTER
B
BW
BW
B
A
DQ
BYTE
WRITE DRIVER
A
DQ
BYTE
WRITE REGISTER
A
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
ZZ
CONTROL
Document #: 38-05219 Rev. *A
Page 2 of 17
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CY7C1340F
Pin Configurations
100-pin TQFP
Top View
NC
1
2
3
4
5
80
79
78
NC
DQc
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
DQc
VDDQ
77
76
75
74
73
72
71
70
69
68
67
VSSQ
DQc
6
7
8
BYTE B
BYTE C
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
9
10
11
12
13
14
15
16
17
VDD
66
65
64
63
62
61
60
CY7C1340F
(128K x 32)
NC
NC
VDD
VSS
ZZ
18
19
20
21
22
23
24
25
26
27
28
29
30
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
59
58
57
56
55
54
53
52
51
BYTE A
BYTE D
DQD
VSSQ
VDDQ
DQD
DQD
NC
Document #: 38-05219 Rev. *A
Page 3 of 17
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CY7C1340F
Pin Descriptions
Pin
A0, A1, A
TQFP
37,36,32,33
Type
Input-
Description
Address Inputs used to select one of the 128K address locations. Sampled at
or is active LOW, and CE , CE , and CE
3
34,35,44,45, Synchronous the rising edge of the CLK if
ADSP ADSC
1
2
46,47,48,49,
50,81,82,99,
100
are sampled active. A[1:0] are fed to the two-bit counter.
BWA, BWB, 93,94,95,96
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
Synchronous
.
BW
to the SRAM. Sampled on the rising edge of CLK
C, BWD
88
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
GW
Synchronous of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW[A:D] and BWE).
87
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
BWE
Synchronous signal must be asserted LOW to conduct a byte write.
CLK
89
98
Input-
Clock
Input-
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
CE1
Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH.
97
92
86
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
CE2
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
CE3
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the
Asynchronous DQ pins. When LOW, the DQ pins behave as outputs. When deasserted HIGH, DQ
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
83
84
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW. When
ADV
Synchronous asserted, it automatically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active
ADSP
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
85
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active
ADSC
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
64
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
ZZ
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal opera-
tion, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs
52,53,56,57,
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
58,59,62,63 Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained
68,69,72,73,
74,75,78,79
2,3,6,7,8,9,
12,13
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a
three-state condition.
18,19,22,23,
24,25,28,29
VDD
VSS
15,41,65,
91
Power Supply Power supply inputs to the core of the device.
17,40,67,
Ground
Ground for the core of the device.
90
VDDQ
4,11,20,27,
54,61,70,77
I/O Power Power supply for the I/O circuitry.
Supply
Document #: 38-05219 Rev. *A
Page 4 of 17
[+] Feedback
CY7C1340F
Pin Descriptions (continued)
Pin
TQFP
Type
Description
VSSQ
5,10,21,26,
I/O Ground Ground for the I/O circuitry.
55,60,71,76
MODE
NC
31
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to VDD or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
No Connects. Not internally connected to the die.
14,16,38,39,
42,43,66,1,
30,51,80
Single Write Accesses Initiated by ADSP
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1340F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and
ignored during this first cycle.
) and ADV inputs are
BW[A:D]
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
Accesses can
Strobe (ADSP)
be initiated with either the Processor Address
or the Controller Address Strobe (ADSC).
then the write operation is controlled by BWE and
BW[A:D]
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
signals. The CY7C1340F provides byte write capability that is
described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
Because the CY7C1340F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQ are automatically three-stated
whenever a write cycle is detected, regardless of the state of
OE.
self-timed write circuitry.
synchronous
Synchronous Chip Selects CE1, CE2, CE3 and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control.
is ignored if
ADSP
is HIGH.
CE1
Single Write Accesses Initiated by ADSC
Single Read Accesses
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive
single read cycles are supported.
and
) are asserted active to conduct a write to the
BW[A:D]
desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQX is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1340F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQX inputs. Doing so will three-state the output drivers.
As a safety precaution, DQX are automatically three-stated
whenever a write cycle is detected, regardless of the state of
OE.
The CY7C1340F is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will three-state immediately
after the next clock rise.
Document #: 38-05219 Rev. *A
Page 5 of 17
[+] Feedback
CY7C1340F
Burst Sequences
Interleaved Burst Address Table
(MODE = Floating or VDD
)
The CY7C1340F provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Both read and write burst operations
are supported.
First
Second
Address
A1, A0
Third
Fourth
Address
A1, A0
Address
A1, A0
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Linear Burst Address Table
(MODE = GND)
Sleep Mode
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Snooze mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
Min.
Max.
40
2tCYC
Unit
mA
ns
tZZ
tZZREC
tZZI
tRZZI
ZZ recovery time
ZZ Active to snooze current
ZZ inactive to exit snooze current
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
2tCYC
0
ns
ns
ns
2tCYC
Document #: 38-05219 Rev. *A
Page 6 of 17
[+] Feedback
CY7C1340F
Truth Table [2, 3, 4, 5, 6]
Address
Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
Operation
DQ
Deselected Cycle, Power Down None
Deselected Cycle, Power Down None
Deselected Cycle, Power Down None
Deselected Cycle, Power Down None
Deselected Cycle, Power Down None
H
L
L
L
L
X
L
L
L
X
L
X
L
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
H
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
ZZ Mode, Power-Down
None
External
External
External
External
External
Next
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
L-H
Three-State
Q
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
L
L-H Three-State
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L-H Three-State
L-H
L-H Three-State
L-H
L-H Three-State
X
X
H
H
X
H
X
X
H
H
X
H
Q
Next
Next
Next
Next
L
L
L
L
Q
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
L-H Three-State
L-H
L-H Three-State
Q
H
X
X
L-H
L-H
D
D
L
Partial Truth Table for Read/Write[2, 7]
Function
GW
H
H
H
H
H
H
H
L
BWE
BWA
X
H
L
H
H
H
L
X
BWB
BWC
BWD
X
H
H
H
H
L
L
X
Read
Read
H
L
L
L
L
L
L
X
X
H
H
L
H
H
L
X
H
H
H
L
H
L
X
Write byte A - DQA
Write byte B - DQB
Write byte C - DQC
Write byte D - DQD
Write all bytes
Write all bytes
X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW = L. WRITE = H when all Byte write enable signals
A
B
C
D
(BW , BW , BW , BW ), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the
signal.
is asynchronous and is not sampled with the clock.
OE
OE
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A:D]
after the
or with the assertion of
. As a result,
must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state.
OE
is
ADSC
OE
ADSP
a don't care for the remainder of the write cycle.
6.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when
OE
OE
is
inactive or when the device is deselected, and all data bits behave as output when
is active (LOW).
OE
7. Table only lists a partial listing of the byte write combinations. Any combination of BW
active.
is valid. Appropriate write will be done based on which byte write is
[A:D]
Document #: 38-05219 Rev. *A
Page 7 of 17
[+] Feedback
CY7C1340F
Static Discharge Voltage............................................>2001V
(per MIL-STD-883,Method 3015)
Latch -up Current.....................................................>200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................... –65°C to +150°
Operating Range
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Range
Commercial
Industrial
Temperature (TA)
0°C to +70°C
VDD
VDDQ
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
3.3V −5%/+10% 2.5V− 5%
DC Voltage Applied to Outputs
to VDD
–40°C to +85°C
in Three-State ..................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Electrical Characteristics Over the Operating Range[8, 9]
Parameter
VDD
VDDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
2.375
2.4
Max.
3.6
VDD
Unit
V
V
V
V
V
V
V
V
VOH
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
DDQ = 2.5V, VDD = Min., IOH = –2.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
DDQ = 2.5V, VDD = Min., IOL = 2.0 mA
V
2.0
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH Voltage[8]
Input LOW Voltage[8]
0.4
0.4
V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
2.0 VDD + 0.3V
1.7 VDD + 0.3V
–0.3
–0.3
–5
0.8
0.7
5
V
V
µA
VDDQ = 2.5V
Input Load Current except ZZ GND ≤ VI ≤ VDDQ
and MODE
Input Current of MODE
Input = VSS
Input = VDD
Input = VSS
–30
–5
µA
µA
µA
5
Input Current of ZZ
Input = VDD
GND ≤ VI ≤ VDDQ, Output Disabled
30
5
µA
µA
IOZ
IDD
Output Leakage Current
–5
VDD Operating Supply Cur-
VDD = Max., IOUT = 0 mA,
4-ns cycle, 250 MHz
325
290
265
240
225
205
120
115
110
100
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
rent
f = fMAX = 1/tCYC
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
ISB1
Automatic CE
V
DD = Max., Device Deselected, 4-ns cycle, 250 MHz
Power-down
V
IN ≥ VIH or VIN ≤ VIL, f = fMAX =
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
Current—TTL Inputs
1/tCYC
80
Shaded areas contain advance information.
Notes:
8. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
9. T
: Assumes a linear ramp from 0v to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
Power-up
DD
IH
DD
DDQ
Document #: 38-05219 Rev. *A
Page 8 of 17
[+] Feedback
CY7C1340F
Electrical Characteristics Over the Operating Range[8, 9]
Parameter
Description
Test Conditions
Min.
Max.
Unit
ISB2
Automatic CE
V
DD = Max., Device Deselected, All speeds
40
mA
Power-down
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs
f = 0
ISB3
Automatic CE
V
DD = Max., Device Deselected, 4-ns cycle, 250 MHz
105
100
95
85
75
mA
mA
mA
mA
mA
mA
mA
Power-down
or VIN ≤ 0.3V or VIN > VDDQ
–
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
Current—CMOS Inputs
0.3V, f = fMAX = 1/tCYC
65
45
ISB4
Automatic CE Power-down
Current—TTL Inputs
VDD = Max., Device Deselected, All speeds
VIN ≥ VIH or VIN ≤ VIL, f = 0
Thermal Characteristics[10]
TQFP
Parameter
Description
Test Conditions
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard test
methodsandproceduresformeasuring
thermal impedance, per EIA / JESD51.
41.83
°C/W
(Junction to Ambient)
ΘJC
Thermal Resistance
9.99
°C/W
(Junction to case)
Capacitance[10]
Parameter
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
Max.
Unit
pF
pF
CIN
CCLK
CI/O
Note:
TA = 25°C, f = 1 MHz,
5
5
5
VDD = 3.3V
V
DDQ = 3.3V
pF
10. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05219 Rev. *A
Page 9 of 17
[+] Feedback
CY7C1340F
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDD
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDD
90%
10%
Z = 50Ω
0
10%
L
GND
≤ 1ns
5 pF
R =1538Ω
≤ 1ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document #: 38-05219 Rev. *A
Page 10 of 17
[+] Feedback
CY7C1340F
[15, 16]
Switching Characteristics Over the Operating Range
250 MHz 225 MHz
200 MHz
166 MHz
133 MHz 100 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
VDD(Typical) to the first Access[11] 1.0
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
1.0
1.0
1.0
1.0
1.0
ms
Clock Cycle Time
Clock HIGH
4.0
1.7
1.7
4.4
2.0
2.0
5.0
2.0
2.0
6.0
2.5
2.5
7.5
3.0
3.0
10
3.5
3.5
ns
ns
ns
Clock LOW
Output Times
tCO
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Data Output Valid After CLK Rise
2.6
2.6
2.8
3.5
4.0
4.5 ns
ns
Data Output Hold After CLK Rise 1.0
1.0
0
1.0
0
2.0
0
2.0
0
2.0
0
Clock to Low-Z[12, 13, 14]
Clock to High-Z[12, 13, 14]
0
ns
2.6
2.6
2.6
2.6
2.8
2.8
3.5
3.5
4.0
4.5
4.5 ns
4.5 ns
ns
OE LOW to Output Valid
LOW to Output Low-Z[12, 13, 14]
0
0
0
0
0
0
OE
2.6
2.6
2.8
3.5
4.0
4.5 ns
OE HIGH to Output
High-Z[12, 13, 14]
Set-up Times
tAS
tADS
Address Set-up Before CLK Rise 0.8
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
,
0.8
ADSC ADSP Set-up Before CLK
Rise
tADVS
tWES
0.8
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ADV Set-up Before CLK Rise
Set-up Before 0.8
GW, BWE, BW[A:D]
CLK Rise
tDS
Data Input Set-up Before CLK
Rise
0.8
0.8
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
tCES
Chip Enable Set-up Before CLK
Rise
Hold Times
tAH
Address Hold After CLK Rise
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
tADH
tADVH
tWEH
,
Hold After CLK Rise
ADSP ADSC
ADV Hold After CLK Rise
,
,
GW BWE BW[A:D] Hold After CLK
Rise
tDH
Data Input Hold After CLK Rise
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
tCEH
Chip Enable Hold After CLK Rise 0.4
Shaded areas contain advance information.
Notes:
11. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V minimum initially before a read or write operation
DD
POWER
12. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
13. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05219 Rev. *A
Page 11 of 17
[+] Feedback
CY7C1340F
Switching Waveforms
Read Timing[17]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,BW[A:D]
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
OEV
CO
t
t
CHZ
t
t
t
OELZ
OEHZ
DOH
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
17. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05219 Rev. *A
Page 12 of 17
[+] Feedback
CY7C1340F
Switching Waveforms (continued)
Write Timing[17, 18]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A:D]
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
Data in (D)
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
18.
[A:D]
Document #: 38-05219 Rev. *A
Page 13 of 17
[+] Feedback
CY7C1340F
Switching Waveforms (continued)
Read/Write Timing[17, 19, 20]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW[A:D]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
D(A3)
D(A5)
D(A6)
High-Z
High-Z
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Single WRITE
BURST READ
Back-to-Back
WRITEs
UNDEFINED
DON’T CARE
Notes:
19.
20.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
ADSP or ADSC.
is HIGH.
GW
Document #: 38-05219 Rev. *A
Page 14 of 17
[+] Feedback
CY7C1340F
Switching Waveforms (continued)
ZZ Mode Timing [21, 22]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
21. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
22. DQs are in high-Z when exiting ZZ sleep mode.
Ordering Information
Speed
Package
Name
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
(MHz)
Ordering Code
CY7C1340F-250AC
CY7C1340F-250AI
CY7C1340F-225AC
CY7C1340F-225AI
CY7C1340F-200AC
CY7C1340F-200AI
CY7C1340F-166AC
CY7C1340F-166AI
CY7C1340F-133AC
CY7C1340F-133AI
CY7C1340F-100AC
CY7C1340F-100AI
Package Type
250
225
200
166
133
100
A101
A101
A101
A101
A101
A101
A101
A101
A101
A101
A101
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Shaded area contains advance information.
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05219 Rev. *A
Page 15 of 17
[+] Feedback
CY7C1340F
Package Diagram
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. PowerPC is a registered trademark
of IBM. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05219 Rev. *A
Page 16 of 17
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
[+] Feedback
CY7C1340F
Document History Page
Document Title: CY7C1340F 4-Mb (128K x 32) Pipelined DCD Sync SRAM
Document Number: 38-05219
Orig. of
REV.
**
*A
ECN NO. Issue Date Change
Description of Change
119827
12/16/02
HGK
SWI
New Data Sheet
Final Data Sheet
200143
See ECN
Document #: 38-05219 Rev. *A
Page 17 of 17
[+] Feedback
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