CY7C1345A-100BGC [CYPRESS]
Standard SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119;
| 型号： | CY7C1345A-100BGC |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119 静态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
345A
CY7C1345A/GVT71128E36
128K x 36 Synchronous Flow-Through Burst SRAM
eral circuitry and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a pos-
Features
• Fast access times: 7.5 and 8 ns
itive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), and Global Write (GW).
• Fast clock speed: 117 and 100 MHz
• Provide high-performance 2-1-1-1 access rate
• Fast OE access times: 4.0 ns
• 3.3V –5% and +10% power supply
• 2.5V or 3.3V I/O supply
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE), and Sleep Mode Control (ZZ).
The data outputs (DQ), enabled by OE, are also asynchro-
nous.
• 5V tolerant inputs except I/Os
• Clamp diodes to VSSQ at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. BW1 con-
trols DQ1–DQ8 and DQP1. BW2 controls DQ9–DQ16 and
DQP2. BW3 controls DQ17–DQ24 and DQP3. BW4 controls
DQ25–DQ32 and DQP4. BW1, BW2, BW3, and BW4 can be
active only with BWE being LOW. GW being LOW causes all
bytes to be written.
Functional Description
The CY7C1345A/GVT71128E36 operates from a +3.3V pow-
er supply and all outputs operate on a +2.5V supply. All inputs
and outputs are JEDEC standard JESD8-5 compatible. The
device is ideally suited for 486, Pentium®, 680x0, and Power-
PC™ systems and for systems that benefit from a wide syn-
chronous data bus.
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The
CY7C1345A/GVT71128E36
SRAM
integrates
131,072x36 SRAM cells with advanced synchronous periph-
Selection Guide
7C1345A-117
71128E36-7
7C1345A-100
71128E36-8
7C1345A-100
71128E36-9
7C1345A-100
71128E36-10
Maximum Access Time (ns)
7.5
370
10
8
8
8
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
320
10
320
10
320
10
Cypress Semiconductor Corporation
Document #: 38-05123 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 13, 2002
CY7C1345A/GVT71128E36
128K x 36 (CY7C1345A/GVT71128E36) Functional Block Diagram[1]
BYTE 1 WRITE
BW1#
BWE#
D
Q
CLK
BYTE 2 WRITE
BW2#
D
Q
GW#
BYTE 3 WRITE
BW3#
D
Q
BYTE 4 WRITE
BW4#
D
Q
ENABLE
CE#
CE2
D
Q
CE2#
ZZ
Power Down Logic
OE#
ADSP#
Input
Register
A16-A2
Address
Register
ADSC#
DQ1-DQ32,
DQP1, DQP2
DQP3, DQP4
CLR
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
Document #: 38-05123 Rev. *A
Page 2 of 16
CY7C1345A/GVT71128E36
Pin Configurations
100-Pin TQFP
Top View
DQP3
DQ17
DQ18
VCCQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VCCQ
DQ23
DQ24
NC
DQP2
DQ16
DQ15
VCCQ
VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ
VCCQ
DQ10
DQ9
VSS
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1345A/GVT71128E36
(128K X 36)
VCC
NC
VSS
NC
VCC
ZZ
DQ25
DQ26
VCCQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VCCQ
DQ31
DQ32
DQP4
DQ8
DQ7
VCCQ
VSSQ
DQ6
DQ5
DQ4
DQ3
VSSQ
VCCQ
DQ2
DQ1
DQP1
Document #: 38-05123 Rev. *A
Page 3 of 16
CY7C1345A/GVT71128E36
Pin Configurations (continued)
119-Ball Bump BGA
128Kx36—CY7C1345A/GVT71128E36
Top View
1
2
3
A4
4
ADSP
ADSC
VCC
NC
5
6
7
A
B
C
D
E
F
VCCQ
A6
A8
A16
VCCQ
NC
NC
CE2
A7
A3
A9
CE2
A15
NC
A2
A12
VSS
VSS
VSS
BW2
VSS
NC
NC
DQ17
DQ18
VCCQ
DQ21
DQ23
VCCQ
DQ25
DQ26
VCCQ
DQ30
DQ32
NC
DQP3
DQ19
DQ20
DQ22
DQ24
VCC
VSS
VSS
VSS
BW3
VSS
NC
DQP2
DQ14
DQ13
DQ12
DQ10
VCC
DQ16
DQ15
VCCQ
DQ11
DQ9
VCCQ
DQ8
DQ6
VCCQ
DQ2
DQ1
NC
CE
OE
G
H
J
ADV
GW
VCC
CLK
NC
K
L
DQ27
DQ28
DQ29
DQ31
DQP4
A5
VSS
BW4
VSS
VSS
VSS
MODE
A10
NC
VSS
BW1
VSS
VSS
VSS
NC
DQ7
DQ5
DQ4
DQ3
DQP1
A13
M
N
P
R
T
BWE
A1
A0
VCC
A11
NC
NC
NC
A14
NC
NC
ZZ
U
VCCQ
NC
NC
VCCQ
Pin Descriptions
Pin
Name
BGA Pins
QFP Pins
Type
Input-
Description
Addresses: These inputs are registered and must meet the set-up
4P, 4N, 2A, 3A, 37, 36, 35, 34, A0–A16
5A, 6A, 3B, 5B, 33, 32, 100, 99,
Synchronous and hold times around the rising edge of CLK. The burst counter
generates internal addresses associated with A0 and A1, during
burst cycle and wait cycle.
2C, 3C, 5C, 6C, 82, 81, 44, 45,
2R, 6R, 3T, 4T,
5T
46, 47, 48,
49,50
5L, 5G, 3G, 3L
93,94,95,96
BW1,
Input-
Byte Write: A byte write is LOW for a Write cycle and HIGH for a
BW2, Synchronous Read cycle. BW1 controls DQ1–DQ8 and DQP1. BW2 controls
BW3,
BW4
DQ9–DQ16 and DQP2. BW3 controls DQ17–DQ24 and DQP3.
BW4 controls DQ25–DQ32 and DQP4. Data I/O are high imped-
ance if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
4H
4K
87
88
89
BWE
GW
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the set-up and hold times around the rising edge of
CLK.
Input-
Global Write: This active LOW input allows a full 36-bit Write to
Synchronous occur independent of the BWE and BWn lines and must meet the
set-up and hold times around the rising edge of CLK.
CLK
Input-
Clock: This signal registers theaddresses, data, chip enables, write
Synchronous control and burst control inputs on its rising edge. All synchronous
inputs must meet set-up and hold times around the clock’s rising
edge.
Document #: 38-05123 Rev. *A
Page 4 of 16
CY7C1345A/GVT71128E36
Pin Descriptions (continued)
Pin
Name
BGA Pins
QFP Pins
Type
Description
4E
98
CE
CE2
CE2
OE
Input-
Chip Enable: This active LOW input is used to enable the device
Synchronous and to gate ADSP.
6B
2B
4F
4G
92
97
86
83
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device.
Input-
Synchronous
Chip Enable: This active HIGH input is used to enable the device.
Input
Output Enable: This active LOW asynchronous input enables the
data output drivers.
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle (no
address advance).
4A
4B
84
85
ADSP
ADSC
Input-
Address Status Processor: This active LOW input, along with CE
Synchronous being LOW, causes a new external address to be registered and a
Read cycle is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes device to
Synchronous be deselected or selected along with new external address to be
registered. A Read or Write cycle is initiated depending upon write
control inputs.
3R
7T
31
64
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin
selects Linear Burst. A NC or HIGH on this pin selects Interleaved
Burst.
Input-Asyn- Snooze: This active HIGH input puts the device in low power con-
chronous
sumption standby mode. For normal operation, this input has to be
either LOW or NC (No Connect).
7P, 7N, 6N, 6M, 52, 53, 56, 57,
6L, 7L, 6K, 7K, 58, 59, 62, 63,
7H, 6H, 7G, 6G, 68, 69, 72-75,
6F, 6E, 7E, 7D, 78, 79, 2, 3, 6-9,
1D, 1E, 2E, 2F, 12, 13, 18, 19,
DQ1–
DQ32
Input/
Output
Data Inputs/Outputs: First Byte is DQ1–DQ8. Second Byte is
DQ9–DQ16. Third Byte is DQ17–DQ24. Fourth Byte is
DQ25–DQ32. Input data must meet set-up and hold times around
the rising edge of CLK.
1G, 2G, 1H, 2H,
1K, 1L, 2K, 2L,
2M, 1N, 2N, 1P
22-25, 28, 29
51, 80, 1, 30
15, 41,65, 91
6P, 6D, 2D, 2P
DQP1–
DQP4
Input/
Output
Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2
is parity bit for DQ9–DQ16. DQP3 is parity bit for DQ17–DQ24 and
DQP4 is parity bit for DQ25–DQ32.
4C, 2J, 4J, 6J,
4R
VCC
VSS
Supply
Ground
Core power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 17, 40, 67, 90
3F, 5F, 5G, 3H,
Ground: GND
5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N,
3P, 5P
1A, 7A, 1F, 7F, 4, 11, 20, 27, 54, VCCQ
I/O Supply Output Buffer Supply: +2.5V (from 2.375V to VCC
)
1J, 7J, 1M, 7M,
1U, 7U
61, 70, 77
5, 10, 21, 26, 55, VSSQ
60, 71, 76
I/O Ground Output Buffer Ground: GND
1B, 7B, 1C, 7C, 14, 16, 38, 39,
NC
-
No Connect: These signals are not internally connected.
4D, 3J, 5J, 4L,
1R, 5R, 7R, 1T,
2T, 6T, 2U, 3U,
4U, 5U, 6U
42, 43, 66
Document #: 38-05123 Rev. *A
Page 5 of 16
CY7C1345A/GVT71128E36
Burst Address Table (MODE = NC/V
)
Burst Address Table (MODE = GND)
CC
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Used
Operation
CE
H
L
CE2 CE2 ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
None
None
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
X
L
L
None
L
H
H
L
None
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
External
External
External
External
External
Next
L
X
X
L
L-H
Q
READ Cycle, Begin Burst
L
L
L
H
X
L
L-H High-Z
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
READ Cycle, Begin Burst
L
L
L
H
L
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
L-H
L-H
D
D
H
X
L
X
WRITE Cycle, Suspend Burst
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + BW1*BW2*BW3*BW3]*GW equals LOW. WRITE = H means
[BWE + BW1*BW2*BW3*BW3]*GW equals HIGH.
3. BW1 enables write to DQ1–DQ8 and DQP1. BW2 enables write to DQ9–DQ16 and DQP2. BW3 enables write to DQ17–DQ24 and DQP3. BW4 enables write
to DQ25–DQ32 and DQP4.
4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5. Suspending burst generates wait cycle.
6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Document #: 38-05123 Rev. *A
Page 6 of 16
CY7C1345A/GVT71128E36
Partial Truth Table for Read/Write
FUNCTION
READ
GW
H
BWE
BW1
BW2
X
BW3
X
BW4
X
H
L
L
L
X
X
H
L
READ
H
H
H
H
WRITE one byte
WRITE all bytes
WRITE all bytes
H
H
H
H
H
L
L
L
L
L
X
X
X
X
Power Dissipation.......................................................... 1.6W
Maximum Ratings
Short Circuit Output Current ....................................... 20 mA
.
(Above which the useful life may be impaired. For user guide-
lines only, not tested.)
Operating Range
Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V
VIN..........................................................–0.5V to +VCC+0.5V
Storage Temperature (plastic).....................–55°C to +125°C
Junction Temperature ...............................................+125°C
[9,10]
Range
Ambient Temperature
VCC
Com’l
0°C to +70°C
3.3V –5%/+10%
Electrical Characteristics Over the Operating Range[11]
Parameter
VIHD
VIH
Description
Test Conditions
Min.
1.7
Max.
Unit
V
Input High (Logic 1) Voltage[12, 13] Data Inputs (DQxx)
VCC+0.3
All other
1.7
4.6
0.7
2
V
VIl
Input Low (Logic 0) Voltage[12, 13]
–0.3
–2
V
ILI
Input Leakage Current[14]
Output Leakage Current
Output High Voltage[12, 15]
Output Low Voltage[12, 15]
Supply Voltage[12]
0V < VIN < VCC
µA
µA
V
ILO
Output(s) disabled, 0V < VOUT < VCC
IOH = –2.0 mA
–2
2
VOH
VOL
1.7
IOL = 2.0 mA
0.7
3.6
V
VCC
3.135
2.375
V
VCCQ
I/O Supply Voltage
VCC
V
-7
-8
-9
-10
Parameter
Description
Conditions
Typ. 117 MHz 100 MHz 90 MHz 50 MHz Unit
ICC
Power Supply
Current:
Device selected;
150
370
320
290
200
mA
all inputs < VILor > VIH;
Operating[16, 17, 18] cycle time > tKC Min.; VCC = Max.;
outputs open
ISB2
CMOS
Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or
> VCC – 0.2;
5
10
10
10
10
mA
Standby[17, 18]
all inputs static; CLK frequency = 0
ISB3
TTL Standby[17, 18] Device deselected; all inputs < VIL 10
or > VIH; all inputs static;
20
80
20
70
20
60
20
40
mA
mA
VCC = Max.; CLK frequency = 0
ISB4
Clock
Device deselected;
all inputs < VIL or > VIH; VCC = Max.;
40
Running[17, 18]
CLK cycle time > tKC Min.
Notes:
9. Please refer to waveform (c)
10. Power Supply ramp-up should be monotonic.
11. Values in table are associated with the operating frequencies listed.
12. All voltages referenced to VSS (GND).
13. Overshoot:
VIH < +6.0V for t < tKC /2.
Undershoot: VIL < –2.0V for t < tKC /2.
14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA.
15. AC I/O curves are available upon request.
16.
ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
17. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
18. Typical values are measured at 3.3V, 25°C and 20-ns cycle time.
Document #: 38-05123 Rev. *A
Page 7 of 16
CY7C1345A/GVT71128E36
Thermal Consideration
Parameter
Description
Conditions
TQFP Typ.
Unit
°C/W
°C/W
ΘJA
ΘJC
Thermal Resistance - Junction to Ambient
Thermal Resistance - Junction to Case
Still air, soldered on 4.25 x 1.125
inch 4-layer PCB
25
9
Capacitance
Parameter
Description
Input Capacitance[19]
Input/Output Capacitance (DQ)[19]
Test Conditions
Typ.
4
Max.
Unit
CI
TA = 25°C, f = 1 MHz,
VCC= 3.3V
5
8
pF
pF
CO
7
Typical Output Buffer Characteristics
Output High Voltage
Pull-up Current
Output Low Voltage
Pull-down Current
VOH (V)
–0.5
0
I
OH (mA) Min.
IOH (mA) Max.
VOL (V)
–0.5
0
IOL (mA) Min.
I
ΟL (mA) Max.
–38
–38
–38
–26
–20
0
–105
–105
–105
–83
–70
–30
–10
0
0
0
0
0
0.8
0.4
10
20
31
40
40
40
40
20
40
63
80
80
80
80
1.25
1.5
0.8
1.25
1.6
2.3
2.7
0
2.8
2.9
0
3.2
3.4
0
0
3.4
AC Test Loads and Waveforms
tP U
=
20 0us
ALL INPUT PULSES
90%
2.5V
90%
10%
V c c ty p
V c c m in
Z = 50
0
Ω
F or proper R E S E T
bring V c c dow n to 0V
10%
R = 50
Ω
L
0V
V = 1.25V
t
Rise Time:
1.8 V/ns
Fall Time:
1.8 V/ns
(a)
(b)
(c)
Note:
19. This parameter is sampled.
20. Overshoot: VIH(AC) <VDD + 1.5V for t <tTCYC/2; undershoot: VIL(AC) < 0.5V for t <tTCYC/2; power-up: VIH < 2.6V and VDD <2.4V and VDDQ < 1.4V for t<200
ms.
Document #: 38-05123 Rev. *A
Page 8 of 16
CY7C1345A/GVT71128E36
Switching Characteristics Over the Operating Range[21]
-7
-8
-9
90 MHz
-10
50 MHz
117 MHz
100 MHz
Parameter
Clock
tKC
Description
Min. Max. Min. Max.
Min.
Max.
Min.
Max.
Unit
Clock Cycle Time
8.5
3
10
4
11
4.5
4.5
20
4.5
4.5
ns
ns
ns
tKH
Clock HIGH Time
Clock LOW Time
tKL
3
4
Output Times
tKQ
Clock to Output Valid
7.5
8
8.5
10
ns
ns
ns
ns
ns
ns
ns
tKQX
Clock to Output Invalid
2
0
2
2
0
2
2
0
2
2
0
2
tKQLZ
Clock to Output in Low-Z[19, 22, 23]
Clock to Output in High-Z[19, 22, 23]
OE to Output Valid[24]
tKQHZ
3.5
4.0
3.5
4.0
3.5
4.0
3.5
4.0
tOEQ
tOELZ
OE to Output in Low-Z[19, 22, 23]
OE to Output in High-Z[19, 22, 23]
0
0
0
0
tOEHZ
3.5
3.5
3.5
3.5
Set-Up Times
tS
Address, Controls and Data In[25]
Address, Controls and Data In[25]
1.5
0.5
2.0
0.5
2.0
0.5
2.0
0.5
ns
ns
Hold Times
tH
Notes:
21. Test conditions as specified with the output loading as shown in AC Test Loads unless otherwise noted. Values in table are associated with the operating
frequencies listed.
22. Measured at ±200 mV from steady state.
23. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ
.
24. OE is a “Don’t Care” when a byte write enable is sampled LOW.
25. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “Don’t Care” as defined in the truth table.
Document #: 38-05123 Rev. *A
Page 9 of 16
CY7C1345A/GVT71128E36
Timing Diagrams
Read Timing[26]
KC
t
KL
CLK
ADSP#
t
t
S
KH
t
H
ADSC#
t
S
ADDRESS
A1
A2
t
H
BW1#, BW2#,
BW3#, BW4#,
BWE#, GW#
CE#
(See Note)
t
S
ADV#
OE#
DQ
t
H
t
t
t
KQ
KQ
OEQ
t
t
KQLZ
OELZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
Q(A2+2)
SINGLE READ
BURST READ
Note:
26. CE active in this timing diagram means that all Chip Enables CE, CE2, and CE2 are active.
Document #: 38-05123 Rev. *A
Page 10 of 16
CY7C1345A/GVT71128E36
Timing Diagrams (continued)
Write Timing[26]
CLK
t
S
ADSP#
ADSC#
t
H
t
S
ADDRESS
A1
A2
A3
t
H
BW1#, BW2#,
BW3#, BW4#,
BWE#
GW#
CE#
(See Note)
t
S
ADV#
OE#
DQ
t
H
t
OEHZ
t
KQX
Q
D(A1)
D(A2)
D(A2+2)
D(A2+2)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
Document #: 38-05123 Rev. *A
Page 11 of 16
CY7C1345A/GVT71128E36
Timing Diagrams (continued)
Read/Write Timing[26]
CLK
t
S
ADSP#
ADSC#
t
H
t
S
ADDRESS
A2
A3
A4
A5
A1
t
H
BW1#, BW2#,
BW3#, BW4#,
BWE#, GW#
CE#
(See Note)
ADV#
OE#
DQ
Q(A1)
Q(A2)
D(A3)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
D(A5)
D(A5+1)
Single Reads
Single Write
Burst Read
Burst Write
Document #: 38-05123 Rev. *A
Page 12 of 16
CY7C1345A/GVT71128E36
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
117
CY7C1345A-117AC
GVT71128E36T-7
CY7C1345A-117BGC
GVT71128E36B-7
CY7C1345A-100AC
GVT71128E36T-8
CY7C1345A-100BGC
GVT71128E36B-8
CY7C1345A-100AC
GVT71128E36T-9
CY7C1345A-100BGC
GVT71128E36B-9
CY7C1345A-100AC
GVT71128E36T-10
CY7C1345A-100BGC
GVT71128E36B-10
A101
BG119
A101
100-Lead Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
100-Lead Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
100-Lead Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
100-Lead Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
Commercial
100
100
100
Commercial
Commercial
Commercial
BG119
A101
BG119
A101
BG119
Document #: 38-05123 Rev. *A
Page 13 of 16
CY7C1345A/GVT71128E36
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05123 Rev. *A
Page 14 of 16
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1345A/GVT71128E36
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05123 Rev. *A
Page 15 of 16
CY7C1345A/GVT71128E36
Document History Page
Document Title: CY7C1345A/GVT71128E36 128K x 36 Synchronous Flow-Through Burst SRAM
Document Number: 38-05123
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
108314
121069
123136
Description of Change
09/25/01
11/13 /02
01/19/03
BRI
DSG
RBI
New Cypress spec—converted from Galvantech format
Updated package drawing 51-85115 (BG119) to rev. *B
Added power up requirements to operating conditions information.
*A
*B
Document #: 38-05123 Rev. *A
Page 16 of 16
相关型号：
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