CY7C1345B_技术文档

CY7C1345B

128K x 36 Synchronous Flow-Through 3.3V Cache RAM

Features

Functional Description

• Supports 117-MHzmicroprocessorcachesystems with

zero wait states

• 128K by 36 common I/O

• Fast clock-to-output times

— 7.5 ns (117-MHz version)

The CY7C1345B is a 3.3V, 128K by 36 synchronous cache

RAM designed to interface with high-speed microprocessors

with minimum glue logic. Maximum access delay from clock

rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-

tures the first address in a burst and increments the address

automatically for the rest of the burst access.

• Two-bit wrap-around counter supporting either

interleaved or linear burst sequence

• Separate processorand controller address strobespro-

vide direct interface with the processor and external

cache controller

• Synchronous self-timed write

• Asynchronous output enable

• Supports 3.3V & 2.5V I/O levels

• ZZ “sleep” mode

The CY7C1345B allows either interleaved or linear burst se-

quences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses can be initiated with the Processor

Address Strobe (ADSP) or the cache Controller Address

Strobe (ADSC) inputs. Address advancement is controlled by

the Address Advancement (ADV) input.

A synchronous self-timed write mechanism is provided to sim-

plify the write interface. A synchronous chip enable input and

an asynchronous output enable input provide easy control for

bank selection and output three-state control.

Logic Block Diagram

MODE

2

(A ,A )

0

1

Q

0

CLK

ADV

ADSC

BURST

COUNTER

CE

CLR

1

ADSP

Q

15

17

ADDRESS

REGISTER

CE

D

128K X 36

MEMORY

ARRAY

A

[16:0]

GW

17

15

DQ[31:24],DP3

Q

D

BYTEWRITE

BWE

BWS

REGISTERS

3

DQ[23:16],DP2

D

BYTEWRITE

REGISTERS

BWS

2

DQ[15:8],DP1

D

BYTEWRITE

1

REGISTERS

DQ[7:0],DP0 Q

BWS

BYTEWRITE

0

REGISTERS

36

CE

1

2

D

ENABLE

Q

CE

REGISTER

3

CLK

INPUT

REGISTERS

CLK

OE

ZZ

SLEEP

CONTROL

DQ

[31:0]

DP

[3:0]

Selection Guide

7C1345B-117

7C1345B-100

Maximum Access Time (ns)

7.5

350

2.0

8.0

325

2.0

Maximum Operating Current (mA)

Maximum Standby Current (mA)

Intel and Pentium are registered trademarks of Intel Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

September 11, 2000

CY7C1345B

Pin Configurations

100-Pin TQFP

DP₂

1

DP₁

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQ₁₆

DQ₁₇

V_DDQ

V_SSQ

DQ₁₈

DQ₁₉

DQ₂₀

DQ₂₁

V_SSQ

V_DDQ

DQ₂₂

DQ₂₃

NC

2

DQ₁₅

DQ₁₄

3

4

V_DDQ

V_SSQ

DQ₁₃

DQ₁₂

DQ₁₁

DQ₁₀

V_SSQ

V_DDQ

DQ₉

5

6

7

8

BYTE2

9

BYTE1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

DQ₈

V_SS

CY7C1345B

V_DD

NC

V_DD

ZZ

V_SS

DQ₂₄

DQ₂₅

V_DDQ

V_SSQ

DQ₂₆

DQ₂₇

DQ₂₈

DQ₂₉

V_SSQ

V_DDQ

DQ₃₀

DQ₃₁

DP₃

DQ₇

DQ₆

V_DDQ

V_SSQ

DQ₅

DQ₄

DQ₃

DQ₂

V_SSQ

V_DDQ

DQ₁

DQ₀

DP₀

BYTE3

BYTE0

2

CY7C1345B

Pin Configurations (continued)

119-Ball BGA

2

1

3

A

4

5

A

6

A

7

A

B

C

D

E

F

V

A

CE

A

ADSP

ADSC

V

DDQ

NC

DQ

CE

A

NC

DQ

2

3

V

DD

DQP

DQ

V

NC

V

DQP

DQ

c

SS

b

DQ

V

CE

V

DQ

b

c

1

b

V

DQ

OE

ADV

GW

DQ

V

DDQ

b

G

H

J

DQ

BW

V

BW

V

DQ

c

b

DQ

c

SS

V

NC

V

NC

V

DDQ

DD

K

DQ

V

CLK

V

DQ

d

SS

a

L

M

N

DQ

BW

NC

BWE

A1

BW

DQ

d

a

V

DDQ

SS

DQ

d

SS

a

P

R

T

DQ

DQP

A

V

A0

V

DQP

a

DQ

d

SS

a

NC

MODE

A

V

A

NC

ZZ

DD

NC

A

NC

V

NC

V

DDQ

U

DDQ

Pin Descriptions

Name

I/O

Description

Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A

ADSC

Input-

[15:0]

Synchronous

is captured in the address registers. A

are also loaded into the burst counter. When ADSP and

[1:0]

ADSC are both asserted, only ADSP is recognized.

ADSP

Input-

Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A

[15:0]

Synchronous

is captured in the address registers. A

ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE is deasserted HIGH.

are also loaded into the burst counter. When ADSP and

[1:0]

1

A

Input-

Synchronous

A , A Address Inputs. These inputs feed the on-chip burst counter as the LSBs as well as being

1 0

used to access a particular memory location in the memory array.

[1:0]

Input-

Synchronous

Address Inputs used in conjunction with A to select one of the 64K address locations. Sampled

[16:2]

[1:0]

at the rising edge of the CLK, if CE , CE , and CE are sampled active, and ADSP or ADSC is active

1 2 3

LOW.

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the

rising edge. BW controls DQ and DP , BW controls DQ and DP , BW controls DQ

[23:16]

BW

Input-

Synchronous

[3:0]

0

[7:0]

0

1

[15:8]

1

2

and DP , and BW controls DQ

and DP . See Write Cycle Description table for further details.

2

3

[31:24]

3

ADV

BWE

GW

Input-

Synchronous

Advance Input, used to advance the on-chip address counter. When LOW the internal burst counter

is advanced in a burst sequence. The burst sequence is selected using the MODE input.

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be

asserted LOW to conduct a byte write.

Input-

Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct

Synchronous

a global write, independent of the state of BWE and BW

. Global writes override byte writes.

[3:0]

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device.

CE

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

1

2

Synchronous

and CE to select/deselect the device. CE gates ADSP.

3

1

CE

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE and CE to select/deselect the device.

2

1

3

CY7C1345B

Pin Descriptions (continued)

Name

CE

I/O

Description

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

Input-

3

1

Synchronous

and CE to select/deselect the device.

2

OE

Input-

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,

Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input

data pins.

ZZ

Input-

Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby

Asynchronous mode in which all other inputs are ignored, but the data in the memory array is maintained.Leaving

ZZ floating or NC will default the device into an active state. ZZ pin has an internal pull-down.

MODE

-

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst

order. Mode pin has an internal pull-up.

DQ

DP

,

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

[31:0]

[3:0]

by A

during the previous clock rise of the read cycle. The direction of the pins is controlled by

[16:0]

OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as

outputs. When HIGH, DQ and DP are placed in a three-state condition. The outputs are

[31:0]

[3:0]

automatically three-stated when a Write cycle is detected.

V

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.

DD

Ground

Ground for the I/O circuitry of the device. Should be connected to ground of the system.

Ground for the device. Should be connected to ground of the system.

SS

SSQ

DDQ

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.

NC

-

No connects.

DNU

Do not use pins. Should be left unconnected or tied LOW.

serted active, and (2) ADSP or ADSC is asserted LOW (if the

access is initiated by ADSC, the write inputs must be deassert-

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. Maximum access delay from

ed during this first cycle). The address presented to the ad-

dress inputs is latched into the address register and the burst

counter/control logic and presented to the memory core. If the

OE input is asserted LOW, the requested data will be available

the clock rise (t

) is 7.5 ns (117-MHz device).

CDV

The CY7C1345B supports secondary cache in systems utiliz-

ing either a linear or interleaved burst sequence. The inter-

leaved burst order supports Pentium and i486 processors. The

linear burst sequence is suited for processors that utilize a

linear burst sequence. The burst order is user selectable, and

is determined by sampling the MODE input. Accesses can be

initiated with either the Processor Address Strobe (ADSP) or

the Controller Address Strobe (ADSC). Address advancement

through the burst sequence is controlled by the ADV input. A

two-bit on-chip wraparound burst counter captures the first ad-

dress in a burst sequence and automatically increments the

address for the rest of the burst access.

at the data outputs a maximum to t

after clock rise. ADSP

CDV

is ignored if CE is HIGH.

1

Functional Description

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are sat-

isfied at clock rise: (1) CE , CE , and CE are all asserted

1

2

3

active, and (2) ADSP is asserted LOW. The addresses pre-

sented are loaded into the address register and the burst

counter/control logic and delivered to the RAM core. The write

inputs (GW, BWE, and BW

) are ignored during this first

[3:0]

Byte write operations are qualified with the Byte Write Enable

clock cycle. If the write inputs are asserted active (see Write

Cycle Descriptions table for appropriate states that indicate a

write) on the next clock rise, the appropriate data will be

latched and written into the device. Byte writes are allowed.

(BWE) and Byte Write Select (BW

) inputs. A Global Write

[3:0]

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip synchro-

nous self-timed write circuitry.

During byte writes, BW controls DQ

, BW controls

0

[7:0]

1

Three synchronous Chip Selects (CE , CE , CE ) and an

DQ

, BW controls DQ

, and BW controls DQ

.

[31:24]

1

2

3

[15:8]

2

[23:16]

3

asynchronous Output Enable (OE) provide for easy bank se-

All I/Os are three-stated during a byte write. Since this is a

common I/O device, the asynchronous OE input signal must

be deasserted and the I/Os must be three-stated prior to the

lection and output three-state control. ADSP is ignored if CE

is HIGH.

1

presentation of data to DQ

data lines are three-stated once a write cycle is detected, re-

. As a safety precaution, the

[31:0]

Single Read Accesses

gardless of the state of OE.

A single read access is initiated when the following conditions

are satisfied at clock rise: (1) CE , CE , and CE are all as-

1

2

3

4

CY7C1345B

Single Write Accesses Initiated by ADSC

Table 1. Counter Implementation for the Intel®

Pentium®/80486 Processor’s Sequence

This write access is initiated when the following conditions are

satisfied at clock rise: (1) CE , CE , and CE are all asserted

active, (2) ADSC is asserted LOW, (3) ADSP is deasserted

1

2

3

First

Second

Third

Fourth

Address

HIGH, and (4) the write input signals (GW, BWE, and BW

)

[3:0]

A

,A

A

, A

A

, A

A

, A

X + 1 x

indicate a write access. ADSC is ignored if ADSP is active LOW.

X + 1

x

X + 1

x

X + 1

x

The addresses presented are loaded into the address register

and the burst counter/control logic and delivered to the RAM

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

core. The information presented to DQ

will be written into

[31:0]

the specified address location. Byte writes are allowed. During

byte writes, BW controls DQ , BW controls DQ , BW

2

0

[7:0]

1

[15:8]

. All I/Os are

controls DQ

, and BWS controls DQ

[23:16]

3

[31:24]

three-stated when a write is detected, even a byte write. Since

this is a common I/O device, the asynchronous OE input signal

must be deasserted and the I/Os must be three-stated prior to

Table 2. Counter Implementation for a Linear Sequence

the presentation of data to DQ

data lines are three-stated once a write cycle is detected, re-

gardless of the state of OE.

. As a safety precaution, the

First

Second

Third

Fourth

[31:0]

Address

A

, A

A

, A

A

, A

A

, A

X + 1 x

X + 1

x

X + 1

x

X + 1

x

Burst Sequences

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

The CY7C1345B provides an on-chip 2-bit wraparound burst

counter inside the SRAM. The burst counter is fed by A

,

[1:0]

and can follow either a linear or interleaved burst order. The

burst order is determined by the state of the MODE input. A

LOW on MODE will select a linear burst sequence. A HIGH on

MODE will select an interleaved burst order. Leaving MODE

unconnected will cause the device to default to a interleaved

burst sequence.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ HIGH

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed. Ac-

cesses pending when entering the “sleep” mode are not con-

sidered valid nor is the completion of the operation guaran-

teed. The device must be deselected prior to entering the

“sleep” mode. CE , CE , CE , ADSP, and ADSC must remain

1

2

3

inactive for the duration of t

after the ZZ input returns

ZZREC

LOW. Leaving ZZ unconnected defaults the device into an ac-

tive state.

5

CY7C1345B

Cycle Description Table^{[1, 2, 3]}

ADD

Cycle Description

Used

CE CE

CE

X

L

ZZ ADSP ADSC ADV WE

OE CLK

DQ

L-H High-Z

1

3

2

Deselected Cycle, Power-down

Snooze Mode, Power-down

Read Cycle, Begin Burst

None

H

L

X

H

X

L

H

L

X

L

X

L

X

L

X

L

X

L

None

L

X

L

None

L

H

X

L

None

X

L

X

H

X

L

None

X

L

X

High-Z

Q

External

Read Cycle, Begin Burst

L

H

X

L

L-H High-Z

Write Cycle, Begin Burst

L

H

X

H

X

H

X

H

X

L-H

D

Q

Read Cycle, Begin Burst

L

H

L

Read Cycle, Begin Burst

L

H

L

L-H High-Z

L-H

L-H High-Z

L-H

L-H High-Z

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

X

H

X

H

X

H

X

H

X

H

Q

H

L

Q

H

X

L

L-H

D

Q

L

Current

H

L

H

L

L-H High-Z

L-H

L-H High-Z

Q

H

X

L-H

D

Write Cycle, Suspend Burst

L

Notes:

1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.

2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS_[3:0].Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE

is a “Don't Care” for the remainder of the write cycle.

3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.

6

CY7C1345B

Write Cycle Descriptions^{[1, 2, 3, 4]}

Function

GW

1

BWE

1

BW

X

1

BW

X

1

BW

X

1

BW

X

1

3

2

1

0

Read

1

0

Write Byte 0, DP

Write Byte 1, DP

1

0

1

0

1

0

1

0

1

Write Bytes 1, 0, DP , DP

1

0

1

0

1

Write Byte 2, DP

1

0

1

0

1

2

Write Bytes 2, 0, DP , DP

1

0

1

0

1

0

2

0

1

Write Bytes 2, 1, DP , DP

1

0

1

0

1

2

Write Bytes 2, 1, 0, DP , DP , DP

1

0

1

0

2

1

0

Write Byte 3, DP

1

0

1

3

Write Bytes 3, 0, DP , DP

1

0

1

0

3

0

Write Bytes 3, 1, DP , DP

1

0

1

0

1

3

Write Bytes 3, 1, 0, DP , DP , DP

1

0

1

0

3

1

0

Write Bytes 3, 2, DP , DP

1

0

1

3

2

Write Bytes 3, 2, 0, DP , DP , DP

1

0

1

0

3

2

0

Write Bytes 3, 2, 1, DP , DP , DP

1

0

1

3

2

1

Write All Bytes

1

0

X

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

I

t

Snooze mode

standby current

ZZ > V − 0.2V

10

mA

ns

CCZZ

DD

Deviceoperationto

ZZ

ZZ > V − 0.2V

2t

CYC

ZZS

DD

ZZ recovery time

ZZ < 0.2V

2t

ns

ZZREC

CYC

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

Static Discharge Voltage .......................................... >2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-Up Current.................................................... >200 mA

Storage Temperature ................................. –65°C to +150°C

Operating Range

Ambient Temperature with

Power Applied............................................. –55°C to +125°C

Ambient

Range Temperature

[6]

V

DDQ

DD

Supply Voltage on V Relative to GND........ –0.5V to +4.6V

DD

Com’l

Ind’l

0°C to +70°C

3.135V to 3.6V 2.375V to V

DD

DC Voltage Applied to Outputs

in High Z State ....................................–0.5V to V + 0.5V

[5]

DD

–40°C to +85°C

[5]

DC Input Voltage .................................–0.5V to V + 0.5V

DD

Notes:

4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.

5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.

6. T_Ais the case temperature.

7

CY7C1345B

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min. Max. Unit

V

Output HIGH Voltage

V

= 3.3V, V = Min., I = –4.0 mA

2.4

2.0

V

OH

DDQ

DD

OH

= 2.5V, V = Min., I = –2.0 mA

DD

OH

Output LOW Voltage

= 3.3V, V = Min., I = 8.0 mA

0.4

0.7

OL

DD

OL

= 2.5V, V = Min., I = 2.0 mA

DD

OL

V

Input HIGH Voltage

= 3.3V

2.0

1.7

V

+

DD

IH

0.3V

V

= 2.5V

V

+

V

DDQ

DD

0.3V

[5]

V

Input LOW Voltage

V

= 3.3V

= 2.5V

–0.3

−1

0.8

0.7

1

V

IL

DDQ

[5]

Input LOW Voltage

I

Input Load Current

GND ≤ V ≤ V

µA

X

I

DDQ

(except ZZ and MODE)

Input Current of MODE

Input Current of ZZ

Input = V

–30

–5

µA

SS

5

DDQ

SS

30

5

DDQ

I

Output Leakage Current

GND ≤ V ≤ V , Output Disabled

–5

OZ

OS

DD

I

DD

[7]

Output Short Circuit Current

V

= Max., V

= GND

–300 mA

DD

OUT

V

Operating Supply Current

V

f = f

= Max., I

= 0 mA,

8.5-ns cycle, 117 MHz

10-ns cycle, 100 MHz

350

325

125

110

mA

DD

OUT

= 1/t

CYC

MAX

I

Automatic CE Power-Down

Current—TTL Inputs

Max. V , Device Deselected, 8.5-ns cycle, 117 MHz

DD

V

f = f

SB1

≥ V or V ≤ V

IN IH IN IL

10-ns cycle, 100 MHz

All speeds

= 1/t

,

MAX

CYC

inputs switching

I

Automatic CE Power-Down

Current—CMOS Inputs

Max. V , Device Deselected,

V

f = 0, inputs static

10

mA

SB2

SB3

SB4

DD

≤ 0.3V or V > V

– 0.3V,

DDQ

IN

Automatic CE Power-Down

Current—CMOS Inputs

Max. V , Device Deselected,

8.5-ns cycle, 117 MHz

10-ns cycle, 100 MHz

95

85

mA

DD

V

≥ V

– 0.3V or V ≤ 0.3V,

IN

DDQ IN

f = f

, inputs switching

MAX

Automatic CE Power-Down

Max. V , Device Deselected,

30

mA

DD

Current—TTL Inputs

V ≥ V –0.3V or V ≤ 0.3V, f = 0,

IN DD IN

inputs static

Note:

7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

8

CY7C1345B

Capacitance^[8]

Parameter

Description

Input Capacitance

I/O Capacitance

Test Conditions

T = 25°C, f = 1 MHz,

Max.

4.0

Unit

pF

C

IN

A

V

= 5.0V

DD

C

4.0

pF

I/O

AC Test Loads and Waveforms

R1=317

Ω

OUTPUT

3.3V

OUTPUT

ALL INPUT PULSES

90%

3.0V

GND

Z =50

Ω

90%

10%

0

R =50

L

Ω

10%

R2=351

Ω

5 pF

V =1.5V

L

INCLUDING

JIG AND

SCOPE

Rise Time: 1 V/ns

Fall Time: 1 V/ns

(a)

(b)

[9]

Switching Characteristics Over the Operating Range

-117

-100

Parameter

Description

Min.

8.5

3.0

2.0

0.5

Max.

Min.

10

Max.

Unit

ns

t

Clock Cycle Time

Clock HIGH

CYC

4.0

2.0

0.5

CH

Clock LOW

CL

Address Set-Up Before CLK Rise

Address Hold After CLK Rise

AS

AH

Data Output Valid After CLK Rise

Data Output Hold After CLK Rise

ADSP, ADSC Set-Up Before CLK Rise

ADSP, ADSC Hold After CLK Rise

7.5

8.0

CDV

DOH

ADS

ADH

WES

WEH

ADVS

ADVH

DS

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

BWS

, GW,BWE Set-Up Before CLK Rise

, GW,BWE Hold After CLK Rise

[1:0]

ADV Set-Up Before CLK Rise

ADV Hold After CLK Rise

Data Input Set-Up Before CLK Rise

Data Input Hold After CLK Rise

Chip Enable Set-Up

DH

CES

CEH

CHZ

CLZ

EOHZ

EOLZ

EOV

Chip Enable Hold After CLK Rise

[10, 11]

Clock to High-Z

3.5

[10, 11]

Clock to Low-Z

0

[10, 12]

OE HIGH to Output High-Z

[10, 12]

OE LOW to Output Low-Z

OE LOW to Output Valid

Notes:

8. Tested initially and after any design or process changes that may affect these parameters.

9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and

output loading of the specified I_OL/I_OHand load capacitance. Shown in (a) and (b) of AC Test Loads.

10. t_CHZ, t_CLZ, t_EOHZ, and t_EOLZare specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.

11. At any given voltage and temperature, t_CHZ(max.) is less than t_CLZ(min.).

12. This parameter is sampled and not 100% tested.

9

CY7C1345B

Timing Diagrams

[13, 14]

Write Cycle Timing

Single W rite

Burst W rite

Pipelined Write

t

Unselected

CH

t

CYC

CLK

t

ADH

t

ADS

t

ADSP ignored with CE inactive

CL

1

ADSP

t

ADH

t

ADSC initiated write

ADS

ADSC

ADV

t

ADVH

ADVS

t

ADV Must Be Inactive for ADSP Write

WD2

AS

WD3

WD1

ADD

GW

WE

t

AH

t

WH

t

WH

t

WS

t

WS

t

CES

CEH

CE masks ADSP

1

CE

1

t

CEH

CES

Unselected with CE

2

CE

2

CE

3

t

CES

t

CEH

OE

t

DH

t

DS

High-Z

Data In

3a

2a

= UNDEFINED

2c

2d

1a

2b

= DON’T CARE

Notes:

13. WE is the combination of BWE, BW_[3:0], and GW to define a write cycle (see Write Cycle Descriptions table).

14. WDx stands for Write Data to Address X.

10

CY7C1345B

Timing Diagrams (continued)

[13, 15]

Read Cycle Timing

Burst Read

Single Read

Unselected

t

CYC

CH

Pipelined Read

CLK

t

ADH

ADS

t

ADSP ignored with CE inactive

CL

1

ADSP

t

ADS

ADSC initiated read

ADSC

ADV

t

ADVS

t

ADH

Suspend Burst

t

ADVH

AS

ADD

GW

WE

RD3

RD1

RD2

t

AH

t

WS

t

WS

t

WH

t

CES

CEH

t

WH

CE masks ADSP

1

CE

1

2

Unselected with CE

2

t

CES

t

CEH

CE

OE

3

t

CEH

CES

t

EOV

t

OEHZ

t

DOH

t

CDV

3a

2c

Data Out

2d

2a

2b

2c

1a

t

CLZ

t

CHZ

= DON’T CARE

= UNDEFINED

Note:

15. RDx stands for Read Data from Address X.

11

CY7C1345B

Timing Diagrams (continued)

Read/Write Timing

t

CYC

CL

CH

CLK

t

AH

t

AS

A

D

B

C

ADD

t

ADH

ADS

ADSP

ADSC

ADV

t

ADH

ADS

t

ADVH

ADVS

t

CEH

t

CES

CE

1

t

CEH

CES

CE

t

WES

WEH

WE

ADSP ignored

with CE HIGH

1

OE

t

EOHZ

D(C)

t

CLZ

Data

D

(C+3)

Q

(B+3)

D

(C+1)

D

(C+2)

Q

(B+2)

Q

(B+1)

Q(B)

Q(A)

Q(D)

In/Out

CDV

t

DOH

t

CHZ

Device originally

deselected

WE is the combination of BWE, BWS

, and GW to define a write cycle (see Write Cycle Descriptions table).

[1:0]

CE is the combination of CE and CE . All chip selects need to be active in order to select

2

3

the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,

Qx stands for Data-out X.

= UNDEFINED

= DON’T CARE

12

CY7C1345B

Timing Diagrams (continued)

Pipeline Timing

t

CYC

CL

CH

CLK

t

AS

WD1

WD2

WD3

WD4

RD1

RD2

RD3

RD4

ADD

t

ADS

ADH

ADSC initiated Reads

ADSC

ADSP

ADV

ADSP initiated Reads

t

CEH

CES

CE

1

CE

t

WEH

WES

WE

OE

ADSP ignored

with CE HIGH

1

t

CLZ

Data In/Out

1a

In

1a

2a

3a

4a

2a

In

3a

In

4a

I^Dn^(C)

Out Out Out Out

t

CDV

t

DOH

Back to Back Reads

t

CHZ

Back to Back Writes

= UNDEFINED

= DON’T CARE

13

CY7C1345B

Timing Diagrams (continued)

OE Switching Waveforms

OE

t

EOV

t

EOHZ

three-state

I/Os

t

EOLZ

14

CY7C1345B

Timing Diagrams (continued)

[16, 17]

ZZ Mode Timing

CLK

ADSP

HIGH

ADSC

CE

1

2

LOW

HIGH

CE

3

ZZ

t

ZZS

I

CC

I

(active)

CC

t

ZZREC

I

CCZZ

I/Os

Three-state

Notes:

16. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.

17. I/Os are in three-state when exiting ZZ sleep mode.

15

CY7C1345B

Ordering Information

Speed

Package

Name

Operating

Range

(MHz)

Ordering Code

Package Type

100-Lead Thin Quad Flat Pack

119-Ball BGA

117

CY7C1345B-117AC

CY7C1345B-117BGC

CY7C1345B-100AC

CY7C1345B-100BGC

CY7C1345B-100AI

CY7C1345B-100BGI

A101

BG119

A101

Commercial

Industrial

100

100-Lead Thin Quad Flat Pack

119-Ball BGA

BG119

A101

100-Lead Thin Quad Flat Pack

119-Ball BGA

BG119

Document #: 38-00953-*B

Package Diagram

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

16

CY7C1345B

Package Diagram

119-Lead FBGA (14 x 22 x 2.4 mm) BG119

51-85115

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	CY7C1345B
厂家：	CYPRESS
描述：	128K x 36 Synchronous Flow-Through 3.3V Cache RAM 128K ×36的同步流程，通过3.3V高速缓存RAM
文件：	总17页 (文件大小：346K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1345B [CYPRESS]

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