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CY7C1345B-50AC [CYPRESS]

Cache SRAM, 128KX36, 11ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
CY7C1345B-50AC
型号： CY7C1345B-50AC
厂家： CYPRESS    CYPRESS
描述：

Cache SRAM, 128KX36, 11ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

静态存储器
文件： 总15页 (文件大小：266K)
中文：  中文翻译
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PRELIMINARY  
CY7C1345B  
128K x 36 Synchronous Flow-Through 3.3V Cache RAM  
Features  
Functional Description  
• Supports117-MHzmicroprocessorcachesystems with  
zero wait states  
• 128K by 36 common I/O  
• Fast clock-to-output times  
— 7.5 ns (117-MHz version)  
The CY7C1345B is a 3.3V, 128K by 36 synchronous cache  
RAM designed to interface with high-speed microprocessors  
with minimum glue logic. Maximum access delay from clock  
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-  
tures the first address in a burst and increments the address  
automatically for the rest of the burst access.  
• Two-bit wrap-around counter supporting either  
interleaved or linear burst sequence  
• Separate processorand controller address strobes pro-  
vide direct interface with the processor and external  
cache controller  
• Synchronous self-timed write  
• Asynchronous output enable  
• 3.3V I/Os  
• JEDEC-standard pinout  
• 100-pin TQFP packaging  
• ZZ “sleep” mode  
The CY7C1345B allows either interleaved or linear burst se-  
quences, selected by the MODE input pin. A HIGH selects an  
interleaved burst sequence, while a LOW selects a linear burst  
sequence. Burst accesses can be initiated with the Processor  
Address Strobe (ADSP) or the cache Controller Address  
Strobe (ADSC) inputs. Address advancement is controlled by  
the Address Advancement (ADV) input.  
A synchronous self-timed write mechanism is provided to sim-  
plify the write interface. A synchronous chip enable input and  
an asynchronous output enable input provide easy control for  
bank selection and output three-state control.  
Logic Block Diagram  
MODE  
2
(A ,A )  
0
1
Q
Q
0
CLK  
ADV  
ADSC  
BURST  
COUNTER  
CE  
CLR  
1
ADSP  
Q
15  
17  
ADDRESS  
REGISTER  
CE  
D
128K X 36  
MEMORY  
ARRAY  
A
[16:0]  
GW  
17  
15  
DQ[31:24],DP3  
Q
Q
Q
D
BYTEWRITE  
BWE  
BWS  
REGISTERS  
3
DQ[23:16],DP2  
D
BYTEWRITE  
REGISTERS  
BWS  
BWS  
2
DQ[15:8],DP1  
D
D
BYTEWRITE  
1
REGISTERS  
DQ[7:0],DP0 Q  
BWS  
BYTEWRITE  
0
REGISTERS  
36  
36  
CE  
CE  
CE  
1
2
D
ENABLE  
Q
CE  
REGISTER  
3
CLK  
INPUT  
REGISTERS  
CLK  
OE  
ZZ  
SLEEP  
CONTROL  
DQ  
[31:0]  
DP  
[3:0]  
Selection Guide  
7C1345B-117  
7C1345B-100  
7C1345B-90  
7C1345B-50  
Maximum Access Time (ns)  
7.5  
350  
2.0  
8.0  
325  
2.0  
8.5  
300  
2.0  
11.0  
250  
2.0  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
Intel and Pentium are registered trademarks of Intel Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
April 5, 2000  
PRELIMINARY  
CY7C1345B  
Pin Configurations  
DP2  
1
DP1  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQ16  
DQ17  
VDDQ  
VSSQ  
DQ18  
DQ19  
DQ20  
DQ21  
VSSQ  
VDDQ  
DQ22  
DQ23  
VSSQ  
VDD  
2
DQ15  
DQ14  
3
4
VDDQ  
VSSQ  
DQ13  
DQ12  
DQ11  
DQ10  
VSSQ  
VDDQ  
DQ9  
5
6
7
8
BYTE2  
9
BYTE1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
DQ8  
100-Pin TQFP  
CY7C1345B  
VSS  
NC  
NC  
VDD  
ZZ  
VSS  
DQ24  
DQ25  
VDDQ  
VSSQ  
DQ26  
DQ27  
DQ28  
DQ29  
VSSQ  
VDDQ  
DQ30  
DQ31  
DP3  
DQ7  
DQ6  
VDDQ  
VSSQ  
DQ5  
DQ4  
DQ3  
DQ2  
VSSQ  
VDDQ  
DQ1  
DQ0  
DP0  
BYTE3  
BYTE0  
2
PRELIMINARY  
CY7C1345B  
Pin Configurations (continued)  
119-Ball BGA  
2
1
3
A
A
A
4
5
A
A
A
6
A
7
A
B
C
D
E
F
V
A
CE  
A
ADSP  
ADSC  
V
DDQ  
DDQ  
NC  
NC  
DQ  
CE  
A
NC  
NC  
DQ  
2
3
V
DD  
DQP  
DQ  
V
NC  
V
DQP  
DQ  
c
c
SS  
SS  
SS  
SS  
SS  
SS  
b
b
DQ  
V
V
CE  
V
V
DQ  
b
c
c
c
1
b
V
DQ  
DQ  
DQ  
OE  
ADV  
GW  
DQ  
DQ  
DQ  
V
DDQ  
DDQ  
b
G
H
J
DQ  
BW  
V
BW  
V
DQ  
c
c
c
c
b
b
b
b
b
DQ  
DQ  
c
SS  
SS  
V
V
NC  
V
NC  
V
V
DDQ  
DDQ  
DD  
DD  
DD  
K
DQ  
DQ  
V
CLK  
V
DQ  
DQ  
d
d
SS  
SS  
a
a
L
M
N
DQ  
DQ  
DQ  
DQ  
BW  
NC  
BWE  
A1  
BW  
DQ  
DQ  
DQ  
DQ  
d
d
d
d
d
a
a
a
a
a
V
V
V
V
V
V
DDQ  
DDQ  
SS  
SS  
SS  
DQ  
DQ  
d
SS  
a
P
R
T
DQ  
DQP  
A
V
A0  
V
V
DQP  
A
DQ  
d
d
SS  
SS  
SS  
a
a
NC  
NC  
MODE  
A
V
NC  
ZZ  
DD  
NC  
NC  
A
A
NC  
NC  
V
NC  
NC  
NC  
V
DDQ  
U
DDQ  
the specified address location. Byte writes are allowed. During  
byte writes, BW controls DQ , BW controls DQ , BW  
2
Functional Description  
0
[7:0]  
1
[15:8]  
Single Write Accesses Initiated by ADSP  
This access is initiated when the following conditions are sat-  
isfied at clock rise: (1) CE , CE , and CE are all asserted  
controls DQ  
, and BWS controls DQ  
. All I/Os are  
[23:16]  
3
[31:24]  
three-stated when a write is detected, even a byte write. Since  
this is a common I/O device, the asynchronous OE input signal  
must be deasserted and the I/Os must be three-stated prior to  
1
2
3
active, and (2) ADSP is asserted LOW. The addresses pre-  
sented are loaded into the address register and the burst  
counter/control logic and delivered to the RAM core. The write  
the presentation of data to DQ  
. As a safety precaution, the  
[31:0]  
data lines are three-stated once a write cycle is detected, re-  
gardless of the state of OE.  
inputs (GW, BWE, and BW  
) are ignored during this first  
[3:0]  
clock cycle. If the write inputs are asserted active (see Write  
Cycle Descriptions table for appropriate states that indicate a  
write) on the next clock rise, the appropriate data will be  
latched and written into the device. Byte writes are allowed.  
Single Read Accesses  
A single read access is initiated when the following conditions  
are satisfied at clock rise: (1) CE , CE , and CE are all as-  
1
2
3
serted active, and (2) ADSP or ADSC is asserted LOW (if the  
access is initiated by ADSC, the write inputs must be deassert-  
ed during this first cycle). The address presented to the ad-  
dress inputs is latched into the address register and the burst  
counter/control logic and presented to the memory core. If the  
OE input is asserted LOW, the requested data will be available  
During byte writes, BW controls DQ  
, BW controls  
0
[7:0]  
1
DQ  
, BW controls DQ  
, and BW controls DQ  
.
[31:24]  
[15:8]  
2
[23:16]  
3
All I/Os are three-stated during a byte write. Since this is a  
common I/O device, the asynchronous OE input signal must  
be deasserted and the I/Os must be three-stated prior to the  
presentation of data to DQ  
. As a safety precaution, the  
[31:0]  
at the data outputs a maximum to t  
after clock rise. ADSP  
data lines are three-stated once a write cycle is detected, re-  
gardless of the state of OE.  
CDV  
is ignored if CE is HIGH.  
1
Burst Sequences  
Single Write Accesses Initiated by ADSC  
This write access is initiated when the following conditions are  
The CY7C1338 provides an on-chip 2-bit wraparound burst  
counter inside the SRAM. The burst counter is fed by A  
satisfied at clock rise: (1) CE , CE , and CE are all asserted  
1
2
3
,
[1:0]  
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted  
HIGH, and (4) the write input signals (GW, BWE, and BW  
and can follow either a linear or interleaved burst order. The  
burst order is determined by the state of the MODE input. A  
LOW on MODE will select a linear burst sequence. A HIGH on  
MODE will select an interleaved burst order. Leaving MODE  
unconnected will cause the device to default to a interleaved  
burst sequence.  
)
[3:0]  
indicate a write access. ADSC is ignored if ADSP is active LOW.  
The addresses presented are loaded into the address register  
and the burst counter/control logic and delivered to the RAM  
core. The information presented to DQ  
will be written into  
[31:0]  
3
PRELIMINARY  
CY7C1345B  
Sleep Mode  
Table 1. Counter Implementation for the Intel®  
Pentium®/80486 Processor’s Sequence  
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed. Ac-  
cesses pending when entering the “sleep” mode are not con-  
sidered valid nor is the completion of the operation guaran-  
teed. The device must be deselected prior to entering the  
First  
Second  
Third  
Fourth  
Address  
Address  
Address  
Address  
A
, A  
A
,A  
A
, A  
A
, A  
X + 1 x  
X + 1  
x
X + 1  
x
X + 1  
x
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
“sleep” mode. CE , CE , CE , ADSP, and ADSC must remain  
1
2
3
inactive for the duration of t  
after the ZZ input returns  
ZZREC  
LOW. Leaving ZZ unconnected defaults the device into an ac-  
tive state.  
Table 2. Counter Implementation for a Linear Sequence  
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
A
, A  
A
, A  
A
, A  
A
, A  
X + 1 x  
X + 1  
x
X + 1  
x
X + 1  
x
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
4
PRELIMINARY  
CY7C1345B  
Cycle Description Table[1, 2, 3]  
ADD  
Cycle Description  
Used  
CE CE  
CE  
X
L
ZZ ADSP ADSP ADV WE  
OE CLK  
DQ  
L-H High-Z  
L-H High-Z  
L-H High-Z  
L-H High-Z  
L-H High-Z  
1
3
2
Deselected Cycle, Power-down  
Deselected Cycle, Power-down  
Deselected Cycle, Power-down  
Deselected Cycle, Power-down  
Deselected Cycle, Power-down  
Snooze Mode, Power-down  
Read Cycle, Begin Burst  
None  
H
L
X
X
H
X
X
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
None  
None  
L
X
L
L
None  
L
H
H
X
L
None  
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None  
X
X
X
L
X
High-Z  
Q
External  
External  
External  
External  
External  
Next  
L-H  
Read Cycle, Begin Burst  
L
L
L
H
X
L
L-H High-Z  
Write Cycle, Begin Burst  
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H  
L-H  
D
Q
Read Cycle, Begin Burst  
L
L
L
H
H
H
H
H
H
L
Read Cycle, Begin Burst  
L
L
L
H
L
L-H High-Z  
L-H  
L-H High-Z  
L-H  
L-H High-Z  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next  
L
H
L
Next  
L
Q
Next  
L
H
X
X
L
Next  
L
L-H  
L-H  
L-H  
D
D
Q
Next  
L
L
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z  
L-H  
L-H High-Z  
Q
H
X
X
L-H  
L-H  
D
D
Write Cycle, Suspend Burst  
L
Notes:  
1. X= “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.  
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks  
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE  
is a “Don't Care” for the remainder of the write cycle.  
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.  
5
PRELIMINARY  
CY7C1345B  
Write Cycle Descriptions[1, 2, 3, 4]  
Function  
GW  
1
BWE  
1
BW  
X
1
BW  
X
1
BW  
X
1
BW  
X
1
3
2
1
0
Read  
Read  
1
0
Write Byte 0, DP  
Write Byte 1, DP  
1
0
1
1
1
0
0
1
1
0
1
1
0
1
Write Bytes 1, 0, DP , DP  
1
0
1
1
0
0
0
1
Write Byte 2, DP  
1
0
1
0
1
1
2
Write Bytes 2, 0, DP , DP  
1
0
1
0
1
0
2
0
1
Write Bytes 2, 1, DP , DP  
1
0
1
0
0
1
2
Write Bytes 2, 1, 0, DP , DP , DP  
1
0
1
0
0
0
2
1
0
0
Write Byte 3, DP  
1
0
0
1
1
1
3
Write Bytes 3, 0, DP , DP  
1
0
0
1
1
0
3
0
0
Write Bytes 3, 1, DP , DP  
1
0
0
1
0
1
3
Write Bytes 3, 1, 0, DP , DP , DP  
1
0
0
1
0
0
3
1
Write Bytes 3, 2, DP , DP  
1
0
0
0
1
1
3
2
Write Bytes 3, 2, 0, DP , DP , DP  
1
0
0
0
1
0
3
2
0
1
Write Bytes 3, 2, 1, DP , DP , DP  
1
0
0
0
0
1
3
2
Write All Bytes  
Write All Bytes  
1
0
0
0
0
0
0
X
X
X
X
X
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Test Conditions  
ZZ > V − 0.2V  
Min  
Max  
Unit  
I
Snooze mode  
standby current  
3
mA  
ns  
CCZZ  
DD  
t
Deviceoperationto  
ZZ  
ZZ > V − 0.2V  
2t  
CYC  
ZZS  
DD  
t
ZZ recovery time  
ZZ < 0.2V  
2t  
ns  
ZZREC  
CYC  
[5]  
DC Input Voltage ................................ –0.5V to V + 0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage .......................................... >2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................–65°C to +150°C  
Latch-Up Current.................................................... >200 mA  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
Ambient  
DD  
[6]  
Range Temperature  
V
V
DDQ  
DD  
DC Voltage Applied to Outputs  
[5]  
in High Z State ....................................–0.5V to V + 0.5V  
DD  
Com’l  
0°C to +70°C  
3.135V to 3.6V 2.375V to V  
DD  
Notes:  
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.  
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.  
6. TA is the case temperature.  
6
PRELIMINARY  
CY7C1345B  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Test Conditions  
Min. Max. Unit  
V
V
Output HIGH Voltage  
V
V
V
V
= 3.3V, V = Min., I = –4.0 mA  
2.4  
1.7  
V
V
V
V
V
OH  
DDQ  
DDQ  
DDQ  
DDQ  
DD  
OH  
= 2.5V, V = Min., I = –2.0 mA  
DD  
OH  
Output LOW Voltage  
Input HIGH Voltage  
= 3.3V, V = Min., I = 8.0 mA  
0.4  
0.7  
OL  
DD  
OL  
= 2.5V, V = Min., I = 2.0 mA  
DD  
OL  
V
V
1.7  
V
+
DD  
IH  
IL  
0.3V  
0.8  
1
[5]  
Input LOW Voltage  
–0.3  
−1  
V
I
Input Load Current  
GND ≤ V ≤ V  
µA  
X
I
DDQ  
(except ZZ and MODE)  
Input Current of MODE  
Input = V  
Input = V  
Input = V  
Input = V  
–30  
–5  
µA  
µA  
µA  
µA  
µA  
SS  
5
DDQ  
SS  
Input Current of ZZ  
30  
5
DDQ  
I
I
I
Output Leakage Current  
GND ≤ V ≤ V , Output Disabled  
–5  
OZ  
OS  
DD  
I
DD  
[7]  
Output Short Circuit Current  
V
V
f = f  
= Max., V  
= GND  
–300 mA  
DD  
OUT  
V
Operating Supply Current  
= Max., I  
= 0 mA,  
8.5-ns cycle, 117 MHz  
10-ns cycle, 100 MHz  
11-ns cycle, 90 MHz  
20-ns cycle, 50 MHz  
350  
325  
300  
250  
35  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
DD  
DD  
OUT  
= 1/t  
CYC  
MAX  
I
Automatic CE Power-Down  
Current—TTL Inputs  
Max. V , Device Deselected, 8.5-ns cycle, 117 MHz  
DD  
V
f = f  
ing  
SB1  
≥ V or V ≤ V  
IN  
IH  
IN  
IL  
10-ns cycle, 100 MHz  
11-ns cycle, 90 MHz  
20-ns cycle, 50 MHz  
All speeds  
30  
= 1/t  
, inputs switch-  
MAX  
CYC  
25  
20  
I
I
Automatic CE Power-Down  
Current—CMOS Inputs  
Max. V , Device Deselected,  
V
f = 0, inputs static  
10  
SB2  
SB3  
DD  
≤ 0.3V or V > V  
– 0.3V,  
IN  
IN  
DDQ  
Automatic CE Power-Down  
Current—CMOS Inputs  
Max. V , Device Deselected,  
8.5-ns cycle, 117 MHz  
10-ns cycle, 100 MHz  
11-ns cycle, 90 MHz  
20-ns cycle, 50 MHz  
10  
10  
10  
10  
18  
mA  
mA  
mA  
mA  
mA  
DD  
V
≥ V  
– 0.3V or V ≤ 0.3V,  
IN  
DDQ IN  
f = f  
, inputs switching  
MAX  
I
Automatic CE Power-Down  
Max. V , Device Deselected,  
DD  
SB4  
Current—TTL Inputs  
V ≥V –0.3V or V ≤ 0.3V, f=0,  
IN DD IN  
inputs static  
Note:  
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.  
7
PRELIMINARY  
CY7C1345B  
Capacitance[8]  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
4.0  
Unit  
pF  
C
Input Capacitance  
I/O Capacitance  
IN  
A
V
= 5.0V  
DD  
C
4.0  
pF  
I/O  
AC Test Loads and Waveforms  
R1=317  
Ω
OUTPUT  
3.3V  
OUTPUT  
ALL INPUT PULSES  
90%  
3.0V  
GND  
Z =50  
Ω
90%  
10%  
0
R =50  
L
Ω
10%  
R2=351  
Ω
5 pF  
V =1.5V  
L
INCLUDING  
JIG AND  
SCOPE  
Rise Time: 1 V/ns  
Fall Time: 1 V/ns  
(a)  
(b)  
[9]  
Switching Characteristics Over the Operating Range  
-117  
-100  
-90  
-50  
Parameter  
Description  
Clock Cycle Time  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
8.5  
3.0  
3.0  
2.0  
0.5  
10  
4.0  
4.0  
2.0  
0.5  
11  
4.5  
4.5  
2.0  
0.5  
20  
4.5  
4.5  
2.0  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CYC  
CH  
Clock HIGH  
Clock LOW  
CL  
Address Set-Up Before CLK Rise  
Address Hold After CLK Rise  
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
ADSP, ADSC Set-Up Before CLK Rise  
ADSP, ADSC Hold After CLK Rise  
AS  
AH  
7.5  
8.0  
8.5  
11.0  
CDV  
DOH  
ADS  
ADH  
WES  
WEH  
ADVS  
ADVH  
DS  
2.0  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
BWS  
BWS  
, GW,BWE Set-Up Before CLK Rise  
, GW,BWE Hold After CLK Rise  
[1:0]  
[1:0]  
ADV Set-Up Before CLK Rise  
ADV Hold After CLK Rise  
Data Input Set-Up Before CLK Rise  
Data Input Hold After CLK Rise  
Chip Enable Set-Up  
DH  
CES  
CEH  
CHZ  
CLZ  
EOHZ  
EOLZ  
EOV  
Chip Enable Hold After CLK Rise  
[10, 11]  
Clock to High-Z  
3.5  
3.5  
3.5  
3.5  
3.5  
3.5  
3.5  
3.5  
3.5  
3.5  
3.5  
3.5  
[10, 11]  
Clock to Low-Z  
0
0
0
0
0
0
0
0
[10, 12]  
OE HIGH to Output High-Z  
[10, 12]  
OE LOW to Output Low-Z  
OE LOW to Output Valid  
Notes:  
8. Tested initially and after any design or process changes that may affect these parameters.  
9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and  
output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads.  
10. tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.  
11. At any given voltage and temperature, tCHZ (max.) is less than tCLZ (min.).  
12. This parameter is sampled and not 100% tested.  
8
PRELIMINARY  
CY7C1345B  
Timing Diagrams  
[13, 14]  
Write Cycle Timing  
Single W rite  
Burst W rite  
Pipelined Write  
t
Unselected  
CH  
t
CYC  
CLK  
t
ADH  
t
ADS  
t
ADSP ignored with CE inactive  
CL  
1
ADSP  
t
ADH  
t
ADSC initiated write  
ADS  
ADSC  
ADV  
t
t
ADVH  
ADVS  
t
ADV Must Be Inactive for ADSP Write  
WD2  
AS  
WD3  
WD1  
ADD  
GW  
WE  
t
AH  
t
WH  
t
WH  
t
WS  
t
WS  
t
t
CES  
CEH  
CE masks ADSP  
1
CE  
1
t
t
CEH  
CES  
Unselected with CE  
2
CE  
CE  
2
3
t
CES  
t
CEH  
OE  
t
DH  
t
DS  
High-Z  
High-Z  
Data-  
In  
3a  
2a  
= UNDEFINED  
2c  
2d  
1a  
2b  
= DON’T CARE  
Notes:  
13. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table).  
14. WDx stands for Write Data to Address X.  
9
PRELIMINARY  
CY7C1345B  
Timing Diagrams (continued)  
[13, 15]  
Read Cycle Timing  
Burst Read  
Single Read  
Unselected  
t
t
CYC  
CH  
Pipelined Read  
CLK  
t
t
ADH  
ADS  
t
ADSP ignored with CE inactive  
CL  
1
ADSP  
t
ADS  
ADSC initiated read  
ADSC  
ADV  
t
ADVS  
t
ADH  
Suspend Burst  
t
t
ADVH  
AS  
ADD  
GW  
WE  
RD3  
RD1  
RD2  
t
AH  
t
WS  
t
WS  
t
WH  
t
t
CES  
CEH  
t
WH  
CE masks ADSP  
1
CE  
CE  
1
2
Unselected with CE  
2
t
t
CES  
t
CEH  
CE  
OE  
3
t
CEH  
CES  
t
EOV  
t
OEHZ  
t
DOH  
t
CDV  
3a  
Data Out  
2d  
2a  
2b  
2c  
1a  
t
CLZ  
t
CHZ  
= DON’T CARE  
= UNDEFINED  
Note:  
15. RDx stands for Read Data from Address X.  
10  
PRELIMINARY  
CY7C1345B  
Timing Diagrams (continued)  
Read/Write Timing  
t
t
t
CYC  
CL  
CH  
CLK  
t
AH  
t
t
AS  
A
D
B
C
ADD  
t
ADH  
ADS  
ADSP  
ADSC  
ADV  
t
t
ADH  
ADS  
t
t
ADVH  
ADVS  
t
CEH  
t
CES  
CE  
1
t
t
CEH  
CES  
CE  
t
t
WES  
WEH  
WE  
ADSP ignored  
with CE HIGH  
1
OE  
t
EOHZ  
D(C)  
t
t
CLZ  
Data  
D
(C+3)  
Q
(B+3)  
D
(C+1)  
D
(C+2)  
Q
(B+2)  
Q
(B+1)  
Q(B)  
Q(B)  
Q(A)  
Q(D)  
In/Out  
CDV  
t
DOH  
t
CHZ  
Device originally  
deselected  
WE is the combination of BWE, BWS  
, and GW to define a write cycle (see Write Cycle Descriptions table).  
[1:0]  
CE is the combination of CE and CE . All chip selects need to be active in order to select  
2
3
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,  
Qx stands for Data-out X.  
= UNDEFINED  
= DON’T CARE  
11  
PRELIMINARY  
CY7C1345B  
Timing Diagrams (continued)  
Pipeline Timing  
t
t
t
CYC  
CL  
CH  
CLK  
t
AS  
WD1  
WD2  
WD3  
WD4  
RD1  
RD2  
RD3  
RD4  
ADD  
t
t
ADS  
ADH  
ADSC initiated Reads  
ADSC  
ADSP  
ADV  
ADSP initiated Reads  
t
t
CEH  
CES  
CE  
1
CE  
t
t
WEH  
WES  
WE  
OE  
ADSP ignored  
with CE HIGH  
1
t
CLZ  
Data In/Out  
1a  
In  
1a  
2a  
3a  
4a  
2a  
In  
3a  
In  
4a  
In
Out Out Out Out  
t
CDV  
t
DOH  
Back to Back Reads  
t
CHZ  
Back to Back Writes  
= UNDEFINED  
= DON’T CARE  
12  
PRELIMINARY  
CY7C1345B  
Timing Diagrams (continued)  
OE Switching Waveforms  
OE  
t
EOV  
t
EOHZ  
three-state  
I/Os  
t
EOLZ  
13  
PRELIMINARY  
CY7C1345B  
Timing Diagrams (continued)  
[16, 17]  
ZZ Mode Timing  
CLK  
ADSP  
HIGH  
ADSC  
CE  
CE  
1
2
LOW  
HIGH  
CE  
3
ZZ  
t
ZZS  
I
CC  
I
(active)  
CC  
t
ZZREC  
I
CCZZ  
I/Os  
Three-state  
Notes:  
16. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.  
17. I/Os are in three-state when exiting ZZ sleep mode.  
14  
PRELIMINARY  
CY7C1345B  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(MHz)  
117  
100  
90  
Ordering Code  
Package Type  
CY7C1345B-117AC  
CY7C1345B-100AC  
CY7C1345B-90AC  
CY7C1345B-50AC  
A101  
A101  
A101  
A101  
100-Lead Thin Quad Flat Pack  
100-Lead Thin Quad Flat Pack  
100-Lead Thin Quad Flat Pack  
100-Lead Thin Quad Flat Pack  
Commercial  
50  
Document #: 38-00953-*A  
Package Diagram  
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101  
51-85050-A  
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  

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