CY7C1347D-225BGC [CYPRESS]
128K x 36 Synchronous-Pipelined Cache SRAM; 128K ×36的同步流水线高速缓存SRAM
| 型号： | CY7C1347D-225BGC |
| 厂家： | 
CYPRESS |
| 描述： | 128K x 36 Synchronous-Pipelined Cache SRAM |
| 文件： | 总21页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1347D
128K x 36 Synchronous-Pipelined Cache SRAM
Features
Functional Description
• Fast access times: 2.5 and 3.5 ns
This Cypress Synchronous Burst SRAM employs high-speed,
low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
• Fast clock speed: 250, 225, 200, and 166 MHz
• 1.5-ns set-up time and 0.5-ns hold time
• Fast OE access times: 2.5 ns and 3.5 ns
The CY7C1347D SRAM integrate 131,072 x 36 SRAM cells
with advanced synchronous peripheral circuitry and a 2-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE), depth-expansion Chip Enables (CE2 and CE2), Burst
Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa,
BWb, BWc, BWd, and BWE), and Global Write (GW).
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
• Three chip enables for depth expansion and address
pipeline
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
pin (ADV).
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written.
• Automatic power-down for portable applications
• JTAG boundary scan
• JEDEC standard pinout
• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Four pins are used to implement JTAG test capabilities: Test
Mode Select (TMS), Test Data-in (TDI), Test Clock (TCK), and
Test Data-out (TDO). The JTAG circuitry is used to serially shift
data to and from the device. JTAG inputs use LVTTL/LVCMOS
levels to shift data during this testing mode of operation.
The CY7C1347D operates from a +3.3V power supply. All
inputs and outputs are LVTTL-compatible
Selection Guide
CY7C1347D-250 CY7C1347D-225 CY7C1347D-200
CY7C1347D-166
Maximum Access Time (ns)
2.5
450
10
2.5
400
10
2.5
360
10
3.5
300
10
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 38-05022 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 30, 2004
CY7C1347D
Functional Block Diagram—CY7C1347D[1]
BYTE a WRITE
BWa#
BWE#
D
Q
CLK
BYTE b WRITE
BWb#
D
Q
GW#
BYTE c WRITE
BWc#
D
Q
BYTE d WRITE
BWd#
D
Q
ENABLE
CE#
CE2
D
Q
D
Q
CE2#
OE#
ZZ
Power Down Logic
Input
Register
ADSP#
15
A
Address
Register
OUTPUT
REGISTER
ADSC#
DQa,DQb
DQc,DQd
CLR
D
Q
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Note:
1. The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05022 Rev. *D
Page 2 of 21
CY7C1347D
Pin Configurations
100-Pin TQFP
Top View
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
1
2
3
4
5
6
7
8
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
CY7C1347D
Document #: 38-05022 Rev. *D
Page 3 of 21
CY7C1347D
Pin Configurations (continued)
119-Ball BGA
Top View
1
2
3
A
4
ADSP
ADSC
VCC
NC
5
6
7
A
B
C
D
E
F
VCCQ
NC
A
A
A
VCCQ
NC
CE2
A
A
A
CE2
A
NC
A
A
NC
DQc
DQc
VCCQ
DQc
DQc
VCCQ
DQd
DQd
VCCQ
DQd
DQd
NC
DQc
DQc
DQc
DQc
DQc
VCC
DQd
DQd
DQd
DQd
DQd
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQb
DQb
DQb
DQb
DQb
VCC
DQa
DQa
DQa
DQa
DQa
A
DQb
DQb
VCCQ
DQb
DQb
VCCQ
DQa
DQa
VCCQ
DQa
DQa
NC
CE
OE
G
H
J
ADV
GW
VCC
CLK
NC
K
L
VSS
BWd
VSS
VSS
VSS
MODE
A
M
N
P
R
T
BWE
A1
A0
VCC
A
NC
NC
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
CY7C1347D Pin Descriptions
BGA Pins
QFP Pins
Name
Type
Input-
Description
Addresses: These inputs are registered and must meet the
4P
4N
37
36
A0
A1
A
Synchronous set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C, 100, 99, 82, 81,
35, 34, 33, 32,
5C, 6C, 2R, 6R,
3T, 4T, 5T
44, 45, 46, 47,
48, 49, 50
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
Input-
Byte Write: A byte write is LOW for a Write cycle and HIGH for
Synchronous a Read cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
4H
4K
87
88
89
BWE
GW
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the set-up and hold times around the rising edge
of CLK.
Input-
Global Write: This active LOW input allows a full 36-bit Write to
Synchronous occur independent of the BWE and BWn lines and must meet
the set-up and hold times around the rising edge of CLK.
CLK
Input-
Clock: This signal registers the addresses, data, chip enables,
Synchronous write control and burst control inputs on its rising edge. All
synchronous inputs must meet set-up and hold times around
the clock’s rising edge.
4E
6B
2U
98
92
38
CE
Input-
Chip Enable: This active LOW input is used to enable the device
Synchronous and to gate ADSP.
CE2
TMS
Input-
Synchronous device.
Chip Enable: This active LOW input is used to enable the
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VSS.
Page 4 of 21
Document #: 38-05022 Rev. *D
CY7C1347D
CY7C1347D Pin Descriptions (continued)
BGA Pins
QFP Pins
Name
Type
Description
2U
39
TDI
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VCC.
3U
5U
43
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VSS
or VCC.
42
TDO
NC
Output
–
IEEE 1149.1 test output. LVTTL-level output. If JTAG feature is
not utilized, this pin should be disconnected.
1B,7B,1C,7C,4D,
3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 6U
14, 16, 66
No Connect: These signals are not internally connected.
Burst Address Table (MODE = NC/VCC
)
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Truth Table [2, 3, 4, 5, 6, 7]
Address
Used
Operation
CE CE2 CE2 ADSP ADSC
ADV
X
X
X
X
X
X
X
X
X
X
L
Write
OE
X
X
X
X
X
L
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Read Cycle, Begin Burst
None
None
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
L
None
L
X
L
L
None
L
H
H
L
None
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
L
External
External
External
External
External
Next
L
X
X
L
Read Cycle, Begin Burst
L
L
L
H
X
L
High-Z
D
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Q
Read Cycle, Begin Burst
L
L
L
H
L
High-Z
Q
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
H
H
H
H
Q
Read Cycle, Suspend Burst
H
High-Z
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH. BWa enables write to
DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
3. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
7. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the
CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Document #: 38-05022 Rev. *D
Page 5 of 21
CY7C1347D
Truth Table (continued)[2, 3, 4, 5, 6, 7]
Address
Operation
Used
CE CE2 CE2 ADSP ADSC
ADV
H
Write
OE
L
CLK
L-H
L-H
L-H
L-H
DQ
Q
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Current
Current
Current
Current
H
H
X
H
X
X
X
X
X
X
X
X
X
X
H
X
H
H
H
H
H
H
L
H
H
High-Z
D
H
X
H
L
X
D
Partial Truth Table for Read/Write
FUNCTION
GW
BWE
BWa
BWb
BWc
X
BWd
Read
Read
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
H
Write one byte
Write all bytes
Write all bytes
H
L
L
X
X
X
X
TDI –Test Data In (INPUT)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register (refer to Figure 1). It is allowable to leave this pin
unconnected if it is not used in an application. The pin is pulled
up internally, resulting in a logic HIGH level. TDI is connected
to the most significant bit (MSB) of any register (see Figure 2).
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the critical speed path of the device. Never-
theless, the device supports the standard TAP controller archi-
tecture (the TAP controller is the state machine that controls
the TAPs operation) and can be expected to function in a
manner that does not conflict with the operation of devices with
IEEE Standard 1149.1-compliant TAPs. The TAP operates
using LVTTL/LVCMOS logic level signaling.
TDO – Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1). Output changes in
response to the falling edge of TCK. This is the output side of
the serial registers placed between TDI and TDO. TDO is
connected to the least significant bit (LSB) of any register (see
Figure 2).
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Performing a TAP Reset
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (VCC
)
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
Test Access Port (TAP)
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
TCK –Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
Test Access Port (TAP) Registers
Overview
TMS – Test Mode Select (INPUT)
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
Document #: 38-05022 Rev. *D
Page 6 of 21
CY7C1347D
Instruction Register
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST,
INTEST, or the preload portion of the SAMPLE/PRELOAD
command.
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The parallel outputs of
the instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the controller
is placed in the test-logic reset state. When the TAP controller
is in the Capture-IR state, the two least significant bits of the
serial instruction register are loaded with a binary “01” pattern
to allow for fault isolation of the board-level serial test data
path.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the
instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
Bypass Register
EXTEST
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
with minimum delay. The bypass register is set LOW (VSS
)
when the BYPASS instruction is executed.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instruc-
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
Boundary Scan Register
The Boundary scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for x36 device and 51
bits for x18 device. The boundary scan register, under the
control of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the
controller is moved to Shift-DR state. The EXTEST, SAMPLE/
PRELOAD and SAMPLE-Z instructions can be used to
capture the contents of the I/O ring.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s
position in the boundary scan register. The MSB of the register
is connected to TDI, and LSB is connected to TDO. The
second column is the signal name and the third column is the
bump number. The third column is the TQFP pin number and
the fourth column is the BGA bump number.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
Identification (ID) Register
SAMPLE/PRELOAD
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded in the
instruction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture setup plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the IEEE
Standard 1149.1-1990; the standard (public) instructions and
device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
Document #: 38-05022 Rev. *D
Page 7 of 21
CY7C1347D
Moving the controller to Shift-DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not imple-
mented in this device, moving the controller to the Update-DR
state with the SAMPLE/PRELOAD instruction loaded in the
instruction register has the same effect as the Pause-DR
command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP controller is in the Shift-DR state, the
bypass register is placed between TDI and TDO. This allows
the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
Reserved
Do not use these instructions. They are reserved for future
use.
TEST-LOGIC
1
RESET
0
1
1
1
REUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
1
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Figure 1. TAP Controller State Diagram[8]
Note:
8. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05022 Rev. *D
Page 8 of 21
CY7C1347D
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register [9]
TDI
TDI
TAP Controller
Figure 2. TAP Controller Block Diagram
TAP DC Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted)
Parameter
Description
Test Conditions
VCCQ = 3.3 V
CCQ = 2.5V
VCCQ = 3.3 V
CCQ = 2.5V
Min.
2.0
Max.
Unit
V
VIH
Input High (Logic 1)
4.6
4.6
Voltage: Inputs[10, 11]
V
1.7
V
Input High (Logic 1)
Voltage: Data[10, 11]
2.0
VCCQ + 0.3
VCCQ + 0.3
0.8
V
V
1.7
VIL
Input Low (Logic 0) Voltage: Inputs and VCCQ = 3.3 V
Data[10, 11]
–0.5
–0.3
–5.0
–30
–5.0
V
VCCQ = 2.5V
0.7
V
ILI
Input Leakage Current
0V < VIN < VCC
5.0
µA
µA
µA
ILI
TMS and TDI Input Leakage Current 0V < VIN < VCC
30
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
5.0
VOLC
VOHC
LVCMOS Output Low Voltage[10, 12] IOLC = 100 µA
LVCMOS Output High Voltage[10, 12] IOHC = 100 µA
0.2
V
V
VCCQ – 0.2
Notes:
9. X = 69.
10. All Voltage referenced to V (GND).
SS
11. Overshoot: V (AC)<V +1.5V for t<t
/2, Undershoot: V (AC)<–0.5V for t<t
/2, Power-up: V <3.6V and V <3.135V and V <1.4V for t<200 ms.
CCQ
IH
CC
KHKH
IL
KHKH
IH
CC
During normal operation, V
must not exceed 3.6V. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than t
(min.).
KHKL
CCQ
12. This parameter is sampled.
Document #: 38-05022 Rev. *D
Page 9 of 21
CY7C1347D
TAP DC Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted) (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOLT
LVTTL Output Low Voltage[10]
VCC = Min. VCCQ =3.3 V, IOLT
= 8.0 mA
0.4
V
VCC = Min. VCCQ = 2.5V, IOLT
= 2.0 mA
0.7
0.4
V
V
V
V
VCC = Min. VCCQ = 2.5V, IOLT
= 1.0 mA
VOHT
LVTTL Output High Voltage[10]
VCC = Min. VCCQ = 3.3 V, IOH
= –4.0 mA
2.4
2.0
VCC = Min, VCCQ = 2.5V,
IOH = –2.0 mA
TAP AC Switching Characteristics Over the Operating Range[13, 14]
Parameter
Clock
Description
Min.
Max
Unit
tTHTH
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
20
ns
MHz
ns
fTF
50
tTHTL
8
8
tTLTH
ns
Output Times
tTLQX
TCK LOW to TDO Unknown
TCK LOW to TDO Valid
TDI Valid to TCK HIGH
TCK HIGH to TDI Invalid
0
ns
ns
ns
ns
tTLQV
10
tDVTH
5
5
tTHDX
Set-up Times
tMVTH
TMS Set-up
5
5
ns
ns
tCS
Capture Set-up
Hold Times
tTHMX
TMS Hold
5
5
ns
ns
tCH
Capture Hold
Notes:
13. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
14. Test conditions are specified using the load in TAP AC Test Conditions.
Document #: 38-05022 Rev. *D
Page 10 of 21
CY7C1347D
TAP Timing and Test Conditions
ALL INPUT PULSES
3.3V / 2.5V
TDO
Z0 = 50 Ω
50 Ω
for 3.3V VCCQ or
20 pF
1.5V
VSS
1.5 ns
Vt = 1.5V
1.5 ns
(a)
V
/2 for 2.5V V
CCQ
CCQ
t
t
THTL
TLTH
t
THTH
TEST CLOCK
(TCK)
t
t
MVTH
THMX
TEST MODE SELECT
(TMS)
t
t
DVTH
THDX
TEST DATA IN
(TDI)
t
TLQV
t
TLQX
TEST DATA OUT
(TDO)
Identification Register Definitions
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
128K x 36
XXXX
Description
Reserved for revision number.
Defines depth of words.
Defines width of bits.
00111
Device Width (22:18)
00011
Reserved (17:12)
XXXXXX
00011100100
1
Reserved for future use.
Cypress Jedec Id Code (11:1)
ID Register Presence Indicator (0)
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bit Size (x36)
3
1
Bypass
ID
32
51
Boundary Scan
Document #: 38-05022 Rev. *D
Page 11 of 21
CY7C1347D
Instruction Codes
Instruction
Code
Description
EXTEST
000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
device outputs to High-Z state. This instruction is not IEEE 1149.1-compliant.
IDCODE
001 Preloads ID register with vendor ID code and places it between TDI and TDO. This instruction
does not affect device operations.
SAMPLE-Z
010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
device outputs to High-Z state.
RESERVED
011 Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This
instruction does not affect device operations. This instruction does not implement IEEE 1149.1
PRELOAD function and is therefore not 1149.1-compliant.
RESERVED
RESERVED
BYPASS
101 Do not use these instructions; they are reserved for future use.
110 Do not use these instructions; they are reserved for future use.
111 Places the bypass register between TDI and TDO. This instruction does not affect device opera-
tions.
Boundary Scan Order
Boundary Scan Order (continued)
Bit#
1
Signal Name
A
TQFP
44
45
46
47
48
49
50
51
52
53
56
57
58
59
62
63
64
68
69
72
73
74
75
78
79
80
81
82
83
Bump ID
2R
3T
Bit#
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Signal Name
ADSP
ADSC
OE
TQFP
84
85
86
87
88
89
92
93
94
95
96
97
98
99
100
1
Bump ID
4A
2
A
4B
3
A
4T
64F
4M
4H
4K
4
A
5T
BWE
GW
5
A
6R
3B
5B
6P
7N
6M
7L
6
A
CLK
CE2
7
A
6B
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
BWa
BWb
BWc
BWd
CE2
5L
9
5G
3G
3L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
6K
7P
6N
6L
2B
CE
4E
A
3A
A
2A
7K
7T
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
2D
1E
2
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
6H
7G
6F
3
2F
6
1G
2H
1D
2E
7
7E
6D
7H
6G
6E
7D
6A
5A
4G
8
9
12
13
14
18
19
22
23
2G
1H
5R
2K
DQd
DQd
DQd
DQd
1L
A
2M
1N
ADV
Document #: 38-05022 Rev. *D
Page 12 of 21
CY7C1347D
Boundary Scan Order (continued)
Bit#
59
60
61
62
63
64
65
66
67
68
69
70
Signal Name
TQFP
24
Bump ID
2P
DQd
DQd
DQd
DQd
DQd
MODE
A
25
1K
28
2L
29
2N
30
1P
31
3R
32
2C
A
33
3C
A
34
5C
A
35
6C
A1
36
4N
A0
37
4P
Document #: 38-05022 Rev. *D
Page 13 of 21
CY7C1347D
Power Dissipation.......................................................... 1.0W
Short Circuit Output Current........................................ 50 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V
Ambient
VIN ...........................................................–0.5V to VCC+0.5V
Range
Com’l
Temperature[15]
VCC
Storage Temperature (plastic) ...................... –55°C to +150°
Junction Temperature ..................................................+150°
0°C to +70°C
3.3V −5%/+10%
Electrical Characteristics Over the Operating Range
Parameter
VIH
Description
Test Conditions
VCCQ = 3.3 V
CCQ = 2.5V
VCCQ = 3.3 V
CCQ = 2.5V
Min.
2.0
Max.
Unit
V
Input High (Logic 1)
4.6
Voltage: Inputs[10, 11]
V
1.7
4.6
V
Input High (Logic 1)
Voltage: Data[10, 11]
2.0
VCCQ + 0.3
V
V
1.7
VCCQ + 0.3
VIL
Input Low (Logic 0) Voltage: Inputs VCCQ = 3.3 V
and Data[10, 11]
–0.5
–0.3
–5
0.8
0.7
5
V
V
VCCQ = 2.5V
ILI
ILI
Input Leakage Current
0V < VIN < VCC
0V < VIN < VCC
µA
µA
MODE and ZZ Input Leakage
Current[17]
–30
30
ILO
Output Leakage Current
Output High Voltage[10]
Output(s) disabled, 0V < VOUT < VCC
VCC = Min, VCCQ = 3.3 V, IOH = –4.0 mA
–5
2.4
2.0
5
µA
V
V
V
V
V
V
V
V
VOH
VCC = Min, VCCQ = 2.5V, IOH = –2.0 mA
VOL
Output Low Voltage[10]
VCC = Min, VCCQ = 3.3V, IOL = 8.0 mA
VCC = Min, VCCQ = 2.5V, IOH = 2.0 mA
0.4
0.7
0.4
3.6
3.6
2.9
VCC = Min, VCCQ = 2.5V, IOH = 1.0 mA
VCC
Supply Voltage[10]
I/O Supply Voltage[10]
3.135
3.135
2.375
VCCQ
3.3 V Range
2.5 V Range
Parameter
Description
Conditions
Typ.
-4
-4.4
-5
-6
Unit
ICC
PowerSupplyCurrent: Device selected; all inputs < VILor > VIH;
150
450
400
360
300
mA
Operating[18, 19, 20]
cycle time > tKC min.; VCC = Max.;
outputs open
ISB2
CMOS Standby[19, 20] Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or >VCC – 0.2;
5
10
10
20
10
20
10
mA
mA
mA
all inputs static; CLK frequency = 0
ISB3
TTL Standby[19, 20]
Device deselected; all inputs < VIL
or > VIH; all inputs static;
10
40
20
20
V
CC = Max.; CLK frequency = 0
Clock Running[19, 20] Device deselected; all inputs < VIL or > VIH;
CC = Max.; CLK cycle time > tKC min.
ISB4
140
125
110
90
V
Notes:
15. T is the case temperature.
A
16. Overshoot: V ≤ +6.0V for t ≤ t /2.
IH
IL
KC
KC
Undershoot:V ≤ –2.0V for t ≤ t /2.
17. Output loading is specified with C = 5 pF as in AC Test Loads.
L
18. I is given with no output current. I increases with greater output loading and faster cycle times.
CC
CC
19. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
20. Typical values are measured at 3.3V, 25°C, and 20-ns cycle time.
Document #: 38-05022 Rev. *D
Page 14 of 21
CY7C1347D
Capacitance[12]
Parameter
Description
Input Capacitance
Test Conditions
Typ.
Max.
Unit
pF
CI
TA = 25°C, f = 1 MHz,
CC = 3.3V
5
7
7
8
V
CO
Input/Output Capacitance (DQ)
pF
Thermal Resistance
Parameter
Description
Test Conditions
TQFP Typ.
BGA Typ.
Unit
ΘJA
ΘJC
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x
25
9
50
8
°C/W
°C/W
1.125 inch, 4-layer PCB
Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms[21]
317Ω / 225Ω
3.3V / 2.5V
3.3V / 2.5V
DQ
DQ
ALL INPUT PULSES
90%
90%
Z =50Ω
0
50Ω
10%
10%
5 pF
0V
351Ω
≤ 1.5 ns
≤ 1.5 ns
V
/ 225Ω
= 1.5Vfor 3.3V VCCQ
t
or VCCQ/2 for 2.5V VCCQ
(c)
(a)
(b)
Switching Characteristics Over the Operating Range[22]
250 MHz
225 MHz
200 MHz
166 MHz
Parameter
Clock
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tKC
Clock Cycle Time
4.0
1.6
1.6
4.4
1.7
1.7
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
tKH
Clock HIGH Time
Clock LOW Time
tKL
Output Times
tKQ
Clock to Output Valid
2.4
2.5
3.0
3.5
ns
ns
ns
ns
ns
ns
ns
tKQX
Clock to Output Invalid
1.25
0
1.25
0
1.25
0
1.25
0
tKQLZ
tKQHZ
tOEQ
Clock to Output in Low-Z[12, 17, 23]
Clock to Output in High-Z[12, 17, 23]
OE to Output Valid[24]
1.25
3.0
2.5
1.25
3.0
2.5
1.25
3.0
2.5
1.25
4.0
3.5
tOELZ
tOEHZ
Set-up Times
tS
OE to Output in Low-Z[12, 17, 23]
OE to Output in High-Z[12, 17, 23]
0
0
0
0
2.5
2.5
2.5
3.5
Address, Controls, and Data In[25]
Address, Controls, and Data In[25]
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
ns
ns
Hold Times
tH
Notes:
21. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH <
2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
22. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
23. At any given temperature and voltage condition, t
is less than t
and t
is less than t
.
KQHZ
KQLZ
OEHZ
OELZ
24. OE is a “Don’t Care” when a byte write enable is sampled LOW.
25. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t care”
as defined in the truth table.
Document #: 38-05022 Rev. *D
Page 15 of 21
CY7C1347D
Typical Output Buffer Characteristics
Output High Voltage
Pull-Up Current
Output Low Voltage
Pull-Down Current
V
OH (V)
–0.5
0
IOH (mA) Min. IOH (mA) Max.
VOL (V)
–0.5
0
IOL (mA) Min. IOL(mA) Max.
–38
–38
–38
–26
–20
0
–105
–105
–105
–83
–70
–30
–10
0
0
0
0
0
0.8
0.4
10
20
31
40
40
40
40
20
40
63
80
80
80
80
1.25
1.5
0.8
1.25
1.6
2.3
2.7
0
2.8
2.9
0
3.2
3.4
0
0
3.4
Switching Waveforms
Read Timing[26, 27]
tKC
tKL
CLK
tKH
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
tH
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
tS
CE#
ADV#
OE#
DQ
tS
tH
tKQ
tKQ
tOEQ
tOELZ
tKQLZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
SINGLE READ
BURST READ
Notes:
26. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active.
27. For X18 product, there are only BWa and BWb for byte write control.
Document #: 38-05022 Rev. *D
Page 16 of 21
CY7C1347D
Switching Waveforms (continued)
Write Timing[26, 27]
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
A3
tH
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
GW#
CE#
tS
ADV#
OE#
DQ
tH
tOEHZ
tKQX
Q
D(A1)
D(A2) D(A2+1) D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1) D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
Document #: 38-05022 Rev. *D
Page 17 of 21
CY7C1347D
Switching Waveforms (continued)
Read/Write Timing[26, 27]
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A2
A3
A4
A5
A1
tH
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
CE#
ADV#
OE#
DQ
Q(A1)
Q(A2)
D(A3)
Single Write
Q(A4)
Q(A4+1) Q(A4+2)
D(A5)
D(A5+1)
Single Reads
Burst Read
Burst Write
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
CY7C1347D-250AC
Package Type
250
A101
BG119
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial
119-Lead FBGA (14 x 22 x 2.4 mm)
CY7C1347D-250BGC
CY7C1347D-225BGC
CY7C1347D-200AC
CY7C1347D-166AC
225
200
166
119-Lead FBGA (14 x 22 x 2.4 mm)
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
A101
Document #: 38-05022 Rev. *D
Page 18 of 21
CY7C1347D
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05022 Rev. *D
Page 19 of 21
CY7C1347D
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05022 Rev. *D
Page 20 of 21
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1347D
Document History Page
Document Title: CY7C1347D: 128K x 36 Synchronous-Pipelined Cache SRAM
Document Number: 38-05022
Orig. of
Rev.
**
ECN No. Issue Date Change
Description of Change
106740
107485
05/07/01
06/06/01
RCS
RCS
New Data Sheet
*A
Added Minimum and Maximum values for 2.5V VCCQ
and all other subsequent parameters.
Defined alternate options for non-utilized JTAG pins.
*B
*C
*D
121064
122474
212291
11/13/02
01/18/03
See ECN
DSG
RBI
Updated package drawing 51-85115 (BG119) to rev. *B
Added power up requirements to AC test loads and waveforms information
Corrected Ordering Info section : delete 166BGA, 200BGA, 225AC
VBL
Document #: 38-05022 Rev. *D
Page 21 of 21
相关型号：
CY7C1347F-133ACT
Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
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