CY7C135-20JC [CYPRESS]
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores; 4K ×8双端口静态RAM和4K ×8双端口SRAM与信号灯
| 型号： | CY7C135-20JC |
| 厂家： | 
CYPRESS |
| 描述： | 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores |
| 文件： | 总12页 (文件大小：554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C135
CY7C1342
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port
SRAM with Semaphores
Features
Functional Description
• True Dual-Ported memory cells which allow simulta-
The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8
dual-port static RAMs. The CY7C1342 includes semaphores
that provide a means to allocate portions of the dual-port RAM
or any shared resource. Two ports are provided permitting in-
dependent, asynchronous access for reads and writes to any
location in memory. Application areas include interproces-
sor/multiprocessor designs, communications status buffering,
and dual-port video/graphics memory.
neous reads of the same memory location
• 4K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Semaphoresincludedonthe7C1342topermitsoftware
handshaking between ports
• Available in 52-pin PLCC
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). The
CY7C135 is suited for those systems that do not require
on-chip arbitration or are intolerant of wait states. Therefore,
the user must be aware that simultaneous access to a location
is possible. Semaphores are offered on the CY7C1342 to as-
sist in arbitrating between ports. The semaphore logic is com-
prised of eight shared latches. Only one side can control the
latch (semaphore) at any time. Control of a semaphore indi-
cates that a shared resource is in use. An automatic pow-
er-down feature is controlled independently on each port by a
chip enable (CE) pin or SEM pin (CY7C1342 only).
The CY7C135 and CY7C1342 are available in 52-pin PLCC.
Logic Block Diagram
R/W
L
R/W
R
CE
L
CE
R
OE
R
OE
L
I/O
7L
I/O
I/O
7R
I/O
CONTROL
I/O
CONTROL
I/O
0L
0R
A
A
11L
0L
11R
ADDRESS
DECODER
ADDRESS
DECODER
MEMORY
ARRAY
A
A
0R
SEMAPHORE
ARBITRATION
(7C1342 only)
CE
L
CE
R
OE
L
OE
R
R/W
R/W
R
L
(7C1342 only)
(7C1342 only)
1342–1
SEM
R
SEM
L
Cypress Semiconductor Corporation
Document #: 38-06038 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised June 22, 2004
CY7C135
CY7C1342
Selection Guide
7C135–15
7C1342–15
7C135–20
7C1342–20
7C135–25
7C1342–25
7C135–35
7C1342–35
7C135–55
7C1342–55
Maximum Access Time (ns)
15
20
25
35
55
Maximum Operating
Current (mA)
Commercial
220
190
180
160
160
Maximum Standby
Current for ISB1(mA)
Commercial
60
50
40
30
30
Pin Configurations
PLCC
Top View
7
6 5 4 3 2 1 52 51 50 49 48 47
A
OE
1L
8
46
45
44
43
42
41
40
39
38
37
36
35
34
R
A
A
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
A
A
A
A
A
A
9
0R
1R
2R
3R
10
11
12
13
14
15
16
17
18
19
20
A
A
A
7C135
4R
5R
A
A
A
6R
A
7R
A
8R
A
9R
A
I/O
I/O
I/O
I/O
2L
NC
I/O
3L
7R
21 22 23 24 25 26 27 28 29 30 31 32 33
1342–3
PLCC
Top View
7
6 5 4 3 2 1 52 51 50 49 48 47
A
OE
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
2L
3L
8
46
45
44
43
42
41
40
39
38
37
36
35
34
R
A
A
A
A
A
A
A
A
A
A
9
0R
1R
2R
3R
4R
5R
10
11
12
13
14
15
16
17
18
19
20
A
A
A
7C1342
A
A
6R
7R
A
I/O
I/O
I/O
I/O
A
A
8R
9R
NC
I/O
7R
21 22 23 24 25 26 27 28 29 30 31 32 33
1342–4
Pin Definitions
Left Port
A0L–11L
Right Port
Description
A0R–11R
CER
Address Lines
Chip Enable
CEL
OEL
OER
Output Enable
Read/Write Enable
R/WL
SEML
R/WR
SEMR
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The
(CY7C1342 only) (CY7C1342 only) three least significant bits of the address lines will determine which semaphore to write
or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested
by writing a 0 into the respective location.
Document #: 38-06038 Rev. *B
Page 2 of 12
CY7C135
CY7C1342
Maximum Ratings[1]
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................–65°C to+150°C
Latch-Up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied..............................................–55°C to+125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 48 to Pin 24)............................................–0.5V to+7.0V
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to+7.0V
DC Input Voltage[2]......................................... –3.0V to +7.0V
Electrical Characteristics Over the Operating Range[4]
7C135–15 7C135–20
7C1342–1 7C1342–2 7C135–25
5
0
7C1342–25
Max Min Max
Max Uni
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Test Conditions
Min.
.
.
.
Min.
.
t
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 4.0 mA
2.4
2.4
2.4
V
V
V
V
0.4
0.4
0.4
VIH
2.2
2.2
2.2
VIL
0.8
0.8
0.8
IIX
GND ≤ VI ≤ VCC
–10 +10 –10 +10 –10 +10 µA
–10 +10 –10 +10 –10 +10 µA
IOZ
Outputs Disabled,
GND ≤ VO ≤ VCC
ICC
Operating Current
VCC = Max.,
IOUT = 0 mA
Com’l
Ind.
220
60
190
50
180 mA
190
ISB1
ISB2
ISB3
Standby Current
(Both Ports TTL Levels)
CEL and CER ≥ VIH,
Com’l
Ind.
40
50
mA
[5]
f = fMAX
Standby Current
(One Port TTL Level)
CEL and CER ≥ VIH,
Com’l
Ind.
130
15
120
15
110 mA
120
[5]
f = fMAX
Standby Current
(Both Ports CMOS Levels)
Both Ports CE and CER ≥
VCC – 0.2V,
Com’l
15
mA
VIN ≥ VCC – 0.2V
Ind.
30
or VIN ≤ 0.2V, f = 0[5]
ISB4
Standby Current
(One Port CMOS Level)
One Port CEL or
CER ≥ VCC – 0.2V,
Com’l
Ind.
125
115
100 mA
115
VIN ≥VCC –0.2VorVIN ≤0.2V,
Active Port Outputs, f =
[5]
fMAX
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Pulse width < 20 ns.
3.
4. See the last page of this specification for Group A subgroup testing information.
5. = 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I .
SB3
T is the “instant on” case temperature.
A
f
MAX
RC
RC
Document #: 38-06038 Rev. *B
Page 3 of 12
CY7C135
CY7C1342
Electrical Characteristics Over the Operating Range[4](continued)
7C135–35
7C135–55
7C1342–35 7C1342–55
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
VCC = Min., IOH = –4.0 mA
Min. Max. Min. Max. Unit
VOH
VOL
VIH
VIL
2.4
2.4
V
V
VCC = Min., IOL = 4.0 mA
0.4
0.4
2.2
2.2
V
Input LOW Voltage
Input Load Current
Output Leakage Current
Operating Current
0.8
0.8
V
IIX
GND ≤ VI ≤ VCC
–10 +10 –10 +10
–10 +10 –10 +10
µA
µA
mA
IOZ
ICC
Outputs Disabled, GND ≤ VO ≤ VCC
VCC = Max., IOUT = 0 mA
VCC = Max., IOUT = 0 mA
Com’l
Ind.
160
180
30
160
180
30
[5]
ISB1
ISB2
ISB3
Standby Current
(Both Ports TTL Levels)
CEL and CER ≥ VIH, f = fMAX
Com’l
Ind.
mA
mA
mA
40
40
[5]
Standby Current
(One Port TTL Level)
CEL and CER ≥ VIH, f = fMAX
Com’l
Ind.
100
110
15
100
110
15
Standby Current
(Both Ports CMOS Levels) VIN ≥ VCC – 0.2V
Both Ports CE and CER ≥ VCC – 0.2V,
Com’l
Ind.
30
30
or VIN ≤ 0.2V, f = 0[5]
ISB4
Standby Current
(One Port CMOS Level)
One Port CEL or CER ≥ VCC – 0.2V,
Com’l
Ind.
90
90
mA
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V,
100
100
[5]
Active Port Outputs, f = fMAX
Capacitance[6]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
CIN
Input Capacitance
Output Capacitance
10
10
pF
pF
COUT
AC Test Loads and Waveforms
5V
R1= 893Ω
R
TH
= 250Ω
R
TH
= 250Ω
OUTPUT
OUTPUT
C= 30pF
OUTPUT
C= 30pF
C = 5 pF
R1= 347Ω
V
X
V
TH
= 1.4V
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 3)
1342–5
1342–6
1342–7
ALL INPUT PULSES
90%
3.0V
GND
90%
10%
10%
≤ 3 ns
1342–8
≤3 ns
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06038 Rev. *B
Page 4 of 12
CY7C135
CY7C1342
Switching Characteristics Over the Operating Range[7, 8]
7C135–15
7C135–20
7C135–25
7C135–35
7C135–55
7C1342–15 7C1342–20 7C1342–25 7C1342–35 7C1342–55
Parameter
Description
Read Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
15
3
20
3
25
3
35
3
55
3
ns
ns
ns
tAA
Address to Data Valid
15
20
25
35
55
tOHA
Output Hold From
Address Change
tACE
tDOE
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
15
10
20
13
25
15
35
20
55
25
ns
ns
ns
ns
ns
ns
ns
ns
[9,10,11]
tLZOE
3
3
0
3
3
0
3
3
0
3
3
0
3
3
0
[9,10,11]
tHZOE
OE HIGH to High Z
CE LOW to Low Z
10
10
15
13
13
20
15
15
25
20
20
35
25
25
55
[9,10,11]
tLZCE
[9,10,11]
tHZCE
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
[11]
tPU
[11]
tPD
WRITE CYCLE
tWC
tSCE
tAW
Write Cycle Time
15
12
12
2
20
15
15
2
25
20
20
2
35
30
30
2
55
50
50
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
Write Pulse Width
tHA
tSA
0
0
0
0
0
tPWE
tSD
12
10
0
15
13
0
20
15
0
25
15
0
50
25
0
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z
tHD
[10,11]
tHZWE
10
13
15
20
25
[10,11]
tLZWE
R/W HIGH to Low Z
3
3
3
3
3
[12]
tWDD
Write Pulse to Data Delay
30
25
40
30
50
30
60
35
70
40
[12]
tDDD
Write Data Valid to Read
Data Valid
SEMAPHORE TIMING[13]
tSOP
SEM Flag Update Pulse
(OE or SEM)
10
10
10
15
15
ns
tSWRD
SEM Flag Write to Read Time
SEM Flag Contention Window
5
5
5
5
5
5
5
5
5
5
ns
ns
tSPS
Notes:
7. See the last page of this specification for Group A subgroup testing information.
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
/I and 30-pF load capacitance.
I
OL OH
9. At any given temperature and voltage condition for any given device, t
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
10. Test conditions used are Load 3.
11. This parameter is guaranteed but not tested.
12. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
13. Semaphore timing applies only to CY7C1342.
Document #: 38-06038 Rev. *B
Page 5 of 12
CY7C135
CY7C1342
Switching Waveforms
Read Cycle No. 1[14,15]
Either Port Address Access
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1342–9
Read Cycle No. 2[14,16]
Either Port CE/OE Access
[13]
or CE
OE
SEM
t
HZCE
t
ACE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
ISB
1342–10
Read Timing with Port-to-Port[17]
t
wc
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
SD
HD
DATA
VALID
INR
ADDRESS
MATCH
L
t
DDD
DATA
VALID
OUTL
t
WDD
1342–11
Notes:
14. R/W is HIGH for read cycle.
15. Device is continuously selected, CE = V and OE = V .
IL
IL
16. Address valid prior to or coincident with CE transition LOW.
17. CE = CE =LOW; R/W = HIGH
L
R
L
Document #: 38-06038 Rev. *B
Page 6 of 12
CY7C135
CY7C1342
Switching Waveforms (continued)
Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[18,19,20]
t
WC
ADDRESS
[13]
t
SCE
SEM
OR CE
t
t
HA
AW
t
PWE
R/W
t
SA
t
t
HD
SD
DATA
IN
DATA VALID
OE
t
t
HZOE
LZOE
HIGH IMPEDANCE
DATA
OUT
1342–12
Write Cycle No. 2:R/W Three-States Data I/Os (Either Port)[19, 21]
t
WC
ADDRESS
t
t
HA
SCE
[13]
SEM
OR
CE
t
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATA VALID
DATA
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA
OUT
1342–13
Notes:
18. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
19. R/W must be HIGH during all address transactions.
20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data to be placed on the
PWE
HZWE SD
bus for the required t . If OE is HIGH during a R/Wcontrolled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified
SD
t
.
PWE
21. Data I/O pins enter high-impedance when OE is held LOW during write.
Document #: 38-06038 Rev. *B
Page 7 of 12
CY7C135
CY7C1342
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side (CY7C1342 only)[22]
t
AA
t
OHA
A –A
0
2
VALID ADDRESS
VALID ADDRESS
t
AW
t
ACE
t
SEM
HA
t
SCE
t
SOP
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
SA
t
PWE
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
1342–14
Timing Diagram of Semaphore Contention (CY7C1342 only)[23,24,25]
A
–A
0L 2L
MATCH
R/W
L
SEM
L
t
SPS
A
–A
MATCH
0R 2R
R/W
R
R
SEM
1342–15
Notes:
22. CE = HIGH for the duration of the above timing (both write and read cycle).
23. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
24. Semaphores are reset (available to both ports) at cycle start.
25. If t is violated, it is guaranteed that only one side will gain access to the semaphore.
SPS
Document #: 38-06038 Rev. *B
Page 8 of 12
CY7C135
CY7C1342
zero (the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the sema-
phore. Table 2 shows sample semaphore operations.
Architecture
The CY7C135 consists of an array of 4K words of 8 bits each
of dual-port RAM cells, I/O and address lines, and control sig-
nals (CE, OE, R/W). Two semaphore control pins exist for the
CY7C1342 (SEML/R).
When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both ports request a semaphore
control by writing a 0 to a semaphore within tSPS of each other,
it is guaranteed that only one side will gain access to the sema-
phore.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. Since there is no
on-chip arbitration, the user must be sure that a specific loca-
tion will not be accessed simultaneously by both ports or erro-
neous data could result. A write operation is controlled by ei-
ther the OE pin (see Write Cycle No. 1 timing diagram) or the
R/W pin (see Write Cycle No. 2 timing diagram). Data can be
written tHZOE after the OE is deasserted or tHZWE after the
falling edge of R/W. Required inputs for write operations are
summarized in Table 1.
Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All sema-
phores on both sides should have a one written into them at
initialization from both sides to assure that they will be free
when needed.
Table 1. Non-Contending Read/Write
If a location is being written to by one port and the opposite
port attempts to read the same location, a port-to-port
flowthrough delay is met before the data is valid on the output.
Data will be valid on the port wishing to read the location tDDD
after the data is presented on the writing port.
Inputs
Outputs
I/O0 – I/O7
High Z
Operation
Power-Down
CE R/W OE
SEM
H
H
X
H
X
L
H
L
Data Out
Read
Semaphore
Read Operation
X
H
L
X
L
H
X
L
X
L
High Z
I/O Lines Disabled
Write to Semaphore
Read
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE are asserted. If the user of the CY7C1342 wishes to ac-
cess a semaphore, the SEM pin must be asserted instead of
the CE pin. Required inputs for read operations are summa-
rized in Table 1.
Data In
Data Out
Data In
H
L
H
H
L
L
X
X
Write
L
X
Illegal Condition
Table 2. Semaphore Operation Example
Semaphore Operation
I/O0-7 I/O0-7
The CY7C1342 provides eight semaphore latches which are
separate from the dual port memory locations. Semaphores
are used to reserve resources which are shared between the
two ports. The state of the semaphore indicates that a re-
source is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a sema-
phore location. The left port then verifies its success in setting
the latch by reading it. After writing to the semaphore, SEM or
OE must be deasserted for tSOP before attempting to read the
Function
No Action
Left Right
Status
1
0
1
1
Semaphore free
Left port writes
semaphore
Left port obtains
semaphore
Right port writes 0 to
semaphore
0
1
1
0
Right side is denied
access
Left port writes 1 to
semaphore
Right port is granted
access to Sema-
phore
semaphore. The semaphore value will be available tSWRD
+
tDOE after the rising edge of the semaphore write. If the left port
was successful (reads a zero), it assumes control over the
shared resource, otherwise (reads a one) it assumes the right
port has control and continues to poll the semaphore. When
the right side has relinquished control of the semaphore (by
writing a one), the left side will succeed in gaining control of
the semaphore. If the left side no longer requires the sema-
phore, a one is written to cancel its request.
Left port writes 0 to
semaphore
1
0
1
1
1
0
1
0
1
1
0
1
1
1
No change. Left port
is denied access
Right port writes 1 to
semaphore
Left port obtains
semaphore
Left port writes 1 to
semaphore
No port accessing
semaphore address
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches. CE
must remain HIGH during SEM LOW. A0–2 represents the
semaphore address. OE and R/W are used in the same man-
ner as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
Right port writes 0 to
semaphore
Right port obtains
semaphore
Right port writes 1 to
semaphore
No port accessing
semaphore
Left port writes 0 to
semaphore
Left port obtains
semaphore
When writing to the semaphore, only I/O0 is used. If a 0 is
written to the left port of an unused semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing a
Left port writes 1 to
semaphore
No port accessing
semaphore
Document #: 38-06038 Rev. *B
Page 9 of 12
CY7C135
CY7C1342
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
140
120
100
80
1.4
1.2
1.0
I
SB
I
CC
1.2
1.0
I
SB3
0.8
0.6
0.4
0.8
0.6
0.4
V
CC
= 5.0V
V
V
= 5.0V
= 5.0V
CC
60
T = 25°C
A
IN
40
0.2
0.6
0.2
20
0
I
CC
0.0
4.0
4.5
5.0
5.5
6.0
–55
25
125
0
1.0
2.0
3.0
4.0 5.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.1
100
90
1.10
1.05
T = 25°C
A
80
70
1.0
0.9
V
CC
= 5.0V
1.00
0.95
V
= 5.0V
CC
60
50
T = 25°C
A
0.8
–55
0.0
1.0
2.0
3.0
4.0 5.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I
vs.CYCLE TIME
CC
1.25
20.0
1.0
V
CC
= 5.0V
T = 25°C
A
V
IN
= 0.5V
15.0
10.0
0.75
0.50
1.0
0.75
V
= 4.5V
CC
5.0
0
0.25
0.0
T = 25°C
A
0.50
10
20
30
40
50
0
200 400 600 800 1000
CAPACITANCE (pF)
0
1.0
2.0
3.0
4.0 5.0
CYCLE FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
Document #: 38-06038 Rev. *B
Page 10 of 12
CY7C135
CY7C1342
Ordering Information
4K x8 Dual-Port SRAM
Speed
(ns)
15
Package
Name
Operating
Range
Ordering Code
Package Type
CY7C135–15JC
CY7C135–20JC
CY7C135–25JC
CY7C135–25JI
CY7C135–35JC
CY7C135–35JI
CY7C135–55JC
CY7C135–55JI
J69
J69
J69
J69
J69
J69
J69
J69
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Commercial
Industrial
20
25
35
55
Commercial
Industrial
Commercial
Industrial
4K x8 Dual-Port SRAM with Semaphores
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
Package Type
15
CY7C1342–15JC
J69
J69
J69
J69
J69
J69
J69
J69
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Commercial
Industrial
20
CY7C1342–20JC
CY7C1342–25JC
CY7C1342–25JI
CY7C1342–35JC
CY7C1342–35JI
CY7C1342–55JC
CY7C1342–55JI
25
35
55
Commercial
Industrial
Commercial
Industrial
Package Diagrams
52-Lead Plastic Leaded Chip Carrier J69
51-85004-*A
Document #: 38-06038 Rev. *B
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C135
CY7C1342
Document History Page
Document Title: CY7C135/CY7C1342 4K x 8 Dual Port Static RAM and 4K x 8 Dual Port Static RAM w/Semaphores
Document Number: 38-06038
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
110181
122288
236763
10/21/01
SZV
RBI
Change from Spec number: 38-00541 to 38-06038
Power up requirements added to Maximum Ratings Information
Removed cross information from features section
*A
*B
12/27/02
SEE ECN
YDT
Document #: 38-06038 Rev. *B
Page 12 of 12
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