CY7C1354B-200BZI [CYPRESS]
9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture; 9 -MB （ 256K ×36 / 512K ×18 ）流水线SRAM与NOBL架构
| 型号： | CY7C1354B-200BZI |
| 厂家： | 
CYPRESS |
| 描述： | 9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture |
| 文件： | 总29页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1354B
CY7C1356B
9-Mb (256K x 36/512K x 18) Pipelined SRAM
with NoBL™ Architecture
Features
Functional Description
• Pin-compatible and functionally equivalent to ZBT
• Supports 225-MHz bus operations with zero wait states
— Available speed grades are 225, 200, and 166 MHz
The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and
512K x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1354B and CY7C1356B are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1354B and CY7C1356B are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1354B and BWa–BWb for CY7C1356B)
and a Write Enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined op-
eration
• Byte Write capability
• Separate VDDQ for 3.3V or 2.5V I/O
• Single 3.3V power supply
• Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.2ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA packag-
es
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability–linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram-CY7C1354B (256K x 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
BW
BW
a
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05114 Rev. *C
Revised June 16, 2004
CY7C1354B
CY7C1356B
Logic Block Diagram-CY7C1356B (512K x 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
MEMORY
ARRAY
E
B
U
F
DQs
DQP
DQP
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
a
F
b
S
T
E
R
S
b
E
R
S
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Selection Guide
CY7C1354B-225
CY7C1356B-225
2.8
CY7C1354B-200
CY7C1356B-200
3.2
CY7C1354B-166
CY7C1356B-166
3.5
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information.
250
35
220
35
180
35
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05114 Rev. *C
Page 2 of 29
CY7C1354B
CY7C1356B
Pin Configurations
100-pin TQFP Packages
DQPc
DQc
1
NC
NC
NC
DDQ
1
A
DQPb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
2
2
NC
79
DQc
3
DQb
3
NC
78
V
V
4
DDQ
4
VDDQ
V
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
5
VSS
V
5
SS
SS
DQc
6
NC
6
NC
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQc
7
NC
7
DQPa
DQa
DQa
DQc
DQc
8
DQb
DQb
8
9
9
V
V
SS
DDQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
V
V
V
DDQ
DDQ
DQc
DQc
NC
DQb
DQb
NC
DQa
DQa
V
CY7C1354B
(256K × 36)
SS
V
V
DD
DD
NC
CY7C1356B
(512K × 18)
NC
VDD
ZZ
DQa
DQa
NC
V
DD
V
V
SS
SS
ZZ
DQd
DQd
DQb
DQb
DDQ
DQa
DQa
V
V
DDQ
VDDQ
V
DDQ
V
V
SS
VSS
SS
V
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQb
DQb
DQa
DQa
NC
DQa DQPb
DQa
VSS
NC
NC
V
SS
V
V
DDQ
SS
SS
V
V
DDQ
DQd
DDQ
VDDQ
V
DQa
NC
NC
NC
NC
NC
NC
DQd
DQa
DQPd
DQPa
Document #: 38-05114 Rev. *C
Page 3 of 29
CY7C1354B
CY7C1356B
Pin Configurations (continued)
119-ball BGA Pinout
CY7C1354B (256K × 36) – 14 × 22 BGA
1
VDDQ
2
A
3
A
4
E(18)
5
A
6
A
7
VDDQ
A
NC
NC
DQc
DQc
VDDQ
DQc
CE2
A
DQPc
A
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
BWd
VSS
VSS
VSS
MODE
A
ADV/LD
VDD
NC
A
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
CE3
A
DQPb
NC
NC
DQb
B
C
D
E
F
G
H
J
K
L
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
CE1
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
OE
A
WE
VDD
CLK
NC
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
NC
VDDQ
M
N
P
CEN
A1
A0
VDD
A
TCK
A
E(72)
TMS
A
E(36)
NC
NC
ZZ
VDDQ
R
NC
A
TDO
T
TDI
U
CY7C1356B (512K x 18)–14 x 22 BGA
1
2
3
4
5
6
7
VDDQ
A
A
E(18)
A
A
VDDQ
A
B
C
D
E
F
G
H
J
NC
NC
DQb
NC
VDDQ
NC
DQb
VDDQ
NC
DQb
VDDQ
DQb
NC
CE2
A
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
A
A
VSS
VSS
VSS
A
A
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
CE3
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
ADV/LD
VDD
NC
VSS
VSS
VSS
VSS
VSS
NC
CE1
OE
A
BWb
VSS
NC
WE
VDD
VSS
VSS
VSS
VSS
VSS
MODE
A
CLK
NC
VSS
K
L
BWa
VSS
VSS
VSS
NC
A
M
N
P
R
T
CEN
A1
A0
VDD
E(36)
TCK
DQa
NC
ZZ
VDDQ
NC
E(72)
VDDQ
A
TMS
A
NC
TDI
TDO
U
Document #: 38-05114 Rev. *C
Page 4 of 29
CY7C1354B
CY7C1356B
Pin Configurations (continued)
165-Ball fBGA Pinout
CY7C1354B (256K × 36) – 13 × 15 fBGA
1
2
3
4
5
6
7
CEN
WE
VSS
VSS
8
9
10
11
NC
E(144)
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
E(288)
NC
A
ADV/LD
A
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
CE1
BWc
BWd
VSS
VDD
BWb
BWa
VSS
VSS
CE3
CLK
VSS
VSS
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
E(18)
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
NC
DQc
A
NC
DQb
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
E(72)
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC
A1
VSS
NC
TDO
VDD
VSS
A
DQa
DQPa
NC
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1356B (512K × 18) – 13 × 15 fBGA
1
E(288)
NC
NC
NC
NC
NC
NC
2
3
4
BWb
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
5
6
7
CEN
8
9
10
11
A
E(144)
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
A
CE3
A
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
CE1
NC
ADV/LD
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E(18)
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A
NC
DQb
DQb
DQb
DQb
NC
NC
NC
A
NC
NC
NC
NC
NC
NC
NC
NC
VDDQ
DQb
DQb
DQb
DQb
DQPb
NC
DQa
DQa
DQa
DQa
NC
A
VDDQ
VDDQ
VDDQ
VDDQ
A
NC
NC
NC
VSS
NC
TDI
VSS
NC
A1
VSS
NC
TDO
VDD
VSS
A
E(72)
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05114 Rev. *C
Page 5 of 29
CY7C1354B
CY7C1356B
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Address Inputs used to select one of the address locations. Sampled at the rising edge of
Synchronous
the CLK.
BWa
BWb
BWc
BWd
Input-
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sam-
pled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc
controls DQc and DQPc, BWd controls DQd and DQPd.
Synchronous
Input-
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
WE
Synchronous
signal must be asserted LOW to initiate a write sequence.
Input-
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
ADV/LD
Synchronous
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1
CE2
Synchronous
CE2 and CE3 to select/deselect the device.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous
CE1 and CE3 to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE3
OE
Synchronous
CE1 and CE2 to select/deselect the device.
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a Write sequence, during the first clock when emerging from a dese-
lected state and when the device has been deselected.
Input-
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
CEN
Synchronous
DQa
DQb
DQc
DQd
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by addresses during the previous clock rise of the Read cycle. The direction of the pins
is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are auto-
matically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE.
Synchronous
DQPa
DQPb
DQPc
DQPd
I/O-
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[a:d]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled
by BWc, and DQPd is controlled by BWd.
Synchronous
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
TDI
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
VDD
VDDQ
VSS
JTAG-Clock
Clock input to the JTAG circuitry.
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
Ground for the device. Should be connected to ground of the system.
Document #: 38-05114 Rev. *C
Page 6 of 29
CY7C1354B
CY7C1356B
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
NC
–
–
No connects. This pin is not connected to the die.
E(18,36,
72, 144,
288)
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
and 288M densities.
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin can be connected to VSS or left
floating.
of the chip enable signals, its output will three-state following
Introduction
Functional Overview
the next clock rise.
Burst Read Accesses
The CY7C1354B and CY7C1356B are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the Clock Enable
input signal (CEN). If CEN is HIGH, the clock signal is not
recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.8 ns (225-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BW[d:a] can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
Writes are simplified with on-chip synchronous self-timed
Write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
The CY7C1354B and CY7C1356B have an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to A0∠A16 is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,b for
CY7C1356B). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the address
register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
(DQa,b,c,d/DQPa,b,c,d for CY7C1354B and DQa,b/DQaPnad,bDfQoPr
CY7C1356B) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the Write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d for CY7C1354B and BWa,b for CY7C1356B)
signals. The CY7C1354B/56B provides Byte Write capability
that is described in the Write Cycle Description table. Asserting
the Write Enable input (WE) with the selected Byte Write
Select (BW) input will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.8 ns
(225-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
Document #: 38-05114 Rev. *C
Page 7 of 29
CY7C1354B
CY7C1356B
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Because the CY7C1354B and CY7C1356B are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
HIGH before presenting data to the DQ
and
(DQa,b,c,d/DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,bDfQoPr
Interleaved Burst Address Table
CY7C1356B) inputs. Doing so will three-state the output
(MODE = Floating or VDD
)
drivers. As a safety precaution, DQ
(DQa,b,c,d/
and DQP
DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,b for
CY7C1356B) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
First
Second
Third
Fourth
Address
Address
Address
Address
A1,A0
A1,A0
A1,A0
A1,A0
Burst Write Accesses
00
01
10
11
01
00
11
10
The CY7C1354B/56B has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct BW
(BWa,b,c,d for CY7C1354B and BWa,b for CY7C1356B) inputs
must be driven in each cycle of the burst write in order to write
the correct bytes of data.
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Second
Third
Fourth
Address
Address
Address
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
10
11
00
Sleep Mode
10
11
00
01
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max
35
2tCYC
Unit
mA
ns
ns
ns
ns
tZZS
tZZREC
tZZI
tRZZI
2tCYC
0
2tCYC
Document #: 38-05114 Rev. *C
Page 8 of 29
CY7C1354B
CY7C1356B
Truth Table[1, 2, 3, 4, 5, 6, 7]
Address
Operation
Used
CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect Cycle None
H
L
L
X
X
X
L
L-H
Three-State
Continue
None
X
L
H
X
X
X
L
L-H
Three-State
Data Out (Q)
Data Out (Q)
Three-State
Deselect Cycle
Read Cycle
External
Next
L
X
L
L
L
L
L
H
L
H
X
H
X
X
X
L
L
L
L
L
L-H
L-H
L-H
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy
External
H
Read
(Begin Burst)
Dummy Read
Next
X
L
L
L
L
L
H
L
X
L
X
L
H
X
X
X
L
L
L
L
L-H
L-H
L-H
L-H
Three-State
Data In (D)
Data In (D)
Three-State
(Continue Burst)
Write Cycle
External
Next
(Begin Burst)
Write Cycle
X
L
H
L
X
L
L
(Continue Burst)
NOP/WRITE
None
H
ABORT
(Begin Burst)
WRITE ABORT Next
X
X
L
L
H
X
X
X
H
X
X
X
L
L-H
L-H
Three-State
-
(Continue Burst)
IGNORE
Current
H
CLOCK EDGE
(Stall)
Sleep MODE
None
X
H
X
X
X
X
X
X
Three-State
Notes:
1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx =
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW
. See Write Cycle Description table for details.
[a:d]
3. When a write cycle is detected, all I/Os are three-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
OE is inactive or when the device is deselected, and DQs = data when OE is active.
= Three-state when
[a:d]
Document #: 38-05114 Rev. *C
Page 9 of 29
CY7C1354B
CY7C1356B
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1354B)
BWd
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
BWc
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
BWb
BWa
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Read
X
H
H
L
Write –No bytes written
Write Byte a– (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
Write Byte c – (DQc and DQPc)
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d – (DQd and DQPd)
Write Bytes d, a
Write Bytes d, b
L
H
H
L
L
H
H
L
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
L
H
H
L
Write All Bytes
L
L
Note:
8. Table only lists a partial listing of the byte write combinations. Any combination of BW
is valid. Appropriate write will be done based on which byte write is active.
[a:d]
Function (CY7C1356B)
Read
Write – No Bytes Written
Write Byte a − (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
WE
H
L
L
L
BWb
BWa
x
H
L
H
x
H
H
L
L
L
L
Test Access Port–Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354B/CY7C1354B incorporates a serial boundary
scan Test Access Port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This port
operates in accordance with IEEE Standard 1149.1-1900, but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 3.3V I/O logic levels.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Document #: 38-05114 Rev. *C
Page 10 of 29
CY7C1354B
CY7C1356B
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data, or control signals into
the SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
EXTEST
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The ×36 configuration has a 69-bit-long
register, and the ×18 configuration has a 69-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
Document #: 38-05114 Rev. *C
Page 11 of 29
CY7C1354B
CY7C1356B
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05114 Rev. *C
Page 12 of 29
CY7C1354B
CY7C1356B
TAP Controller State Diagram
TEST-LOGIC
RESET
1
1
1
1
TEST-LOGIC/
IDLE
SELECT
SELECT
0
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05114 Rev. *C
Page 13 of 29
CY7C1354B
CY7C1356B
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
1
1
0
TDO
Instruction Register
TDI
29
Identification Register
31 30
.
.
2
0
0
.
68 .
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[10, 11]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = 2.0 mA, VDDQ = 3.3V
OH = 2.0 mA, VDDQ = 2.5V
IOH = 100 µA, VDDQ = 3.3V
IOH = 100 µA, VDDQ = 2.5V
IOL = 2.0 mA
Min.
2.0
1.7
2.0
2.0
Max.
Unit
V
V
V
V
V
V
V
V
I
VOH2
Output HIGH Voltage
VOL1
VOL2
VIH
VIL
IX
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
0.7
0.2
VDD + 0.3
0.7
IOL = 100 µA
1.7
–0.3
–30
–30
GND ≤ VI ≤ VDDQ
30
30
µA
µA
IX
Input Load Current TMS and TDI GND ≤ VI ≤ VDDQ
[12, 13]
TAP AC Switching Characteristics Over the Operating Range
Parameter
Description
Min.
Max.
Unit
tTCYC
tTF
tTH
tTL
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
ns
MHz
ns
10
40
40
TCK Clock LOW
ns
Set-up Times
tTMSS
tTDIS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tCS
Notes:
10. All voltage referenced to ground.
11. Overshoot: V (AC) < V + 1.5V for t < t
/2; undershoot: V (AC) > –0.5V for t < t
/2.
TCYC
IH
DD
TCYC
IL
12. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
13. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document #: 38-05114 Rev. *C
Page 14 of 29
CY7C1354B
CY7C1356B
TAP AC Switching Characteristics Over the Operating Range (continued)[12, 13]
Parameter
Hold Times
tTMSH
tTDIH
tCH
Description
Min.
Max.
Unit
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after clock rise
10
10
10
ns
ns
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
20
ns
ns
0
TAP Timing and Test Conditions
1.5V for 3.3V VDDQ
1.25V for 2.5V VDDQ
ALL INPUT PULSES
1.5V
3.0V
1.5 ns
50Ω
VSS
1.5 ns
TDO
Z = 50Ω
0
C = 20 pF
L
tTL
tTH
(a)
GND
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
CY7C1354B
CY7C1356B
Description
Reserved for version number.
001
001
01010001000100110 01010001000010110 Reserved for future use.
00000110100
1
00000110100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Document #: 38-05114 Rev. *C
Page 15 of 29
CY7C1354B
CY7C1356B
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
69
Boundary Scan
Identification Codes
Instruction
Code
Description
EXTEST
000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
SAMPLE Z
010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scanregister between TDI and TDO.
Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1-compliant.
RESERVED
RESERVED
BYPASS
101 Do Not Use: This instruction is reserved for future use.
110
111
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Exit Order (×36) (continued)
Boundary Scan Exit Order (×36)
Bit #
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
119-Ball ID
M6
L7
165-Ball ID
K11
L11
M11
N11
R11
R10
P10
R9
Bit #
1
2
3
4
5
6
7
119-Ball ID
165-Ball ID
B6
K4
H4
M4
F4
B4
G4
C3
B3
D6
H7
G6
E6
D7
E7
F6
G7
H6
T7
K7
L6
B7
A7
B8
A8
K6
P6
T4
A3
C5
B5
A5
C6
A6
P4
A9
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
8
9
P9
R8
P8
R6
P6
R4
P4
R3
P3
R1
N1
L2
K2
J2
M2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
N4
R6
T5
T3
R2
R3
P2
P1
L2
N6
P7
N7
K1
N2
Document #: 38-05114 Rev. *C
Page 16 of 29
CY7C1354B
CY7C1356B
Boundary Scan Exit Order (×36) (continued)
Boundary Scan Exit Order (×18) (continued)
Bit #
119-Ball ID
165-Ball ID
Bit #
119-Ball ID
165-Ball ID
47
48
49
50
N1
M2
L1
M1
L1
K1
J1
16
17
18
19
20
21
22
23
G7
H6
T7
K7
L6
F11
G11
H11
J10
K10
L10
M10
K2
51
Not Bonded
Not Bonded
(Preset to 1)
(Preset to 1)
N6
P7
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
H1
G2
E2
D1
H2
G1
F2
E1
D2
C2
A2
E4
B2
L3
G2
F2
E2
D2
G1
F1
E1
D1
C1
B2
A2
A3
B3
B4
A4
A5
B5
A6
Not Bonded
Not Bonded
(Preset to 0)
(Preset to 0)
24
25
26
27
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
Not Bonded
(Preset to 0)
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
Not Bonded
(Preset to 0)
(Preset to 0)
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
T6
A3
C5
B5
A5
C6
A6
P4
N4
R6
T5
T3
R2
R3
R11
R10
P10
R9
P9
R8
P8
R6
P6
R4
P4
R3
P3
G3
G5
L5
B6
Boundary Scan Exit Order (×18)
Bit #
1
2
3
4
5
6
7
119-Ball ID
165-Ball ID
B6
K4
H4
M4
F4
B4
G4
C3
B3
T2
B7
A7
B8
A8
R1
Not Bonded
Not Bonded
(Preset to 0)
(Preset to 0)
43
44
45
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
A9
B10
A10
A11
Not Bonded
Not Bonded
8
9
10
(Preset to 0)
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
Not Bonded
(Preset to 0)
(Preset to 0)
46
47
48
49
50
51
P2
N1
M2
L1
N1
M1
L1
K1
J1
11
12
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
Not Bonded
(Preset to 0)
(Preset to 0)
K2
13
14
15
D6
E7
F6
C11
D11
E11
Not Bonded
Not Bonded
(Preset to 1)
(Preset to 1)
52
H1
G2
Document #: 38-05114 Rev. *C
Page 17 of 29
CY7C1354B
CY7C1356B
Boundary Scan Exit Order (×18) (continued)
Bit #
119-Ball ID
165-Ball ID
53
54
55
G2
E2
D1
F2
E2
D2
56
Not Bonded
Not Bonded
(Preset to 0)
(Preset to 0)
57
58
59
60
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
Not Bonded
(Preset to 0)
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
Not Bonded
(Preset to 0)
(Preset to 0)
61
62
63
64
65
C2
A2
E4
B2
B2
A2
A3
B3
Not Bonded
Not Bonded
(Preset to 0
(Preset to 0)
66
67
G3
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0
A4
68
69
L5
B6
B5
A6
Document #: 38-05114 Rev. *C
Page 18 of 29
CY7C1354B
CY7C1356B
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC to Outputs in Three-State.............. –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Range
Temperature
VDD
VDDQ
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
to VDD
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range[14, 15]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
VDD
Unit
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
VDDQ
VOH
VOL
VIH
VIL
VDDQ = 3.3V
DDQ = 2.5V
VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V
DD = Min., IOH = −1.0 mA, VDDQ = 2.5V
VDD = Min., IOL= 8.0 mA, VDDQ = 3.3V
DD = Min., IOL= 1.0 mA, VDDQ = 2.5V
V
2.625
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V
2.0
0.4
0.4
VDD + 0.3V
VDD + 0.3V
V
VDDQ = 3.3V
VDDQ = 2.5V
2.0
1.7
–0.3
–0.3
–5
Input LOW Voltage[14] VDDQ = 3.3V
0.8
0.7
5
30
5
250
220
180
50
VDDQ = 2.5V
IX
Input Load Current
Input Current of MODE
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA,
GND ≤ VI ≤ VDDQ
–30
–5
IOZ
IDD
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
ISB4
Automatic CE
Max. VDD, Device Deselected, All speed grades
IN ≥ VIH or VIN ≤ VIL, f = fMAX
1/tCYC
Power-down
V
=
Current—TTL Inputs
Automatic CE
Max. VDD, Device Deselected, All speed grades
35
50
40
mA
mA
mA
Power-down
V
IN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = 0
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
V
IN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = fMAX = 1/tCYC
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
CYC
IL
CYC
15. T
: Assumes a linear ramp from 0V to V
(min.) within 200 ms. During this time V < V and V
< V
.
DD
Power-up
IH
DD
DDQ
DD
Document #: 38-05114 Rev. *C
Page 19 of 29
CY7C1354B
CY7C1356B
Capacitance[16]
Parameter
CIN
CCLK
CI/O
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
BGA Max.
fBGA Max.
TQFP Max.
Unit
pF
pF
TA = 25°C, f = 1 MHz,
5
5
7
5
5
7
5
5
5
V
DD = 3.3V VDDQ = 2.5V
pF
AC Test Loads and Waveforms
R=1667/317Ω
VDDQ
DQ
[16]
OUTPUT
ALL INPUT PULSES
VDD
0V
90%
10%
90%
10%
Z = 50Ω
0
1.5/1.25V
R = 50Ω
L
5 pF
R = 1538/351Ω
< 1.0 ns
< 1.0 ns
V = 1.5V/1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Thermal Resistance[16]
Parameters
Description
Test Conditions
BGA Typ. fBGA Typ. TQFP Typ.
Unit Notes
ΘJA
Thermal Resistance
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per EIA
/ JESD51.
25
27
25
°C/W
17
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
6
6
9
°C/W
17
Switching Characteristics Over the Operating Range [21, 22]
-225
-200
-166
Max.
Parameter
tPower
Description
VCC (typical) to the First Access Read or
Min.
1
Max.
Min.
Max.
Min.
Unit
ms
[17]
1
1
Write
Clock
tCYC
FMAX
tCH
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
4.4
5
6
ns
MHz
ns
225
200
166
1.8
1.8
2.0
2.0
2.4
2.4
tCL
Clock LOW
ns
Output Times
tCO
tEOV
tDOH
tCHZ
tCLZ
tEOHZ
tEOLZ
Data Output Valid after CLK Rise
OE LOW to Output Valid
2.8
2.8
3.2
3.2
3.5
3.5
ns
ns
ns
ns
ns
ns
ns
Data Output Hold after CLK Rise
1.25
1.25
1.25
1.5
1.5
1.5
1.5
1.5
1.5
Clock to High-Z[18, 19, 20]
2.8
2.8
3.2
3.2
3.5
3.5
Clock to Low-Z[18, 19, 20]
HIGH to Output High-Z[18, 19, 20]
OE
OE LOW to Output Low-Z[18, 19, 20]
0
0
0
Shaded areas contain advance information.
Notes:
16. Tested initially and after any design or process changes that may affect these parameters.
17. This part has a voltage regulator internally; t
initiated.
is the time power needs to be supplied above V minimum initially, before a Read or Write operation can be
DD
power
18. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ EOLZ
EOHZ
19. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
EOHZ
EOLZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
21. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05114 Rev. *C
Page 20 of 29
CY7C1354B
CY7C1356B
Switching Characteristics Over the Operating Range (continued)[21, 22]
-225
-200
Max.
-166
Parameter
Set-up Times
tAS
tDS
tCENS
tWES
tALS
tCES
tAH
Description
Min.
Max.
Min.
Min.
Max.
Unit
Address Set-up before CLK Rise
Data Input Set-up before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
0.4
1.5
1.5
1.5
1.5
1.5
1.5
0.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
ns
ns
ns
ns
ns
ns
ns
CEN Set-up before CLK Rise
WE, BWx Set-up before CLK Rise
ADV/LD Set-up before CLK Rise
Chip Select Set-up
Address Hold after CLK Rise
Hold Times
tDH
tCENH
tWEH
tALH
tCEH
Data Input Hold after CLK Rise
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
CEN Hold after CLK Rise
WE, BWx Hold after CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold after CLK Rise
Document #: 38-05114 Rev. *C
Page 21 of 29
CY7C1354B
CY7C1356B
Switching Waveforms
Read/WriteTiming[23,24,25]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
X
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6
-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Document #: 38-05114 Rev. *C
Page 22 of 29
CY7C1354B
CY7C1356B
Switching Waveforms (continued)
[23,24,26]
NOP,STALL AND DESELECT CYCLES
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW
X
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Document #: 38-05114 Rev. *C
Page 23 of 29
CY7C1354B
CY7C1356B
Switching Waveforms (continued)
[27,28]
ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Note:
23. For this waveform ZZ is tied low.
24. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.
26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
28. I/Os are in High-Z when exiting ZZ sleep mode..
Ordering Information
Speed
Package
Name
A101
Operating
Range
Commercial
(MHz)
Ordering Code
CY7C1354B-225AC
CY7C1356B-225AC
CY7C1354B-225AI
CY7C1356B-225AI
CY7C1354B-225BGC
CY7C1356B-225BGC
CY7C1354B-225BGI
CY7C1356B-225BGI
CY7C1354B-225BZC
CY7C1356B-225BZC
CY7C1354B-225BZI
CY7C1356B-225BZI
Package Type
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
225
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Industrial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
Industrial
BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Commercial
BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Industrial
Document #: 38-05114 Rev. *C
Page 24 of 29
CY7C1354B
CY7C1356B
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Package Type
200
CY7C1354B-200AC
CY7C1356B-200AC
CY7C1354B-200AI
CY7C1356B-200AI
CY7C1354B-200BGC
CY7C1356B-200BGC
CY7C1354B-200BGI
CY7C1356B-200BGI
CY7C1354B-200BZC
CY7C1356B-200BZC
CY7C1354B-200BZI
CY7C1356B-200BZI
CY7C1354B-166AC
CY7C1356B-166AC
CY7C1354B-166AI
CY7C1356B-166AI
CY7C1354B-166BGC
CY7C1356B-166BGC
CY7C1354B-166BGI
CY7C1356B-166BGI
CY7C1354B-166BZC
CY7C1356B-166BZC
CY7C1354B-166BZI
CY7C1356B-166BZI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Commercial
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
Industrial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
Industrial
BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Commercial
BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Industrial
Commercial
Industrial
166
A101
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
Industrial
BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Commercial
BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Industrial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05114 Rev. *C
Page 25 of 29
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1354B
CY7C1356B
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
SEE DETAIL
A
(ꢀX)
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
51-85050-*A
DETAIL
A
Document #: 38-05114 Rev. *C
Page 26 of 29
CY7C1354B
CY7C1356B
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4mm) BG119
51-85115-*B
Document #: 38-05114 Rev. *C
Page 27 of 29
CY7C1354B
CY7C1356B
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05114 Rev. *C
Page 28 of 29
CY7C1354B
CY7C1356B
Document History Page
Document Title: CY7C1354B/CY7C1356B 9-Mb (256K x 36/512K x 18) Pipelined SRAM
NoBL™ Architecture
with
Document Number: 38-05114
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
117904
08/28/02
RCS
New Data Sheet
*A
126207
08/27/03
DPM
Removed Preliminary status
Removed 250-MHz Speed bin
Added 225-MHz speed bin
Increased TCO, TEOV, TCHZ, TEOHZ for 200 MHz to 3.2 ns from 3.0 ns
Updated JTAG revision number and device depth
Updated JTAG boundary scan orders
Added tPower specification
Changed footnotes ordering
Added Industrial operating range
Changed Capacitance table to have TQFP, BGA, and fBGA columns.
*B
205060
See ECN
NJY
Removed footnote 13 “Minimum voltage equals –2.0V for pulse durations of less than 20 ns.”
Removed footnote 14 “TA is the case temperature.”
Changed footnote 15 from “Overshoot: V (AC) < V + 1.5V for t < t
/2; undershoot:
IH
DD
TCYC
V
(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t <
IL
200 ms. “to footnote 13“Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2),
undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). “
Added footnote 14 “T
: Assumes a linear ramp from 0V to VDD (min.) within 200ms.
Power-up
During this time VIH < VDD and VDDQ < VDD. “
Added footnote 20 “Timing reference level is 1.5V when V
= 3.3V and is 1.25V when
DDQ
V
= 2.5V.”
DDQ
Changed footnote 21 from “Test conditions shown in (a), (b) and (c) of AC Test Loads. “to
“Test conditions shown in (a) of AC Test Loads unless otherwise noted. “
Updated ZZ Mode Electrical Characteristics.
Updated ISB1 and ISB3 currents in Electrical Characteristics table.
Modified functional block diagram.
Modified Truth Table and Write Cycle Descriptions.
Updated Ordering Information.
*C
230388
See ECN
VBL
Modified ID code
Changed balls B4 and A5 from BWd and BWb to NC and ball A4 from BWc
to BWb for 165-ball FBGA package for CY7C1356B
Changed balls C11 from DQPb to DQPa and balls D11,E11,F11 and G11
from DQb to DQa for CY7C1356B.
Update Ordering Info section: changed BZC to BZI in Industrial part
Document #: 38-05114 Rev. *C
Page 29 of 29
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明