CY7C1360 [CYPRESS]
9-Mbit (256K x 36/512K x 18) Pipelined SRAM; 9兆位（ 256K ×36 / 512K ×18 ）流水线式SRAM
| 型号： | CY7C1360 |
| 厂家： | 
CYPRESS |
| 描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 文件： | 总34页 (文件大小：859K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1360B
CY7C1362B
9-Mbit(256Kx36/512Kx18)PipelinedSRAM
Features
Functional Description[1]
• Supports bus operation up to 225 MHz
• Available speed grades are 225, 200 and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
The CY7C1360B/CY7C1362B SRAM integrates 262,144 x 36
and 524,288 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (
), depth-expansion Chip
CE1
[2]
Enables (CE and
), Burst Control inputs (
,
,
CE3
2
ADSC ADSP
), Write Enables (
ADV
, and
BWX
), and Global Write
and
BWE
(
). Asynchronous inputs include the Output Enable (
)
OE
GW
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor ( ) or
• Provide high-performance 3-1-1-1 access rate
ADSP
) are active. Subsequent
Address Strobe Controller (
ADSC
burst addresses can be internally generated as controlled by
the Advance pin ( ).
• User-selectable burst counter supporting Intel
Pentium® interleaved or linear burst sequences
ADV
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
• Single Cycle Chip Deselect
controlled by the Byte Write control inputs.
when active
GW
causes all bytes to be written.
LOW
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-Ball fBGA packages
The CY7C1360B/CY7C1362B operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
Selection Guide
225 MHz
200 MHz
3.0
166 MHz
3.5
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.8
250
30
220
30
180
30
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE is for A version of TQFP (3 Chip Enable option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.
3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05291 Rev. *C
Revised April 9, 2004
CY7C1360B
CY7C1362B
1
Logic Block DiagrC1360B (256K x 36)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D ,DQPD
DQ
BYTE
WRITE DRIVER
D ,DQPD
BW
D
DQC ,DQP
BYTE
WRITE DRIVER
C
DQC ,DQP
BYTE
WRITE REGISTER
C
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
MEMORY
ARRAY
DQ s
SENSE
AMPS
DQPA
DQB ,DQP
BYTE
WRITE DRIVER
B
E
DQB ,DQP
BYTE
WRITE REGISTER
B
DQP
DQP
B
C
BW
BW
B
A
DQPD
DQ
BYTE
WRITE DRIVER
A ,DQPA
DQ
A ,DQPA
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
2
Logic Block Diagram – CY7C1362B (512K x 18)
ADDRESS
A0, A1, A
REGISTER
A[1:0]
2
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB,DQP
B
DQB,DQP
WRITE REGISTER
B
WRITE DRIVER
OUTPUT
BUFFERS
BW
B
A
DQs
DQP
DQP
OUTPUT
REGISTERS
SENSE
AMPS
MEMORY
ARRAY
A
B
DQA,DQP
A
E
DQA,DQP
WRITE REGISTER
A
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE1
CE2
PIPELINED
ENABLE
CE3
OE
ZZ
SLEEP
CONTROL
Document #: 38-05291 Rev. *C
Page 2 of 34
CY7C1360B
CY7C1362B
Pin Configurations
100-pin TQFP Pinout (3 Chip Enables) (A version)
DQPC
1
DQP
B
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
DQB
B
2
NC
2
DQc
VDDQ
VSSQ
DQ
3
NC
NC
3
VDDQ
4
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
VSSQ
5
5
DQ
DQ
DQ
C
DQ
DQ
DQ
DQ
B
B
B
B
6
6
C
C
7
NC
DQP
A
7
8
DQ
B
B
DQ
A
A
8
DQ
C
9
DQ
DQ
9
VSSQ
VDDQ
VSSQ
VDDBQ
DQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSSQ
VSSQ
VDDAQ
DQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQ
C
DQ
B
B
DQ
C
DQ
B
DQ
DQ
A
NC
VDD
NC
VSS
NC
VDD
ZZ
NC
VDD
NC
VSS
NC
VDD
ZZ
CY7C1362B
(512K x 18)
CY7C1360B
(256K X 36)
VSDS
VSBS
DQ
DQ
A
DQ
DQ
A
A
DQ
D
DQA
DQ
B
DQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
DQ
D
DQ
DQ
DQ
DQ
A
A
A
A
DQ
B
B
B
DQ
DQ
NC
NC
A
A
DQ
D
DQ
DQ
D
DQP
DQ
D
NC
VSSQ
VDDQ
NC
VSSQ
VDDQ
VSSQ
VDDAQ
DQ
VSSQ
VDDQ
NC
DQ
D
DQ
D
DQA
NC
NC
DQPD
DQP
A
NC
NC
100-pin TQFP (2 Chip Enables) (AJ Version)
DQP
C
DQP
B
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A
1
80
DQC
C
DQB
B
NC
2
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ
DQ
NC
NC
3
VDDQ
VDDQ
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
VSSQ
VSSQ
5
DQ
DQ
DQ
DQ
C
C
C
C
DQ
DQ
DQ
DQ
B
B
B
B
6
NC
DQP
A
7
DQ
B
B
DQ
A
A
8
DQ
DQ
9
VSSQ
VDDQ
VSSQ
VDDBQ
DQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSSQ
VSSQ
VDDAQ
DQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQ
C
C
DQ
B
B
DQ
DQ
B
DQ
DQ
A
NC
VDD
NC
VSS
NC
VDD
ZZ
NC
VDD
NC
VSS
NC
VDD
ZZ
CY7C1362B
(512K x 18)
CY7C1360B
(256K X 36)
VSDS
VSBS
DQ
DQ
A
DQ
DQ
A
A
DQ
D
DQA
DQ
B
DQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
DQ
DQ
DQ
DQ
D
D
D
D
DQ
DQ
DQ
DQ
A
A
A
A
DQ
B
B
DQ
DQ
NC
NC
A
A
DQ
DQP
B
NC
VSSQ
VDDQ
NC
VSSQ
VDDQ
VSSQ
VDDAQ
DQ
VSSQ
VDDQ
NC
DQD
D
DQ
DQA
NC
NC
DQP
D
DQP
A
NC
NC
Document #: 38-05291 Rev. *C
Page 3 of 34
CY7C1360B
CY7C1362B
Pin Configurations (continued)
119-ball BGA (2 Chip Enables with JTAG)
CY7C1360B (256K x 36)
1
2
3
4
5
6
7
A
B
C
VDDQ
A
A
A
A
VDDQ
ADSP
ADSC
VDD
NC
NC
CE2
A
A
A
A
A
A
A
NC
NC
D
E
F
DQC
DQC
VDDQ
DQPC
DQC
DQC
VSS
VSS
VSS
NC
CE1
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQB
VDDQ
OE
G
H
J
DQC
DQC
VDDQ
DQD
DQD
VDDQ
DQD
DQC
DQC
VDD
BWC
VSS
NC
BWB
VSS
NC
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
ADV
GW
VDD
CLK
NC
BWE
A1
K
DQD
VSS
VSS
DQD
DQD
DQD
L
M
N
BWD
VSS
VSS
BWA
VSS
VSS
P
R
DQD
NC
DQPD
A
VSS
MODE
A0
VDD
VSS
NC
DQPA
A
DQA
NC
NC
VDDQ
NC
TMS
A
TDI
A
TCK
A
TDO
NC
NC
ZZ
VDDQ
T
U
CY7C1362B (512K x 18)
2
A
CE2
A
NC
DQB
NC
1
3
A
A
4
5
A
A
6
A
A
7
A
B
C
D
E
F
VDDQ
NC
NC
DQB
NC
VDDQ
VDDQ
NC
NC
NC
DQA
VDDQ
ADSP
ADSC
VDD
NC
CE1
A
A
A
VSS
VSS
VSS
VSS
VSS
VSS
DQPA
NC
DQA
OE
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
VSS
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
BWB
VSS
NC
ADV
GW
VDD
K
NC
DQB
VDDQ
DQB
NC
DQB
NC
DQB
NC
DQPB
VSS
VSS
VSS
VSS
VSS
CLK
NC
BWE
A1
VSS
NC
DQA
NC
DQA
NC
DQA
NC
VDDQ
NC
DQA
L
M
N
P
BWA
VSS
VSS
VSS
A0
NC
NC
A
A
MODE
A
VDD
NC
NC
A
A
A
NC
ZZ
R
T
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Document #: 38-05291 Rev. *C
Page 4 of 34
CY7C1360B
CY7C1362B
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable with JTAG)
CY7C1360B (256K x 36)
1
NC / 288M
NC
DQPC
DQC
2
3
4
5
6
7
8
9
10
11
NC
NC / 144M
DQPB
DQB
A
A
B
C
D
E
F
G
H
J
K
L
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
A
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
NC
DQC
DQC
DQC
DQC
VSS
DQD
DQD
DQD
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
DQB
DQB
DQB
DQB
NC
DQA
DQA
DQA
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQC
DQC
NC
DQD
DQD
DQD
DQB
DQB
ZZ
DQA
DQA
DQA
VDDQ
VDDQ
VDDQ
DQD
DQPD
NC
DQD
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC / 18M
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1362B (512K x 18)
1
NC / 288M
NC
2
3
CE1
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
4
BWB
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
5
6
7
8
9
10
11
A
A
NC
A
A
CE
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADSC
OE
VSS
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
3
A
NC
DQB
DQB
DQB
DQB
VSS
NC
NC
NC
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
NC
NC
NC
NC
NC
NC / 144M
DQPA
DQA
B
C
D
E
F
G
H
J
K
L
NC
NC
NC
NC
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQA
DQA
DQA
ZZ
NC
NC
NC
NC
DQB
DQB
DQB
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
DQB
DQPB
NC
NC
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC / 18M
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
MODE NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05291 Rev. *C
Page 5 of 34
CY7C1360B
CY7C1362B
CY7C1360B–Pin Definitions
TQFP
3-Chip
Enable
TQFP
2-Chip
Enable
Name
BGA
fBGA
I/O
Description
Address Inputs used to select one of the 256K
A0, A1, A
37,36,32, 37,36,32,
33,34,35, 33,34,35,
43,44,45, 44,45,46,
46,47,48, 47,48,49,
P4,N4, R6,P6,A2,
Input-
A2,C2,
A10,B2, Synchronous address locations. Sampled at the rising edge of
R2,3A, B10,P3,P4,
B3,C3, P8,P9,P10,
the CLK if
or
is active LOW, and CE ,
ADSP ADSC
CE2, and CE3[2]are sampled active. A1, A0 are fe1d
49,50,81, 50,81,82, T3,T4,A5, P11,R3,R4,
82,99,100 92,99,100 B5,C5, R8,R9,R10,
to the two-bit counter.
.
T5,A6,B6,
C6,R6
R11
93,94,95, 93,94,95,
L5,G5,
G3,L3
B5,A5,A4,
B4
Input-
Byte Write Select Inputs, active LOW. Qualified
with BWE to conduct Byte Writes to the SRAM.
Sampled on the rising edge of CLK.
BWA,BWB
BWC,BWD
96
96
Synchronous
H4
B7
Input-
Global Write Enable Input, active LOW. When
88
88
GW
Synchronous asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written,
regardless of the values on BWX and BWE).
87
89
87
89
M4
K4
A7
B6
Input-
Byte Write Enable Input, active LOW. Sampled
BWE
CLK
Synchronous on the rising edge of CLK. This signal must be as-
serted LOW to conduct a Byte Write.
Input-
Clock
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a
burst operation.
98
98
E4
A3
Input-
Chip Enable 1 Input, active LOW. Sampled on the
CE1
CE2
Synchronous rising edge of CLK. Used in conjunction with CE2
and CE3[2] to select/deselect the device. ADSP is
ignored if CE1 is HIGH.
97
92
97
-
B2
-
B3
A6
Input-
Chip Enable 2 Input, active HIGH. Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE1 and CE3[2] to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the
[2]
CE3
Synchronous rising edge of CLK. Used in conjunction with CE1
andCE2 toselect/deselectthedevice. Notavailable
for AJ package version.
Not connected for BGA.
Where referenced, CE3[2] is assumed active
throughout this document for BGA.
86
83
86
83
F4
B8
A9
Input-
Output Enable, asynchronous input, active
OE
Asynchro- LOW. Controls the direction of the I/O pins. When
nous
LOW, the I/O pins behave as outputs. When
deassertedHIGH, I/Opinsarethree-stated, andact
as input data pins. OE is masked during the first
clock of a read cycle when emerging from a
deselected state.
G4
Input-
Advance Input signal, sampled on the rising
ADV
Synchronous edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
Document #: 38-05291 Rev. *C
Page 6 of 34
CY7C1360B
CY7C1362B
CY7C1360B–Pin Definitions (continued)
TQFP
3-Chip
Enable
TQFP
2-Chip
Enable
Name
ADSP
BGA
fBGA
I/O
Description
Address Strobe from Processor, sampled on
84
84
A4
B9
Input-
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A1, A0 are
also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE1 is deasserted HIGH.
85
64
B4
T7
A8
Input-
AddressStrobefromController, sampledonthe
85
64
ADSC
ZZ
Synchronous rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are
captured in the address registers. A1, A0 are also
loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
H11
Input-
ZZ “Sleep” Input, active HIGH. When asserted
Asynchro- HIGH places the device in a non-time-critical
nous
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
52,53,56, 52,53,56,
57,58,59, 57,58,59,
62,63,68, 62,63,68,
69,72,73, 69,72,73,
74,75,78, 74,75,78,
K6,L6,
M6,N6,
K7,L7,
N7,P7,
E6,F6,
M11,L11,
I/O-
Bidirectional Data I/O lines. As inputs, they feed
DQs,
K11,J11, Synchronous into an on-chip data register that is triggered by the
DQPs
J10,K10,
L10,M10,
D10,E10,
F10,G10,
D11,E11,
F11,G11,
D1,E1,F1,
risingedge of CLK. As outputs, they deliver the data
contained in the memory location specified by the
addresses presented during the previous
clock rise
79,2,3,6,7, 79,2,3,6,7, G6,H6,
8,9,12,13,1 8,9,12,13,1 D7,E7,
of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and
DQPX are placed in a three-state condition.
8,19,22,
8,19,22,
G7,H7,
D1,E1,
23,24,25, 23,24,25,
28,29,51, 28,29,51,
G1,H1, G1,D2,E2,
80,1,30
80,1,30
E2,F2,
F2,G2,J1,
G2,H2, K1,L1,M1,
K1,L1,
N1,P1,
J2,K2,L2,
M2,N11,
K2,L2, C11,C1,N1
M2,N2,
P6,D6,
D2,P2
VDD
15,41,65, 15,41,65, J2,C4,J4, D4,D8,E4, PowerSupply Power supply inputs to the core of the device.
91
91
R4,J6
E8,F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
VSS
17,40,67, 17,40,67,
90 90
D3,E3, C4,C5,C6,
F3,H3, C7,C8,D5,
K3,M3, D6,D7,E5,
Ground
Ground for the core of the device.
N3,P3,
D5,E5,
E6,E7,F5,
F6,F7,G5,
F5,H5, G6,G7,H2,
K5,M5, H5,H6,H7,J
N5,P5
5,J6,J7,
K5,K6,K7,
L5,L6,L7,
M5,M6,M7,
N4,N8
Document #: 38-05291 Rev. *C
Page 7 of 34
CY7C1360B
CY7C1362B
CY7C1360B–Pin Definitions (continued)
TQFP
3-Chip
Enable
TQFP
2-Chip
Enable
Name
VSSQ
BGA
fBGA
I/O
Description
5,10,21,26, 5,10,21,26,
55,60,71, 55,60,71,
-
-
I/O Ground Ground for the I/O circuitry.
76
76
VDDQ
4,11,20,27, 4,11,20,27, A1,F1,J1, C3,C9,D3,
I/O Power Power supply for the I/O circuitry.
54,61,70, 54,61,70,
M1,U1, D9,E3,E9,F
A7,F7,J7, 3,F9,G3,
Supply
77
77
M7,U7
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
MODE
31
31
R3
R1
Input-
Static
Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is
a strap pin and should remain static during device
operation. Mode pin has an internal pull-up.
TDO
TDI
-
-
-
-
-
-
-
-
U5
U3
U2
U4
P7
P5
R5
R7
JTAG serial Serial data-out to the JTAG circuit. Delivers data
output
on the negative edge of TCK. If the JTAG feature is
Synchronous not being utilized, this pin should be disconnected.
This pin is not available on TQFP packages.
JTAG serial Serial data-In to the JTAG circuit. Sampledonthe
input
rising edge of TCK. If the JTAG feature is not being
Synchronous utilized, this pin can be disconnected or connected
to VDD. This pin is not available on TQFP packages.
TMS
TCK
NC
JTAG serial Serial data-In to the JTAG circuit. Sampledonthe
input
rising edge of TCK. If the JTAG feature is not being
Synchronous utilized, this pin can be disconnected or connected
to VDD. This pin is not available on TQFP packages.
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to VSS. This pin is not available on TQFP
packages.
14,16,66, 14,16,38,
B1,C1, A11,B1,C2,
-
No Connects. Not internally connected to the die
42,39,38 39,42,43, R1,T1,T2, C10,H1,H3,
66,
J3,D4,
H9,H10,
L4,5J,5R, N2,N5,N7,
6T,6U, N10,P1,A1,
B7,C7, B11,P2,R2,
R7
N6
Document #: 38-05291 Rev. *C
Page 8 of 34
CY7C1360B
CY7C1362B
CY7C1362B–Pin Definitions
TQFP
3-Chip
Enable
TQFP
2-Chip
Enable
Name
BGA
fBGA
I/O
Description
Address Inputs used to select one of the 512K
A0, A1, A 37,36,32, 37,36,32,
33,34,35, 33,34,35,
43,44,45, 44,45,46,
46,47,48, 47,48,49,
49,50,80, 50,80,81,
81,82,99, 82,92,99,
P4,N4,
A2,C2,
R6,P6,A2,
Input-
A10,A11, Synchronous address locations. Sampled at the rising edge of
R2,T2, B2,B10,P3,
the CLK if
or
is active LOW, and CE ,
ADSP ADSC
A3,B3,
C3,T3,
A5,B5,
C5,T5,
A6,B6,
C6,R6,
T6
P4,P8,P9,
P10,P11,
R3,R4,R8,
R9,R10,
R11
CE2, andCE3[2] are sampled active. A1, A0 are fe1d
to the two-bit counter.
.
100
100
93,94
88
93,94
88
G3,L5
B5,A4
B7
Input-
Byte Write Select Inputs, active LOW. Qualified
BWA,BWB
GW
Synchronous
with BWE to conduct Byte Writes to the SRAM.
.
Sampled on the rising edge of CLK
H4
Input-
Global Write Enable Input, active LOW. When
Synchronous asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written,
regardless of the values on BWX and BWE).
87
89
87
89
M4
K4
A7
B6
Input-
Byte Write Enable Input, active LOW. Sampled
BWE
CLK
Synchronous on the rising edge of CLK. This signal must be
asserted LOW to conduct a Byte Write.
Input-
Clock
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during
a burst operation.
98
98
E4
A3
Input-
Chip Enable 1 Input, active LOW. Sampled on
CE1
CE2
Synchronous the rising edge of CLK. Used in conjunction with
CE2 and CE3[2] to select/deselect the device.
ADSP is ignored if CE1 is HIGH.
97
92
97
-
B2
-
B3
A6
Input-
Chip Enable 2 Input, active HIGH. Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE1 and CE3[2] to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on
[2]
CE3
Synchronous the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. Not
available for AJ package version.
Not connected
for BGA. Where referenced, CE3[2] is assumed
active throughout this document for BGA.
86
83
86
83
F4
B8
A9
Input-
Output Enable, asynchronous input, active
OE
Asynchronous LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and
act as input data pins. OE is masked during the first
clock of a Read cycle when emerging from a
deselected state.
G4
Input-
Advance Input signal, sampled on the rising
ADV
Synchronous edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
Document #: 38-05291 Rev. *C
Page 9 of 34
CY7C1360B
CY7C1362B
CY7C1362B–Pin Definitions (continued)
TQFP
3-Chip
Enable
TQFP
2-Chip
Enable
Name
ADSP
BGA
fBGA
I/O
Description
Address Strobe from Processor, sampled on
84
84
A4
B9
Input-
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A1, A0 are
also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE1 is deasserted
HIGH.
85
64
P4
T7
A8
Input-
Address Strobe from Controller, sampled on
85
64
ADSC
ZZ
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A1, A0 are
also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recog-
nized.
H11
Input-
ZZ “Sleep” Input, active HIGH. When asserted
Asynchronous HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
58,59,62, 58,59,62,
63,68,69, 63,68,69,
P7,K7,
G7,E7,
J10,K10,
I/O-
Bidirectional Data I/O lines. As inputs, they feed
DQs,
L10,M10, Synchronous into an on-chip data register that is triggered by the
DQPs
72,73,8,9, 72,73,8,9, F6,H6,L6, D11,E11,
rising edge of CLK. As outputs, they deliver the
data contained in the memory location specified by
12,13,18, 12,13,18,
19,22,23, 19,22,23,
N6,D1, F11,G11,J1,
H1,L1, K1,L1,M1,D
the addresses presented during the previous
clock
74,24
74,24
N1,E2,
2,E2,F2,
rise of the a Read cycle. The direction of the pins
is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and
DQPX are placed in a three-state condition.
G2,K2, G2,C11,N1
M2,D6,
P2
VDD
15,41,65, 15,41,65, C4,J2,J4, D4,D8,E4,E Power Supply Power supply inputs to the core of the device.
91
91
J6,R4
8,F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
VSS
17,40,67, 17,40,67,
90 90
D3,D5,
H2,C4,C5,
Ground
Ground for the core of the device.
E5,E3,F3, C6,C7,C8,
F5,G5, D5,D6,D7,E
H3,H5,
5,E6,E7,
K3,K5,L3, F5,F6,F7,
M3,M5, G5,G6,G7,
N3,N5, H5,H6,H7,J
P3,P5
-
5,J6,J7,
K5,K6,K7,
L5,L6,L7,
M5,M6,M7,
N4,N8
VSSQ
5,10,21,26, 5,10,21,26,
55,60,71, 55,60,71,
-
I/O Ground Ground for the I/O circuitry.
76
76
Document #: 38-05291 Rev. *C
Page 10 of 34
CY7C1360B
CY7C1362B
CY7C1362B–Pin Definitions (continued)
TQFP
3-Chip
Enable
TQFP
2-Chip
Enable
Name
VDDQ
BGA
fBGA
I/O
Description
4,11,20,27, 4,11,20,27, A1,A7,F1, C3,C9,D3,
54,61,70, 54,61,70, F7,J1,J7, D9,E3,E9,
I/O Power Power supply for the I/O circuitry.
Supply
77
31
-
77
31
-
M1,M7,
U1,U7
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
MODE
TDO
TDI
R3
U5
U3
U2
R1
P7
P5
R5
Input-
Static
Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is
a strap pin and should remain static during device
operation. Mode pin has an internal pull-up.
JTAG serial Serial data-out to the JTAG circuit. Delivers data
output
on the negative edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin should be left uncon-
nected. This pin is not available on TQFP
packages.
-
-
JTAG serial Serial data-In to the JTAG circuit. Sampled on
input
the rising edge of TCK. If the JTAG feature is not
Synchronous being utilized, this pin can be left floating or con-
nected to VDD through a pull-up resistor. This pin
is not available on TQFP packages.
TMS
-
-
JTAG serial Serial data-In to the JTAG circuit. Sampled on
input
the rising edge of TCK. If the JTAG feature is not
Synchronous being utilized, this pin can be disconnected or con-
nected to VDD. This pin is not available on TQFP
packages.
TCK
NC
-
-
U4
R7
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to VSS. This pin is not available on
TQFP packages.
1,2,3,6,7, 1,2,3,6,7,
14,16,25, 14,16,25,
28,29,30, 28,29,30,
38,39,42, 38,39,42,
51,52,53, 43,51,52,
56,57,66, 53,56,57,
75,78,79, 66,75,78,
B1,B7,
A5,B1,B4,
-
No Connects. Not internally connected to the die.
C1,C7, C1,C2,C10,
D2,D4,
D1,D10,
D7,E1, E1,E10,F1,
E6,H2,
F10,G1,
F2,G1, G10,H1,H3,
G6,H7, H9,H10,J2,
79,95,96 J3,J5,K1, J11,K2,
95,96
K6,L4,L2, K11,L2,L1,
L7,M6,
M2,M11,
N2,L7,P1, N2,N7,N10,
P6,R1, N5,N11,P1,
R5,R7, A1,B11,P2,
T1,T4,U6
R2,N6
Document #: 38-05291 Rev. *C
Page 11 of 34
CY7C1360B
CY7C1362B
then the Write operation is controlled by BWE and BWX
signals. The CY7C1360B/CY7C1362B provides Byte Write
capability that is described in the Write Cycle Descriptions
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BWX) input, will selectively write to only
the desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
Write mechanism has been provided to simplify the Write
operations.
Because the CY7C1360B/CY7C1362B is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 3.0 ns
(200-MHz device).
The CY7C1360B/CY7C1362B supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3[2] are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BWX) are asserted active to conduct a Write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
Because the CY7C1360B/CY7C1362B is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
[2]
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if
CE1 is HIGH. The address presented to the address inputs
(A) is stored into the address advancement logic and the
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 3.0 ns (200-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always three-stated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will three-state immediately.
Burst Sequences
The CY7C1360B/CY7C1362B provides a two-bit wraparound
counter, fed by A1, A0, that implements either an interleaved
or linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel Pentium applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Single Write Accesses Initiated by ADSP
Sleep Mode
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
[2]
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
“sleep” mode. CE1, CE2, CE3[2], ADSP, and ADSC must
the
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Document #: 38-05291 Rev. *C
Page 12 of 34
CY7C1360B
CY7C1362B
Interleaved Burst Address Table
(MODE = Floating or VDD
Linear Burst Address Table
(MODE = GND)
)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
First
Address
A1, A0
Second
Address
A1, A0
Third
Fourth
Address
A1, A0
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
35
2tCYC
Unit
mA
ns
ns
ns
2tCYC
0
2tCYC
tRZZI
ns
Document #: 38-05291 Rev. *C
Page 13 of 34
CY7C1360B
CY7C1362B
Truth Table[3, 4, 5, 6, 7, 8]
Operation
Add. Used
None
CE2
X
L
X
L
CE3
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
WRITE
CLK
DQ
CE1
H
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
ZZ ADSP ADSC ADV
OE
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Snooze Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
H
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
None
None
None
None
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
L-H
Three-State
Q
External
External
External
External
External
Next
Next
Next
Next
Next
L
L-H Three-State
L-H
L-H
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
D
Q
L-H Three-State
L-H
L-H Three-State
L-H
L-H Three-State
L-H
L-H
L-H
L-H Three-State
L-H
L-H Three-State
L-H
L-H
Q
L
L
L
L
Q
D
D
Q
Next
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
Q
D
D
WRITE Cycle, Suspend Burst
L
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
6. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .
1
2
3
1
2
X
after the
or with the assertion of
. As a result,
must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state.
is
OE
ADSC
OE
ADSP
a don't care for the remainder of the Write cycle
8.
is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE
OE
is
.
is active (LOW)
inactive or when the device is deselected, and all data bits behave as output when
OE
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
is valid. Appropriate write will be done based on which byte write is active.
[A:D]
Document #: 38-05291 Rev. *C
Page 14 of 34
CY7C1360B
CY7C1362B
Partial Truth Table for Read/Write[5, 9]
Function (CY7C1360B)
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BWC
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
BWB
X
H
H
L
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
GW
BWE
Read
Read
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write Byte C – (DQC and DQPC)
Write Bytes C, A
L
H
H
L
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
H
H
L
L
H
H
L
L
X
L
X
Write All Bytes
X
Truth Table for Read/Write[5]
Function (CY7C1362B)
BWB
X
H
H
L
L
L
X
BWA
GW
BWE
Read
Read
H
H
L
L
L
L
L
X
X
H
L
H
L
L
X
H
H
H
H
H
L
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write All Bytes
Write All Bytes
Document #: 38-05291 Rev. *C
Page 15 of 34
CY7C1360B
CY7C1362B
Test MODE SELECT (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1360B/CY7C1362B incorporates a serial boundary
scan test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These functions
from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of
the SRAM. Note that the TAP controller functions in a manner
that does not conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure .
TDI is internally pulled up and can be unconnected if the TAP
is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1360B/CY7C1362B contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
TEST-LOGIC
1
RESET
0
2
1
0
0
0
1
1
1
Selection
Circuitry
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
Instruction Register
31 30 29
Identification Register
0
Selection
TDI
TDO
Circuitr
y
0
0
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Test Access Port (TAP)
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05291 Rev. *C
Page 16 of 34
CY7C1360B
CY7C1362B
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The SRAM has a 71-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
SAMPLE/PRELOAD
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold time (tCS plus tCH).
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
Document #: 38-05291 Rev. *C
Page 17 of 34
CY7C1360B
CY7C1362B
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Clock
tTCYC
tTF
tTH
tTL
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
25
25
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
5
ns
ns
0
5
5
5
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Notes:
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1ns.
R
F
Document #: 38-05291 Rev. *C
Page 18 of 34
CY7C1360B
CY7C1362B
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ........ ........................................VSS to 3.3V
Input rise and fall times..................... ..............................1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels................... ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
ZO= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[12]
Parameter
VOH1
Description
Output HIGH Voltage IOH = –4.0 mA
Conditions
VDDQ = 3.3V
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
I
OH = –1.0 mA
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage IOH = –100 µA
Output LOW Voltage IOL = 8.0 mA
0.4
0.4
0.2
I
OL = 8.0 mA
Output LOW Voltage IOL = 100 µA
VDDQ = 2.5V
0.2
Input HIGH Voltage
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
2.0
1.7
–0.5
–0.3
–5
VDD + 0.3
VDD + 0.3
0.7
VIL
Input LOW Voltage
VDDQ = 2.5V
0.7
5
IX
Input Load Current
GND < VIN < VDDQ
µA
Note:
12. All voltages referenced to V (GND).
SS
Document #: 38-05291 Rev. *C
Page 19 of 34
CY7C1360B
CY7C1362B
Identification Register Definitions
CY7C1360B
CY7C1362B
(512KX18)
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
(256KX36)
001
Description
Describes the version number
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
001
01010
01010
000000
010110
Device Width (23:18)
000000
100110
00000110100
1
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
00000110100 Allows unique identification of SRAM vendor
1
Indicates the presence of an ID register
Scan Register Sizes
Bit Size(x36)
Register Name
Bit Size(x18)
Instruction
Bypass
3
1
3
1
ID
32
71
32
71
Boundary Scan Order
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
011
100
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05291 Rev. *C
Page 20 of 34
CY7C1360B
CY7C1362B
119-Ball BGA Boundary Scan Order
CY7C1360B (256K x 36)
CY7C1362B (512K x 18)
BIT
#
BALL
ID
Signal
Name
BIT
#
BALL
ID
Signal
Name
BIT# BALL ID
Signal
Name
BIT# BALL ID
Signal
Name
1
CLK
GW
BWE
OE
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
P4
N4
R6
T5
A0
A1
1
CLK
GW
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
P4
N4
A0
A1
K4
H4
M4
F4
B4
A4
G4
C3
B3
D6
H7
G6
E6
D7
E7
F6
G7
H6
T7
K7
L6
K4
H4
2
2
3
A
3
M4
BWE
OE
R6
A
4
A
4
F4
T5
A
5
ADSC
ADSP
ADV
A
T3
A
5
B4
ADSC
ADSP
ADV
A
T3
A
6
R2
R3
P2
A
6
A4
R2
A
7
MODE
DQPD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
7
G4
R3
MODE
Internal
Internal
Internal
Internal
DQPB
DQB
8
8
C3
Internal
Internal
Internal
Internal
P2
9
A
P1
9
B3
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
ZZ
L2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
T2
A
K1
Internal
Internal
Internal
D6
Internal
Internal
Internal
DQPA
DQA
DQA
DQA
DQA
ZZ
N2
N1
M2
L1
N1
M2
DQB
E7
L1
DQB
K2
F6
K2
DQB
Internal
H1
G2
E2
G7
Internal
H1
Internal
DQB
H6
T7
G2
DQB
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
K7
DQA
DQA
DQA
DQA
Internal
Internal
Internal
Internal
Internal
A
E2
DQB
D1
H2
G1
F2
L6
D1
DQB
N6
P7
N7
M6
L7
N6
Internal
Internal
Internal
Internal
Internal
C2
Internal
Internal
Internal
Internal
Internal
A
P7
Internal
Internal
Internal
Internal
Internal
T6
E1
D2
C2
A2
K6
P6
T4
A3
C5
B5
A5
C6
A6
B6
A
A2
A
E4
CE1
CE2
BWD
BWC
BWB
BWA
Internal
E4
CE1
A
B2
A3
A
B2
CE2
A
L3
C5
A
Internal
Internal
G3
Internal
Internal
BWB
BWA
Internal
A
G3
G5
L5
B5
A
A
A5
A
A
C6
A
L5
A
Internal
A6
A
Internal
A
B6
A
Document #: 38-05291 Rev. *C
Page 21 of 34
CY7C1360B
CY7C1362B
165-Ball fBGA Boundary Scan Order
CY7C1360B (256K x 36)
CY7C1362B (512K x 18)
BIT#
BALL
ID
Signal
Name
BIT#
BALL
ID
Signal
Name
BIT#
BALL
ID
Signal
Name
BIT# BALL ID
Signal
Name
1
B6
B7
CLK
GW
BWE
OE
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
R6
P6
R4
P4
R3
P3
R1
N1
L2
A0
A1
1
B6
B7
CLK
GW
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
R6
P6
A0
A1
2
2
3
A7
A
3
A7
BWE
OE
R4
A
4
B8
A
4
B8
P4
A
5
A8
ADSC
ADSP
ADV
A
A
5
A8
ADSC
ADSP
ADV
A
R3
A
6
B9
A
6
B9
P3
A
7
A9
MODE
DQPD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
7
A9
R1
MODE
Internal
Internal
Internal
Internal
DQPB
DQB
8
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
P10
R9
8
B10
Internal
Internal
Internal
Internal
N1
9
A
9
A10
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
ZZ
K2
J2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A11
A
Internal
Internal
Internal
C11
Internal
Internal
Internal
DQPA
DQA
DQA
DQA
DQA
ZZ
M2
M1
L1
M1
L1
DQB
K1
J1
D11
K1
DQB
E11
J1
DQB
Internal
G2
F2
F11
Internal
G2
Internal
DQB
G11
H11
F2
DQB
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
E2
D2
G1
F1
J10
DQA
DQA
DQA
DQA
Internal
Internal
Internal
Internal
Internal
A
E2
DQB
K10
D2
DQB
L10
Internal
Internal
Internal
Internal
Internal
B2
Internal
Internal
Internal
Internal
Internal
A
M10
Internal
Internal
Internal
Internal
Internal
R11
E1
D1
C1
B2
A2
A3
B3
B4
A4
A5
B5
A6
A
A2
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
A3
CE1
A
R10
P10
A
B3
CE2
A
A
Internal
Internal
A4
Internal
Internal
BWB
BWA
CE3
A
R9
A
P9
A
P9
A
R8
A
R8
A
B5
P8
A
P8
A
A6
P11
A
P11
A
Document #: 38-05291 Rev. *C
Page 22 of 34
CY7C1360B
CY7C1362B
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Operating Range
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
in Three-State ..................................... –0.5V to VDDQ + 0.5V
to VDD
Industrial
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range[13, 14]
Parameter
VDD
VDDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
VDD
Unit
V
V
VDDQ = 3.3V
VDDQ = 2.5V
2.625
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
V
V
V
V
V
V
V
V
µA
2.0
Output LOW Voltage
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
V
DDQ = 2.5V, VDD = Min., IOL = 1.0 mA
Input HIGH Voltage[13] VDDQ = 3.3V
2.0
1.7
–0.3
–0.3
–5
VDDQ = 2.5V
Input LOW Voltage[13]
VDDQ = 3.3V
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
0.7
5
Input Load Current
except ZZ and MODE
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
µA
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
30
5
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
All speeds
250
220
180
50
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
ISB4
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≥ VIH or VIN ≤ VIL
Current—TTL Inputs
f = fMAX = 1/tCYC
Automatic CE
VDD = Max, Device Deselected,
All speeds
30
50
40
mA
mA
mA
Power-down
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
Automatic CE
VDD = Max, Device Deselected, or All speeds
Power-down
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX = 1/tCYC
Automatic CE
VDD = Max, Device Deselected,
All Speeds
Power-down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
13. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
14. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
Power-up
DD
IH
DD
DDQ
Document #: 38-05291 Rev. *C
Page 23 of 34
CY7C1360B
CY7C1362B
Thermal Resistance[15]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard
test methods and procedures
for measuring thermal
25
25
27
°C/W
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
9
6
6
°C/W
impedance, per EIA / JESD51.
Capacitance[15]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
5
5
5
5
5
7
5
5
7
VDD = 3.3V.
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
V
DDQ = 2.5V
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDD
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDD
90%
10%
Z = 50Ω
0
10%
L
GND
≤ 1 ns
5 pF
R =1538Ω
≤ 1 ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
15. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05291 Rev. *C
Page 24 of 34
CY7C1360B
CY7C1362B
Switching Characteristics Over the Operating Range[16, 17]
225 MHz
200 MHz
166 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
Min.
1
Max
Min.
1
Max
Min.
1
Max
Unit
ms
VDD(Typical) to the First Access[18]
Clock Cycle Time
Clock HIGH
4.4
1.8
1.8
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
Clock LOW
Output Times
tCO
tDOH
tCLZ
tCHZ
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z[19, 20, 21]
2.8
3.0
3.5
ns
ns
ns
ns
ns
ns
ns
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
Clock to High-Z[19, 20, 21]
2.8
2.8
3.0
3.0
3.5
3.5
tOEV
OE LOW to Output Valid
LOW to Output Low-Z[19, 20, 21]
OE
tOELZ
tOEHZ
Set-up Times
tAS
tADS
tADVS
tWES
0
0
0
OE HIGH to Output High-Z[19, 20, 21]
2.8
3.0
3.5
Address Set-up before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
,
ADSC ADSP Set-up before CLK Rise
ADV Set-up before CLK Rise
Set-up before CLK Rise
GW, BWE, BWX
tDS
tCES
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
Hold Times
tAH
tADH
tADVH
tWEH
tDH
Address Hold after CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
,
Hold after CLK Rise
ADSP ADSC
ADV Hold after CLK Rise
,
,
GW BWE BWX Hold after CLK Rise
Data Input Hold after CLK Rise
tCEH
Chip Enable Hold after CLK Rise
Shaded areas contain advance information.
Notes:
16. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation
DD
POWER
19. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
20. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
21. This parameter is sampled and not 100% tested.
Document #: 38-05291 Rev. *C
Page 25 of 34
CY7C1360B
CY7C1362B
Switching Waveforms
Read Cycle Timing[22]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
OELZ
t
CHZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
22. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05291 Rev. *C
Page 26 of 34
CY7C1360B
CY7C1362B
Switching Waveforms(continued)
Write Cycle Timing[22, 23]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
ADDRESS
BWE,
t
t
AH
AS
A1
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
23.
Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05291 Rev. *C
Page 27 of 34
CY7C1360B
CY7C1362B
Switching Waveforms(continued)
Read/Write Cycle Timing[22, 24, 25]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE,
t
t
WEH
WES
BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes:
24.
.
The data bus (Q) remains in high-Z following a Write cycle, unless a new Read access is initiated by
ADSP or ADSC
25. GW is HIGH.
Document #: 38-05291 Rev. *C
Page 28 of 34
CY7C1360B
CY7C1362B
Switching Waveforms(continued)
ZZ Mode Timing [26, 27]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
27. DQs are in High-Z when exiting ZZ sleep mode.
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Part and Package Type
225
CY7C1360B-225AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Commercial
CY7C1362B-225AC
3 Chip Enables
CY7C1360B-225AI
CY7C1362B-225AI
Industrial
CY7C1360B-225AJC
CY7C1362B-225AJC
CY7C1360B-225AJI
CY7C1362B-225AJI
CY7C1360B-225BGC
CY7C1362B-225BGC
CY7C1360B-225BGI
CY7C1362B-225BGI
CY7C1360B-225BZC
CY7C1362B-225BZC
CY7C1360B-225BZI
CY7C1362B-225BZI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Commercial
Industrial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and Commercial
JTAG
Industrial
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) Commercial
3 Chip Enables and JTAG
Industrial
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
Document #: 38-05291 Rev. *C
Page 29 of 34
CY7C1360B
CY7C1362B
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Part and Package Type
200
CY7C1360B-200AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Commercial
CY7C1362B-200AC
3 Chip Enables
CY7C1360B-200AI
CY7C1362B-200AI
Industrial
CY7C1360B-200AJC
CY7C1362B-200AJC
CY7C1360B-200AJI
CY7C1362B-200AJI
CY7C1360B-200BGC
CY7C1362B-200BGC
CY7C1360B-200BGI
CY7C1362B-200BGI
CY7C1360B-200BZC
CY7C1362B-200BZC
CY7C1360B-200BZI
CY7C1362B-200BZI
CY7C1360B-166AC
CY7C1362B-166AC
CY7C1360B-166AI
CY7C1362B-166AI
CY7C1360B-166AJC
CY7C1362B-166AJC
CY7C1360B-166AJI
CY7C1362B-166AJI
CY7C1360B-166BGC
CY7C1362B-166BGC
CY7C1360B-166BGI
ICY7C1362B-166BGI
CY7C1360B-166BZC
CY7C1362B-166BZC
CY7C1360B-166BZI
CY7C1362B-166BZI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Commercial
Industrial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and Commercial
JTAG
Industrial
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) Commercial
3 Chip Enables and JTAG
Industrial
166
A101
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
Industrial
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Commercial
Industrial
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and Commercial
JTAG
Industrial
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) Commercial
3 Chip Enables and JTAG
Industrial
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
Document #: 38-05291 Rev. *C
Page 30 of 34
CY7C1360B
CY7C1362B
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05291 Rev. *C
Page 31 of 34
CY7C1360B
CY7C1362B
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05291 Rev. *C
Page 32 of 34
CY7C1360B
CY7C1362B
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05291 Rev. *C
Page 33 of 34
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypressproductsarenotwarrantednorintendedtobeusedformedical, life-support, life-saving, criticalcontrolorsafetyapplications, unlesspursuanttoanexpresswrittenagreementwithCypress.
CY7C1360B
CY7C1362B
Document History Page
Document Title: CY7C1360B/CY7C1362B 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Document #: 38-05291 Rev. *C
Orig. of
REV.
**
*A
*B
*C
ECN NO. Issue Date Change
Description of Change
114766
117939
205060
225181
08/08/02
08/20/02
See ECN
See ECN
RCS
RCS
NJY
VBL
New Data Sheet
Added A0 and A1 to 165 fBGA pinout
Final Data Sheet
Update Ordering Info section: shade S,E part numbers
Document #: 38-05291 Rev. *C
Page 34 of 34
相关型号：
CY7C1360A-150ACT
Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
CY7C1360A-150ACT
Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
ROCHESTER
CY7C1360A-150BGCT
Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
ROCHESTER
CY7C1360A-150BGCT
Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CYPRESS
CY7C1360A-150BGI
Cache SRAM, 256KX36, 4.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
ROCHESTER
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